On Oxygen Deficiency and Fast Transient Charge-Trapping Effects in High-k Dielectrics

This letter correlates fast transient charging (FTC) in high-k gate dielectrics to variations in its oxygen content. Analysis of electrical and physical data suggests that the observed enhancement of FTC may be caused by reduction of the oxygen content in the high-k film due to O scavenging process induced by the HfSi_x metal electrode. A hypothesis correlating O scavenging from the high-k dielectric to O vacancy formation, which contributes to FTC, is proposed     

高k栅介质的可靠性问题

随着集成电路特征尺寸的不断缩短,利用先进的高k/金属栅堆叠来取代传统的SiO2/多晶硅栅结构成为微电子技术发展的必然,确保这些新的栅极堆叠类型具有足够的可靠性是非常重要的.综述了高k栅介质可靠性的研究现状,阐明了瞬态充电效应导致的阈值电压不可靠问题,对偏压温度不稳定现象(BTI)和高k击穿特性进行了探讨.     

Theoretical and experimental investigation of Si nanocrystal memory device with HfO/sub 2/ high-k tunneling dielectric

In this paper, silicon (Si) nanocrystal memory using chemical vapor deposition (CVD) HfO/sub 2/ high-k dielectrics to replace the traditional SiO/sub 2/ tunneling/control dielectrics has been fabricated and characterized for the first time. The advantages of this approach for improved nanocrystal memory operation have also been studied theoretically. Results show that due to its unique band asymmetry in programming and retention mode, the use of high-k dielectric on Si offers lower electron barrier height at dielectric/Si interface and larger physical thickness, resulting in a much higher J/sub g,programming//J/sub g,retention/ ratio than that in SiO/sub 2/ and therefore faster programming and longer retention. The fabricated device with CVD HfO/sub 2/ shows excellent programming efficiency and data-retention characteristics, thanks to the combination of a lower electron barrier height and a larger physical thickness of HfO/sub 2/ as compared with SiO/sub 2/ of the same electrical oxide thickness (EOT). It also shows clear single-electron charging effect at room temperature and superior data endurance up to 10/sup 6/ write/erase cycles.     

Charging-Effects in RF capacitive switches influence of insulating layers composition

The dielectric charging is one of the major failures reducing the reliability of capacitive switches with electrostatic actuation. Then the control of the charging/discharging processes is a key factor to allow a fast recovering of the dielectric after charging. From transient current measurements on MIM capacitors it is possible to select the best material for RF-MEMS.We have studied different PECVD silicon nitride obtained under low (380 KHz), high (13.56 MHz) or mixed (380kHz/13.56MHz) frequency power supply. The conduction mechanism into the dielectrics has been deduced from current measurements on MIM capacitors. Then the film properties have been studied by infrared measurement in order to identify the chemical bond into the dielectric which can explain the charging behaviour. It was observed that low hydrogen content in the films is in good correlation with electrical quality and kinetic of the charging/discharging processes.     

高k介质在浮栅型非挥发性存储器中的应用

随着微电子技术节点不断向前推进,基于传统浮栅结构的非挥发性存储器(NVM)技术遇到严重的技术难点,其中最主要的问题是SiO2隧穿层已经接近厚度极限,很难继续减薄.作为改进措施,引入高k介质作为新型隧穿层材料.文章介绍了高k材料的研究现状和在NVM器件中应用所取得的进展;最后,对高k介质进一步应用的研究趋势进行了展望.     

Lateral nonuniformity of effective oxide charges in MOS capacitors with Al/sub 2/O/sub 3/ gate dielectrics

The high-frequency Terman's method for interface-trap-density (D/sub it/) extraction is used to examine the lateral nonuniformity (LNU) of effective oxide charges in MOS capacitors. The two-parallel-subcapacitor model is constructed to simulate LNU charges, and it was shown that the value of the found effective D/sub it/ appears negative as the LNU occurs in the gate oxide. This technique was first used to examine the effective oxide charge distribution in Al/sub 2/O/sub 3/ high-k gate dielectrics prepared by anodic oxidation and nitric-acid oxidation. It was found that the LNU effect in Al/sub 2/O/sub 3/ is sensitive to oxidation mechanisms and can be avoided by using an appropriate oxidation process. The proposed technique is useful for the preparation and reliability improvement of high-k gate dielectrics.     

Electrical properties of Ta/sub 2/O/sub 5/ gate dielectric on strained-Si

High dielectric constant (high-k) thin Ta/sub 2/O/sub 5/ films have been deposited on tensilely strained silicon (strained-Si) layers using a microwave plasma enhanced chemical vapour deposition technique at a low temperature. The deposited Ta/sub 2/O/sub 5/ films show good electrical properties as gate dielectrics and are suitable for microelectronic applications. The feasibility of integration of strained-Si and high-k dielectrics has been demonstrated.     

The charging and discharging of high-voltage stress-generated trapsin thin silicon oxide

Excess high-voltage stress-generated low-level leakage currents through 10 nm silicon oxides, previously described as DC currents, are shown to decay to the limit of detection given adequate observation time and, thus, have no discernible component. A physical model is presented which describes the majority of the excess low-level leakage currents in terms of the charging and discharging of traps previously generated by the high voltage stress. Excess low-level leakage currents measured with voltage pulses with polarity opposite to that of the stress voltage are found to contain an additional current component, which is explained by the transient charging and discharging of certain traps inside the oxide. Evidence is presented which suggests that an oxide trap generated by the high-voltage stress can contain either a positive or a negative charge, in addition to being neutral and that the traps are located near both oxide interfaces. All of the trap charging and discharging currents can be explained by the flow of electrons into and out of traps generated by the high voltage stress, without resorting to the flow of holes in the oxide     

堆叠栅介质MOS器件栅极漏电流的计算模型

采用顺序隧穿理论和传输哈密顿方法并考虑沟道表面量子化效应,建立了高介电常数堆叠栅介质MOS器件栅极漏电流的顺序隧穿模型。利用该模型数值,研究了Si3N4/SiO2、Al2O3/SiO2、HfO2/SiO2和La2O3/SiO2四种堆叠栅介质结构MOS器件的栅极漏电流随栅极电压和等效氧化层厚度变化的关系。依据计算结果,讨论了堆叠栅介质MOS器件按比例缩小的前景。     

Au纳米晶MIS结构存储性能研究

从器件结构和能带的角度分析了提高非易失性存储器性能的可能途径,建立了纳米晶浮栅结构的存储模型,并在模型中考虑了量子限制效应对纳米晶存储性能的影响.基于模型计算,分析了纳米晶材料、高k隧穿介质材料及其厚度对纳米晶浮栅结构存储性能的影响.同时,制作了MIS结构(Si/ZrO2/Au Ncs/SiO2/Al)的存储单元,针对该存储单元的电荷存储能力和电荷保持特性进行测试,并对测试结果进行分析.     

Effective Work Function Engineering of TaxCy Metal Gate on Hf-Based Dielectrics

This letter reports the engineering of effective work function (EWF) for tantalum carbide (TaC) metal gate on high-k gate dielectrics. The dependence of EWF on Si concentration in HfSiO as well as nitridation techniques is revealed. The EWF was extracted by both terraced oxide and terraced high-k techniques with the bulk and interface charges taken into account. The incorporation of Si in Hf-based dielectrics results in an increase of EWF, while the presence of N tends to decrease the EWF. Plasma nitridation is found to be more effective in lowering the EWF than a thermal nitridation. The phenomena can be explained by the modification of TaC/high-k interface dipole moment, which arises from the electronegativity difference for various interface bonds. Based on the above findings, we proposed a novel approach to reduce the EWF of TaC on HfSiON by using a thin HfO₂ cap layer after optimizing the nitridation. The MOSFET results show that this technique is able to achieve a lower V_t without degrading the device performance     

Influences of structure around gate-edge on high electric field strength in MISFETs with high-k gate dielectrics

In this paper, dependences of electric field strength around gate-edge in gate dielectrics of MISFETs with high-k gate dielectrics on design parameters are studied. It is newly found that locations of sidewall/gate dielectric interfaces relative to gate electrode edges are critical to electric field strength of high-k MISFETs. Electric field can be as high as 4 MV/cm, which could have large influences on the yield of large scale integrated circuits (LSIs) with high-k gate dielectrics. An explanation of this phenomenon is given by considering discontinuity in electric field at interfaces between two materials with different dielectric constants. It is clarified that an electrical potential of side and top surfaces of gate dielectrics is strongly affected by the discontinuity of electric field strength at interfaces. As a result, electric field strength around gate electrode edges critically depends on locations of sidewall/gate dielectrics interfaces relative to gate electrode edges. Based on the physical considerations, a structure, in which gate sidewalls are also made of high-k materials, is studied from the viewpoint of electric field strength around gate electrode edges. It is shown that this structure effectively suppresses electric field strength around gate edges.     

Characteristics and physical mechanisms of positive bias and temperature stress-induced drain current degradation in HfSiON nMOSFETs

Drain current degradation in HfSiON gate dielectric nMOSFETs by positive gate bias and temperature stress is investigated by using a fast transient measurement technique. The degradation exhibits two stages, featuring a different degradation rate and stress temperature dependence. The first-stage degradation is attributed to the charging of preexisting high-k dielectric traps and has a log(t) dependence on stress time, whereas the second-stage degradation is mainly caused by new high-k trap creation. The high-k trap growth rate is characterized by two techniques, namely 1) a recovery transient technique and 2) a charge-pumping technique. Finally, the effect of processing on high-k trap growth is evaluated.     

先进的Hf基高k栅介质研究进展

随着CMOS器件特征尺寸的不断缩小,SiO2作为栅介质材料已不能满足集成电路技术高速发展的需求,利用高k栅介质取代SiO2栅介质成为微电子技术发展的必然.但是,被认为最有希望替代SiO2的HfO2由于结晶温度低等缺点,很难集成于现有的CMOS工艺中,新型Hf基高k栅介质的研究成为当务之急.据报道,在HfO2中引入N、Si、Al和Ta可大大改善其热力学稳定性,由此形成的高k栅介质具有优良的电学特性,基本上满足器件的要求.本文综述了这类先进的Hf基高k栅介质材料的最新研究进展.     

Electrical and material property enhancement in HfTaSiON-gated MOS devices by tuning Hf composition

High dielectric constant (high-k) materials, as a replacement for conventional gate dielectrics, have been proposed to overcome the problem of excessive gate leakage current. HfSiON is a potential high-k gate dielectric material, but the value of its dielectric constant is considered a little too low. In this work, we incorporate Ta into HfSiON to form a HfTaSiON gate dielectric. The influences of different Hf contents in HfTaSiON and various post deposition anneal (PDA) treatments were studied in detail. Experimental results show thatimprovements on the material and electrical properties of metal-oxide-semiconductor (MOS) devices such as crystallization temperature, interface quality between high-k dielectric/Si, hysteresis, stress-induced leakage current (SILC) and interface trap density (D_it) are achieved with incorporating a suitable amount of Hf in HfTaSiON high-k gate dielectric     

An improved two-frequency method of capacitance measurement forSrTiO3 as high-k gate dielectric

An improved two-frequency method of capacitance measurement for the high-k gate dielectrics is proposed. The equivalent circuit model of the MOS capacitor including the four parameters of intrinsic capacitance, loss tangent, parasitic series inductance, and series resistance is developed. These parameters can be extracted by independently measuring the capacitor at two different frequencies. This technique is demonstrated for high-k SrTiO₃ gate dielectrics and the results show that the calibrated capacitances are invariant over a wide range of frequency. In addition, the extracted loss tangent, inductance and resistance are independent on gate voltage and frequency. The effect of series resistance on the frequency dispersion of the capacitance can be also explained by this model. These results indicate that this modified technique can be incorporated in the routine capacitance-voltage (C-V) measurement procedure providing the physically meaningful data for the high-k gate dielectrics     

Co-optimization of the metal gate/high-k stack to achieve high-field mobility >90% of SiO/sub 2/ universal mobility with an EOT=/spl sim/1 nm

HfO/sub 2/ and HfSiON gate dielectrics with high-field electron mobility greater than 90% of the SiO/sub 2/ universal mobility and equivalent oxide thickness (EOT) approaching 1 nm are successfully achieved by co-optimizing the metal gate/high-k/bottom interface stack. Besides the thickness of the high-/spl kappa/ dielectrics, the thickness of the ALD TiN metal gate and the formation of the bottom interface also play an important role in scaling EOT and achieving high electron mobility. A phase transformation is observed for aggressively scaled HfO/sub 2/ and HfSiON, which may be responsible for the high mobility and low charge trapping of the optimized HfO/sub 2/ gate stack.     

深亚微米MOS器件中栅介质层的直接隧穿电流

在WKB近似的理论框架下,提出了一个MOS器件中栅介质层直接隧穿电流的模型.在这个模型中,空穴量子化采用了一种改进的单带有效质量近似方法,这种方法考虑了价带的混合效应.通过与试验结果的对比,证明了这个模型可以适用于CMOS器件中电子和空穴的隧穿电流.还研究了介质层能隙中的色散对隧穿电流的影响.这个模型还可以进一步延伸到对未来高介电常数栅介质层中隧穿电流的研究.     

Impact of High-k Gate Dielectrics on the Device and Circuit Performance of Nanoscale FinFETs

The impact of high-k gate dielectrics on device short-channel and circuit performance of fin field-effect transistors is studied over a wide range of dielectric permittivities k. It is observed that there is a decrease in the parasitic outer fringe capacitance C_of in addition to an increase in the internal fringe capacitance C_if with high-k dielectrics, which degrades the short-channel effects significantly. It is shown that fin width scaling is the most suitable approach to recover the degradation in the device performance due to high-k integration. Furthermore, from the circuit perspective, for the 32-nm technology generation, the presence of an optimum k for a given target subthreshold leakage current has been identified by various possible approaches such as fin width scaling, fin-doping adjustment, and gate work function engineering     

Optimised doping profiles for speed-up of GaAs m.e.s.f.e.t.s

Simulation of m.e.s.f.e.t. logic cell shows that discharging of the gate depletion is significantly slower than the charging process. The transient response with the charging/discharging is analytically connected to arbitrary doping profiles. Specific profiles with a doping peak near the substrate boundary can reduce this discharging delay remarkably.