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发光二极管(LED)芯片反射电极中铝的稳定性对芯片的可靠性至关重要,少量铜的加入可改善铝的耐电流性.理论计算了电子柬蒸镀沉积时,镀源和镀膜中铜质量分数的对应关系.对纯铝和不同铜质量分数的铝铜合金进行了金属线耐电流测试和薄膜反射率测试,并对纯铝或铝铜合金电极的LED芯片进行了老化测试.结果表明,相对于纯铝电极结构,铜质量分数为2%的铝铜合金电极在几乎不影响反射率的前提下,可显著提高电极的耐电流性能.以铝铜合金为电极的LED芯片在老化过程中,可有效阻止铝的电迁移,从而显著提升了LED芯片的可靠性. 相似文献
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为了定量研究纳米颗粒的间距对拉曼(Raman)光谱强度的影响,研制了具有高稳定性的纳米劈裂芯片及装置。利用此芯片及装置,可以获得纳米金属桥断裂后自动形成的两针状纳米电极(纳米颗粒),并且能在pm级精度上操纵两纳米电极间的距离,以观察相应拉曼光谱强度的变化。在利用两纳米电极作为增强体的基础上引入了第3纳米电极,以观察其位置对拉曼光谱信号的影响。实验结果表明,光谱信号的强度强烈依赖于3纳米电极的相对位置,第3纳米电极的引入能进一步提高增强因子,为拉曼光谱增强机制的理论研究提供了重要参考数据。 相似文献
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实现贯通芯片的传输路径可自上而下贯穿整个芯片的硅贯通电极技术将会带来半导体芯片几十年一次的结构革命(见图1)。将布满了电路的半导体晶圆削薄至100μm以下,使背面几乎通透可见,然后在芯片上任意开几个贯通孔,通过电镀的方式形成电极。也有一些半导体厂家采用先形成贯通电极,然后再将晶圆削薄的方法。由于该电极是使用半导体的微加工技术所形成的,因此电极直径非常小,仅有几μm ̄几十μm。如果在整个芯片上均打上孔,则可以形成数千甚至数万个贯通电极。硅贯通电极的真正价值主要表现在单个封装内芯片间的相互连接方面(见图2)。将具有贯… 相似文献
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本研究的目的是要从理论上探讨利用单电极双向脉冲刺激实现哺乳动物神经纤维选择性刺激,(即当刺激一束神经时,不兴奋粗神经而兴奋细神经)的可能性.双向脉冲刺激可以降低刺激脉冲对神经纤维产生的电化学损伤.为研究哺乳动物有髓神经纤维的电特性,建立了一个基于简单的无穷大、各向同性的容积导体模型的仿真系统.利用该仿真系统,采用"不对称但电荷平衡"的双向脉冲刺激,计算了神经纤维的兴奋和阻断阈值与纤维直径、纤维-电极间距离的关系.结果表明:在距电极一定距离内采用该双向脉冲刺激模式确实可以实现哺乳动物有髓神经纤维的选择性兴奋. 相似文献
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根据光学薄膜原理,针对正装LED芯片设计了5种不同方式的电极结构,得出电流阻挡层SiO2和Al反射镜叠加制备出的反射电极具有较高的反射率,光电特性明显优于常规电极制备出的LED芯片。实验结果表明,该反射电极的反射率比常规电极结构反射率高53.1%,电流阻挡层SiO2可以改进有源区的电流扩展,减小电流堆积效应,而Al作为反射镜可以降低电极对光的吸收,使其发光效率、光强分布、饱和特性曲线和发光角度明显优于常规电极结构。实验采用化学气相沉积(CVD)法配合电子束蒸发制备反射电极,芯片的光功率提高了5.6%,成功制备出高亮度LED芯片。 相似文献
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开发了一个氧或葡萄糖浓度伏安测量的灵巧的新型传感器.芯片上集成了一个平面的伏安电极结构,CMOS接口电路和一个温度传感器.这种灵巧的传感器总面积为750μm×5000μm.实现了两种不同的电极结构.用Au作为工作电极的两电极系统用作血液中PO_2测量.用Pt作为工作电极和副电极的三电极系统测量血液中葡萄糖浓度,电极上涂了一层葡萄糖氧化酶膜. 相似文献
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针对高速嵌入式系统对自动调节输出电压的电源系统的需求,本文采用PMBus总线为电源芯片之间,电源芯片和控制器之间的通信提供标准,通过重点分析基于PMBus总线的数字可编程电源的内部结构和电压识别的技术实现方法,设计了一支持电压识别(VID)技术的带两路独立电压输出的数字可编程电源系统。经PMBus总线进行配置后,该电源系统可以满足高速嵌入式系统的多种电压需求,取得了良好的效果。 相似文献
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Makie-Fukuda K. Kikuchi T. Matsuura T. Hotta M. 《Solid-State Circuits, IEEE Journal of》1995,30(2):87-92
This paper proposes a method of measuring the influence of digital noise on analog circuits using wide-band voltage comparators as noise detectors. Noise amplitude and r.m.s voltage are successfully measured by this method. A test chip is fabricated to measure the digital noise influence. From the experimental results, it is shown that the digital noise influence can be considerably reduced by using a differential configuration in analog circuits for mixed-signal IC's. The digital noise influence can be further reduced by lowering the digital supply voltage. These results show that the voltage-comparator-based measuring method is effective in measuring the influence of digital noise on analog circuits 相似文献
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Mixed analog and digital circuits are realized on a 1.5 μm silicon-gate CMOS chip with +5 V power supply only. The circuit uses CMOS digital gate arrays of 0.32 K to 19.6 K cells and is created without any additional turnaround time or any restriction on the design. Typical internal digital gate (two-input NAND) speed, with a fanout of 3 and a wire length of 3 mm, is 1.4 ns. A voltage comparator with ±8 mV maximum input offset voltage and 60 ns response time, digital-to-analog and analog-to-digital converters with 4-, 6-, and 8-bit resolution, respectively, and an analog switch of 25 Ω on-resistance can be realized on the same chip with digital circuits. Using this technology, about one-tenth of the turnaround time can be achieved compared with full-custom LSIs for the same system. The product development flow and computer-aided-design tools for designing mixed analog and digital gate arrays are the same as for digital gate arrays 相似文献
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A CMOS very large scale integration (VLSI) chip has been designed and built to implement a scheme developed for multiplexing/demultiplexing the signals required to operate an intracortical stimulating electrode array. Because the use of radio telemetry in a proposed system utilizing this chip may impose limits upon the rate of data transmission to the chip, the scheme described herein was used to reduce the amount of digital information which must be sent to control a large quantity (up to several hundred) of stimulating electrodes. By incorporating multiple current sources on chip, many channels may be stimulated simultaneously. By incorporating on-chip timers, control over pulse timing is assigned to the chip, reducing by up to fourfold the amount of control data which must be sent. By incorporating on-chip RAM, information associated with the desired stimulus amplitude and pulse timing can be stored on chip, In this manner, it is necessary to send control information to the chip only when the information changes, rather than at the stimulus repeat rate for each channel. This further reduces the data rate by a factor of five to ten times or more. The architecture described here, implemented as an eight-channel stimulator, is scalable to a 625-channel stimulator while keeping data transmission rates under 2 Mbps 相似文献
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Shyh-Yih Ma Liang-Gee Chen 《Solid-State Circuits, IEEE Journal of》1999,34(10):1415-1418
A complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) camera chip with direct frame difference output is reported in this paper. The proposed APS cell circuit has in-pixel storage for previous frame image data so that the current frame image and the previous frame image can be read out simultaneously in differential mode. The signal swing of the pixel circuit is maximized for low supply voltage operation. The pixel circuit occupies 32.2×32.2 μm2 of chip area with a fill factor of 33%. A 128×98 element prototype camera chip with an on-chip 8-bit analog-to-digital converter has been fabricated in a 0.5-μm double-poly double-metal CMOS process and successfully tested. The camera chip consumes 56 mW at 30 frames/s with 3.3 V power supply 相似文献
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本文提出了一种可编程复接方法和结构,通过对编程端的设置可得到2∶1、3∶1、4∶1及5∶1的复接模式.该方法鲁棒性强、应用范围广,其组合可实现除包含大于6的质数之外所有路数的复接,解决了光纤通信系统中不同复接模式对应不同复接结构的问题.通过理论推导,本文着重分析了器件延时和时钟相位对芯片工作的影响,并指出了解决途径.基于本方法和结构的全定制单片集成电路采用0.35μm CMOS工艺制造,芯片面积为24.19mm2,实现了串行输出最高数据速率为1.62Gbps的10∶1复接.在1.25Gbps标准速率,工作电压3.3V,负载为50Ω的条件下,功耗仅为174.84mW,输出电压峰-峰值可达到2.42V,占空比为49%,抖动为35ps rms.测试结果表明芯片在复接性能、速度、功耗和面积优化方面的先进性,可满足不同吉比特率通信系统的要求,具有广泛应用和产业化前景. 相似文献