Test generation for specification test of analog circuits using efficient test response observation methods

In this paper, a new automated test generation methodology for specification testing of analog circuits using test point selection and efficient analog test response waveform capture methods for enhancing the test accuracy is proposed. The proposed approach co-optimizes the construction of a multi-tone sinusoidal test stimulus and the selection of the best set of test response observation points. For embedded analog circuits, it uses a subsampling-based digitization method compatible with IEEE 1149.1 to accurately digitize the analog test response waveforms. The proposed specification approach uses ‘alternate test’ framework, in which the specifications of the analog circuit-under-test are computed (predicted) using statistical regression models that are constructed based on process variations and corresponding variations of test responses captured from different test observation points. The test generation process and the test point selection process aim to maximize the accuracy of specification prediction. Experimental results validating the proposed specification test approach are presented.     

A Low-Cost Test Methodology for Dynamic Specification Testing of High-Speed Data Converters

Testing high-speed A/D converters for dynamic specifications needs test equipment running at high frequency. In this paper, a methodology to test high-speed A/D converters using low-frequency resources is described. It is based on the alternate testing approach. In the proposed methodology, models are built to map the signatures of an initial set of devices, obtained on the proposed low-cost test set-up, to the dynamic specifications of the same devices, obtained using high-precision test equipment. During production testing, the devices are tested on the low-cost test set-up. The dynamic specifications of the devices are estimated by capturing their signatures on the low cost test set-up and processing them with the pre-developed models. As opposed to the conventional method of dynamic specification testing of data converters, the proposed approach does not require the tester resources running at a frequency higher than the device-under-test (DUT). The test methodology was verified in simulations as well as in hardware with specification estimation error of less than 5%.

Enhancing confidence in indirect analog/RF testing against the lack of correlation between regular parameters and indirect measurements

The greedy specification testing remains mandatory for analog and radio frequency (RF) integrated circuits because of the accuracy of the sorting based on these measurements. Unfortunately, to be implemented, this kind of testing method often incurs very high costs (expensive instruments, long test time…). A common approach, in the literature, is the so-called indirect/alternate test strategy. This strategy consists in deriving targeted specifications from low-cost Indirect Measurements (IMs). During the industrial test phase, the estimation of regular specifications using IMs is based on a correlation model that has been built previously, during a training phase. Despite the substantial test cost reduction offered by this strategy, its deployment in industry is limited, mainly because of a lack of confidence in the accuracy of estimations made by the correlation model. A solution to increase the confidence in the estimation of specifications using the indirect approach is to implement redundancy in the prediction phase. In this paper, we demonstrate that the redundancy implementation brings more than identifying rare misjudged circuits from a high-correlated model. Indeed redundancy massively increases the accuracy despite of the lack of accurate models that have been assumed in previous implementations of redundant indirect testing. This approach is illustrated on a real case study for which we have experimental measurements on a set of 10,000 devices.     

Fault Simulation for Analog Circuits Under Parameter Variations

Analog integrated circuit testing and diagnosis is a very challenging problem. The inaccuracy of measurements, the infinite domain of possible values and the parameter deviations are among the major difficulties. During the process of optimizing production tests, Monte Carlo simulation is often needed due to parameter variations, but because of its expensive computational cost, it becomes the bottleneck of such a process. This paper describes a new technique to reduce the number of simulations required during analog fault simulation. This leads to the optimization of production tests subjected to parameter variations. In Section 1 a review of the state of the art is presented, Section 2 introduces the algorithm and describes the methodology of our approach. The results on CMOS 2-stage opamp and Fifth-order Low-pass switched-capacitor Filter are given in Sections 3 and conclusions in Section 4.     

System-Level Specification Testing Of Wireless Transceivers

This paper presents an efficient system-level manufacturing test methodology for wireless transceiver systems. Conventional system-level testing procedures incur large test times and require the use of multiple test hardware configurations for measuring frequency and modulation-domain performance specifications, e.g., system-gain, nonlinearity, noise-figure, channel power, adjacent-channel power-ratio, error vector magnitude, modulation signal-to-noise ratio and bit error rate. The proposed test methodology addresses these problems by simplifying the test stimulus application and test response capture/analysis procedures. In addition, the number of test hardware configurations needed to measure all the performance specifications is minimized and fewer as well as shorter tests are used to determine all the test specification values of interest. Test accuracy is achieved by optimizing the test stimulus so that the observed response has strong statistical correlation with the target test specification values. Experimental results show significant testing time reduction and was validated on 1.575 GHz and 900 MHz wireless transceiver prototypes.     

Indirect test of M-S circuits using multiple specification band guarding

Testing analog and mixed-signal circuits is a costly task due to the required test time targets and high end technical resources. Indirect testing methods partially address these issues providing an efficient solution using easy to measure CUT information that correlates with circuit performances. In this work, a multiple specification band guarding technique is proposed as a method to achieve a test target of misclassified circuits. The acceptance/rejection test regions are encoded using octrees in the measurement space, where the band guarding factors precisely tune the test decision boundary according to the required test yield targets. The generated octree data structure serves to cluster the forthcoming circuits in the production testing phase by solely relying on indirect measurements. The combined use of octree based encoding and multiple specification band guarding makes the testing procedure fast, efficient and highly tunable. The proposed band guarding methodology has been applied to test a band-pass Butterworth filter under parametric variations. Promising simulation results are reported showing remarkable improvements when the multiple specification band guarding criterion is used.     

Efficiency of Spectral-Based ADC Test Flows to Detect Static Errors

Testing of Analog-to-Digital Converters is classically composed of two successive and independent phases: the histogram-based test technique evaluating static specifications and the spectral analysis technique evaluating the dynamic performances. Consequently, the fundamental objective here is to investigate the feasibility of an alternative test flow involving exclusively spectral analysis to replace these two time consuming and expensive phases. The viability of this solution depends on the ability of spectral analysis to detect static specifications. In this context, this paper presents a new methodology based on a statistical approach to quantitatively evaluate the efficiency of detecting static errors from dynamic parameter measurements. This methodology has been implemented in an in-house automatic tool allowing one to process any ADC specifications. It is then possible to choose a priori the best test flow for a given application.     

Automated System-Level Test Development for Mixed-Signal Circuits

While in the digital domain, test development is primarily conducted with the use of automated tools, knowledge-based, ad hoc test methods have been in use in the analog domain. High levels of design integration and increasing complexity of analog blocks within a system necessitate automated system-level analog test development tools. We outline a methodology for specification-based automated test generation and fault simulation for analog circuits. Test generation is targeted at providing the highest coverage for each specified parameter. The flexibility of assigning analog test attributes is utilized for merging tests leading to test time reduction with no loss in test coverage. Further optimization in test time is obtained through fault simulations by selecting tests that provide adequate coverage in terms of several components and dropping the ones that do not provide additional coverage. A system-level test set target in the given set of specifications, along with fault and yield coverages in terms of each targeted parameter, and testability problems are determined through the proposed methodology.     

Constraint transformation for IC physical design

In a top-down design methodology, design tasks are divided into simpler subtasks across levels of a hierarchy as an effective divide-and-conquer technique. For every task, tolerances are defined on all performance characteristics to take into account parasitics, mismatches, and other nondeterministic process parameter variations. Constraint transformation is a process used to translate performance specifications into subtask requirements. This paper introduces the problem of constraint transformation and describes some formal solutions for analog circuit applications. Examples illustrate the methodology and show the suitability of this approach in industrial-strength applications     

Optimization-based multifrequency test generation for analog circuits

A robust test set for analog circuits has to detect faults under maximal masking effects due to variations of circuit parameters in their tolerance box. In this paper we propose an optimization based multifrequency test generation method for detecting parametric faults in linear analog circuits. Given a set of performances and a frequency range, our approach selects the test frequencies that maximize the observability on a circuit performance of a parameter deviation under the worst masking effects of normal variations of the other parameters. Experimental results are provided and validated by HSpice simulations to illustrate the proposed approach.     

Adaptive Modeling of Analog/RF Circuits for Efficient Fault Response Evaluation

In this paper, we propose a methodology for adaptive modeling of analog/RF circuits. This modeling technique is specifically geared towards evaluating the response of a faulty circuit in terms of its specifications and/or measurements. The goal of this modeling approach is to compute important test metrics, such as fail probability, fault coverage, and/or yield coverage of a given measurement under process variations. Once the models for the faulty and fault-free circuit are generated, we can simply use Monte-Carlo sampling (as opposed to Monte-Carlo simulations) to compute these statistical parameters with high accuracy. We use the error budget that is defined in terms of computing the statistical metrics and the position of the threshold(s) to decide how precisely we need to extract the necessary models. Experiments on LNA and Mixer confirm that the proposed techniques can reduce the number of necessary simulations by factor of 7 respectively, in the computation of the fail probability.     

Efficient sensitization of multi-bit-paths for testing embedded modules in synchronous sequential circuits

This article presents SPLASH, an algorithm that can sensitize several independent bitpaths simultaneously. SPLASH includes several new concepts and techniques aiming at a significant improvement and acceleration of the path sensitization for testing embedded modules in combinational and synchronous sequential circuits. The transparent paths are used to apply module test patterns through circuit inputs and observe the responses at circuit outputs. It consequently automates an important task of modular test generation, supplying a test pattern assembly program with a specification how to transform module test patterns into circuit level pattern.A number of experiments using combinational and sequential benchmark circuits as well as industrial designs demonstrate the efficiency of the approach.     

一种航空地面电源检测仪的设计与实现

介绍了一种航空地面电源检测仪的功能和性能,给出了设计思想和原理电路,经测试及应用证明其各项性能符合航空维修要求,并且稳定可靠.     

Predictive subset testing: optimizing IC parametric performancetesting for quality, cost, and yield

A formal methodology for IC parametric performance testing, called predictive subset testing, is presented. It is based on a statistical model of parametric process variation. In this Monte-Carlo-based approach, a statistical process simulation is used together with circuit simulation to determine the joint probability distribution of a set of circuit performances. By evaluating the joint probability distribution, rather than assuming the performances to be independent, correlations that exist between them are used to reduce the number of performances that need to be explicitly tested. Once a subset of performances for explicit testing has been identified, regression models are constructed for the untested performances, and from the confidence intervals test limits are assigned for the tested performances. In this manner, the values of the untested performances within desired quality levels are predicted, reducing test complexity and cost     

光电二极管批量快速测试系统的设计与实现

随着光电二极管的用量不断增大,手动测试筛选已满足不了测试需求,定制自动测试系统又存在成本较高、不易推广的缺点。为提高测试效率、解放人力资源及便于测试系统推广,采用一台KEITHLEY 2400源表及开关控制板构建了批量快速测试系统。开关控制板的阵列开关采用两片1∶8多路复用器实现,与采用继电器实现相比,降低了硬件设计难度及复杂度。将开关控制部分与器件载体部分分别设计在两块电路板上,并用两块载体板交替完成器件安装与测试,能实现器件插拔与器件测试并行进行,缩短了测试等待时间。将测试控制、参数测试及数据处理流程化,使测试效率得到了进一步提高。试验结果表明:搭建的测试系统可实现一批64只器件的一键式测试,每只器件单个参数平均测试时间不到1s,且测试准确度较高。     

Variability aware SVM macromodel based design centering of analog circuits

Design centering is the term used for a procedure of obtaining enhanced parametric yield of a circuit despite the variations in device and design parameters. The process variability in nanometer regimes manifest into variations in these devices and design parameters. During design space exploration of analog circuits, a methodology to find design-instances with better yield is necessitated; this would ensure that the circuit will function as per specifications after fabrication, even with impact of statistical variations. We need to evaluate circuit performance for a given instance of a circuit-design identified by possessing a set of nominal values of device-design parameters. A lot of instances need be searched, having different sizes for a given circuit topology. HSPICE is very compute intensive. Instead, we employ macromodeling approach for analog circuits based on support vector machine (SVM), which enables efficient evaluation of performance of such circuits of different sizing during yield optimization loops. These performance macromodels are found to be as accurate as SPICE and at the same time, time-efficient for use in sizing of analog circuits with optimal yield. Process variability aware SVM macromodels are first trained and then used inside the Genetic algorithm loops for design centering of different circuits, subsequently resulting into sized-circuit instances having optimal yield. Post design centering, the sized circuits will be able to provide functions as per specifications upon fabrication. The application of this design centering approach as process variability analysis tool is illustrated on various circuits e.g. two stage op amp, voltage controlled oscillator and mixer circuit with layouts drawn into 90?nm UMC technology (Euro-practice).     

Inline Rth control: Short time thermal transient evaluation for high power LEDs

As junction-to-case thermal resistance R_thJC is a primary performance and reliability parameter for high power light emitting diodes (LED) an accurate specification of this value is of paramount importance. Currently thermal transient characterization methods are reserved to research and quality laboratories. Especially the thermal calibration procedure requires an enormous effort of time. Therefore the R_thJC specification of a high volume production is based on a statistical approach. However, high test coverage or even a single unit test is desired. This paper presents a method for inline R_th control for high power LEDs. By skipping the conventional thermal calibration procedure the method compares the measured response of the device under test with a completely thermal characterized reference curve of a reference device. It enables to detect variations in thermal interface materials, e.g. failures in the thermal adhesive attach, with sufficient accuracy within some hundred milliseconds testing time. The achieved measurement results verify the applicability of inline R_th control in a high volume production.     

Built-in Self Test of RF Subsystems with Integrated Detectors

This paper describes a built-in self test technique for RF subsystems, using low-overhead on-chip detectors to calculate circuit specifications. A novel on-chip amplitude detector has been designed and optimized for RF circuit specification test. The detector has small area overhead with a low-frequency output. A test chip was fabricated in a commercial 0.18 μm CMOS process. By using on-chip detectors in a loopback setup, both the system performance and specifications of the individual components can be accurately measured. Measurements show accurate prediction of system and component specifications.     

Study of CMOS Process Variation by Multiplexing Analog Characteristics

Aggressive technology scaling raises the need for efficient methods to characterize and model circuit variation at both the front and back end of line, where critical parameters such as threshold voltage and parasitic capacitance must be carefully modeled for accurate circuit performance. In this paper we address this need by contributing a test circuit methodology for the extraction of spatial, layout and size dependent variations at both device and interconnect levels. The test chip uses a scan chain approach combined with low-leakage and low-variation switches, and Kelvin sensing connections, providing access to detailed analog device characteristics in large arrays of test devices. Variation measurement using the designed test chip has proven successful for both device and interconnect test structures. The parameter extraction and variation analyses made possible by the variation test chip enable the identification of likely variation sources, quantification of circuit impact and sensitivity, and specification of layout practices for variation minimization.      

A low-cost test solution for wireless phone RFICs

This article describes an IBM approach for testing high-volume, complex RFICs at a fraction of the cost of the integrated circuit. This approach uses a personal computer, a fast benchtop dc parametric analyzer, and RF-to-analog circuits to test an RFIC during the manufacturing process. The described system and methodology are specifically designed for high-volume test, where test cost is extremely important; they are not recommended for lower-volume products (less than 1 million per month). This article describes the system architecture and discusses design, maintenance, and implementation considerations. The system is designed to reduce the cost of a complex RFIC manufacturing test to equal that of a discrete component, such as a resistor or capacitor. Given the relatively easy implementation and the drastic cost reduction associated with the test solution, this architecture establishes a new standard for the future of RF test. In fact, this architecture may result in the fastest RF tester currently available.