A CMOS Backgate-Coupled QVCO Based on Back-to-Back Series Varactor Configuration for Minimal AM-to-PM Noise Conversion

A 3.3 GHz CMOS quadrature voltage-controlled oscillator (QVCO) with very low phase noise is presented. The back-to-back series varactor configuration is employed in the LC tank for minimizing the AM-to-PM noise conversion. The backgate coupling for quadrature phase inter-locking further eliminates the noise contribution from coupling transistors and also reduces power consumption. The implemented QVCO in 0.18 $mu{rm m}$ CMOS technology achieved very low phase noise of ${- 133}~{rm dBc}/{rm Hz}$ at 1 MHz offset, where the total power consumption is 4.4 mW from a 1.0 V supply. The chip has a very high FOM of ${- 196.6}~{rm dBc}/{rm Hz}$.      

A 98/196 GHz Low Phase Noise Voltage Controlled Oscillator With a Mode Selector Using a 90 nm CMOS Process

A 98/196 GHz low phase noise voltage controlled oscillator (VCO) with a fundamental/push-push mode selector using a 90 nm CMOS process is presented in this letter. An innovative concept of the VCO with the mode selector is proposed to switch the fundamental or second harmonic to the RF output. The VCO demonstrates a fundamental frequency of up to 98 GHz with an output power of greater than $-8~{rm dBm}$. The phase noise of the VCO is better than $-100.8~{rm dBc}/{rm Hz}$ at 1 MHz offset frequency, and its figure-of-merit is better than $-186~{rm dBc}/{rm Hz}$. Moreover, the output frequency of the work is up to 196 GHz with a fundamental suppression of greater than $-30~{rm dBc}$ as the VCO is operated in push-push mode.      

A Low Voltage and Low Power Bottom-Series Coupled Quadrature VCO

This letter presents a new low power quadrature voltage-controlled oscillator (QVCO), which consists of two complementary cross-coupled voltage-controlled oscillators (VCOs) with split-source tail inductors. The bottom-series coupling transistors are in parallel with the tail inductors and require no dc voltage headroom. The proposed CMOS QVCO has been implemented with the TSMC 0.18 $mu{rm m}$ CMOS technology and the die area is $0.512times 1.065 {rm mm}^{2}$. At the supply voltage of 1.1 V, the total power consumption is 2.545 mW. The free-running frequency of the QVCO is tunable from 4.38 to 4.71 GHz as the tuning voltage is varied from 0.0 V to 0.6 V. The measured phase noise at 1 MHz frequency offset is $-$120.8 dBc/Hz at the oscillation frequency of 4.4 GHz and the figure of merit (FOM) of the proposed QVCO is $-$ 189.61 dBc/Hz.      

A Low Phase-Noise QVCO With Integrated Back-Gate Coupling and Source Resistive Degeneration Technique

A 0.18 $mu$ m CMOS quadrature voltage-controlled oscillator with an extremely-low phase noise is presented. The excellent phase noise performance is accomplished by integration of the back-gate quadrature phase coupling and source resistive degeneration techniques into a complementary oscillator topology. The measured phase noise is as low as ${-}133$ dBc/Hz at 1 MHz offset from 3.01 GHz. The output phase imbalance is less than 1$^{circ}$ . The output power is $-1.25{pm} 0.5$ dBm and harmonic suppression is greater than 30.8 dBc. The oscillator core consumes 5.38 mA from a 1.5 V power supply. This QVCO achieves the highest figure-of-merit of ${-}193.5$ dBc/Hz.      

A Biphase Modulator Circuit for Impulse Radio-UWB Applications

This letter presents a circuit to provide binary phase shift keying to ultra-wideband (UWB) impulse transmitters. The circuit is based on a Gilbert-cell multiplier and uses active on-chip balun and unbalanced-to-balanced converters for single-ended to single-ended operation. Detailed measurements of the circuit show a gain ripple of $pm 1~{rm dB}$ at an overall gain of $-2~{rm dB}$, an input reflection below $-12~{rm dB}$, an output reflection below $-18~{rm dB}$, a group delay variation below 6 ps and a $-1~{rm dB}$ input compression point of more than 1 dBm in both switching states over the full 3.1–10.6 GHz UWB frequency range. A time domain measurement verifies the switching operation using an FCC-compliant impulse generator. The circuit is fabricated in a $0.8~mu {rm m}$ Si/SiGe HBT technology, consumes 31.4 mA at a 3.2 V supply and has a size of $510 times 490~mu{rm m}^{2}$ , including pads. It can be used in UWB systems using pulse correlation reception or spectral spreading.      

Low Phase Noise Differential Vackar VCO in 0.18 CMOS Technology

In this letter, we present the measured performance of a differential Vackar voltage-controlled oscillator (VCO) implemented for the first time in CMOS technology. The Vackar VCO provided good isolation between the LC tank and the loss-compensating active circuit; thus, excellent frequency stability was achieved over the frequency tuning range. The Vackar VCO was implemented using nMOS transistors and an LC tank in a 0.18 $mu{rm m}$ RF CMOS process. The oscillation frequency ranged from 4.85 to 4.93 GHz. The measured phase noise of the Vackar VCO at 1 MHz offset was $-124.9 ~{rm dB}/{rm Hz}$ at 4.9 GHz with a figure-of-merit (FOM) of $-188 ~{rm dBc}/{rm Hz}$.      

A 10:1 Unequal Wilkinson Power Divider Using Coupled Lines With Two Shorts

A novel unequal Wilkinson power divider is presented. A coupled-line section with two shorts is proposed to realize the high characteristic impedance line, which cannot be implemented by conventional microstrip fabrication technique due to fabrication limitation. The proposed coupled-line structure is compatible with single layer integration and can be easily designed based on an even-odd mode analysis. As a design example, a 10:1 Wilkinson power divider at 2 GHz is fabricated and measured. The measured $-10~{rm dB}$ bandwidth of $S_{11}$ is about 16%, and the isolation $S_{32}$ is better than $-20~{rm dB}$ . The measured amplitude balance between output port 2 and port 3 is between $-10.20~{rm dB}$ and $-9.52~{rm dB}$, and the corresponding phase difference is between 0$^{circ}$ and 4.6$^{circ}$.      

A 0.22 V Quadrature VCO in 90 nm CMOS Process

This letter presents an ultra-low voltage quadrature voltage-controlled oscillator (QVCO). The LC-tank QVCO consists of two low-voltage voltage-controlled oscillators (VCOs) with the body dc biased at the drain bias through a resistor. The superharmonic and back-gate coupling techniques are used to couple two differential VCOs to run in quadrature. The proposed CMOS QVCO has been implemented with the UMC 90 nm CMOS technology and the die area is 0.827 $, times ,$0.913 mm $^{2}$. At the supply voltage of 0.22 V, the total power consumption is 0.33 mW. The free-running frequency of the QVCO is tunable from 3.42 to 3.60 GHz as the tuning voltage is varied from 0.0 to 0.3 V. The measured phase noise at 1 MHz offset is ${-}112.97$ dBc/Hz at the oscillation frequency of 3.55 GHz and the figure of merit (FOM) of the proposed QVCO is about ${-}188.79$ dBc/Hz.      

W-Band Active Down-Conversion Mixer in Bulk CMOS

A W-band (76–77 GHz) active down-conversion mixer has been demonstrated using low leakage (higher ${rm V}_{{rm T}}$) NMOS transistors of a 65-nm digital CMOS process with 6 metal levels. It achieves conversion gain of ${-}8$ dB at 76 GHz with a local oscillation power of 4 dBm (${sim-}2$ dBm after de-embedding the on-chip balun loss), and 3 dB bandwidth of 3 GHz. The SSB noise figures are 17.8–20 dB (11.3–13.5 dB after de-embedding on-chip input balun loss) between 76 and 77 GHz. ${rm IP}_{1{rm dB}}$ is ${-}6.5$ dBm and IIP3 is 2.5 dBm (${sim-}13$ and ${sim}-4$ dBm after de-embedding the on-chip balun loss). The mixer consumes 5 mA from a 1.2 V supply.      

A 108 dB SNR, 1.1 mW Oversampling Audio DAC With A Three-level DEM Technique

A low power audio oversampling $Sigma Delta $ digital-to-analog converter (DAC) with a three-level $(+1,~0,-1)$ dynamic-element-matching (DEM) technique and an inter-symbol interference-free (ISI) output stage is presented. Solutions for design challenges such as ISI, clock jitter sensitivity, and out-of-band noise are presented. The converter is fabricated in a 0.18 $mu{hbox {m}}$ CMOS process, occupies 0.55 ${hbox {mm}}^{2}$, achieves 108 dB dynamic range, $-98~{rm dB ~THD}+{rm N}$ while consumes a total of 1.1 mW per channel at 1.8 V supply.      

A 2.4 GHz Current-Reused CMOS Balun-Mixer

A 0.13 $mu{rm m}$ CMOS 2.4 GHz balun-mixer is proposed, where a current-reused noise-canceling topology is adopted as the transconductance stage to reduce dc power consumption. After frequency conversion, noise-cancellation is achieved only when a specified condition is satisfied, but single-to-differential signal conversion is inherently obtained by the mixer operation. The fabricated chip shows a conversion gain of 13.5 dB, a single-side-band (SSB) noise figure of 8 dB, and an input-referred ${rm IP}_{3}$ of ${- 6}~{rm dBm}$, while consuming only 3.5 mA from a 1.5 V supply voltage.      

A Low-Voltage Mobility-Based Frequency Reference for Crystal-Less ULP Radios

The design of a 100 kHz frequency reference based on the electron mobility in a MOS transistor is presented. The proposed low-voltage low-power circuit requires no off-chip components, making it suitable for application in wireless sensor networks (WSN). After a single-point calibration, the spread of its output frequency is less than 1.1% (3$sigma $) over the temperature range from $-{hbox{22}},^{circ}{hbox{C}}$ to 85$,^{circ}{hbox{C}}$ . Fabricated in a baseline 65$~$nm CMOS technology, the frequency reference circuit occupies 0.11$ hbox{mm}^{2}$ and draws 34 $ muhbox{A}$ from a 1.2 V supply at room temperature.      

Novel Composite Phase-Shifting Transmission-Line and Its Application in the Design of Antenna Array

A novel composite phase-shifting transmission line (TL) with designable characteristics is presented, which can be used to achieve arbitrary phase of the transmission coefficient at any required frequency with a certain length of the TL. An empirical formula is given of the relationship between the phase and physical length of the composite TL at a required frequency. A sample of 0$^{circ}$ phase-shifting TL is designed in details, and is verified by the full-wave simulation. At the required frequency of 5 GHz, the amplitude of ${rm S}_{21}$ is equal to $-0.23~{rm dB}$ with a phase of $-0.467^{circ}$. The electric length is only $0.212lambda_{0}$ , which has been decreased by 68.5% compared to the conventional microstrip line. Using the proposed composite TL, an antenna array is designed with two radiation patches excited by the novel series feed-line. The detailed procedure of such design is presented. The lowest reflection coefficient is exactly achieved at the required frequency of 5 GHz. The maximum radiation is obtained at $theta_{0}=0^{circ}$ , which indicates that the 0$^{circ}$ phase-shifting TL works very well. The sample is also fabricated and good agreements between simulation and measurement results are obtained.      

A $K$ -Band CMOS Distributed Doubler With Current-Reuse Technique

A $K$-band distributed frequency doubler is developed in 0.18 $mu{rm m}$ CMOS technology. This doubler combines the distributed topology for broadband characteristics and current-reuse technique to improve the conversion gain. The high-pass drain line and high-pass inter-stage matching network are used to obtain a good fundamental rejection. A measured conversion gain of better than ${- 12.3}~{rm dB}$ is obtained, and the fundamental rejection is better than 30 dB for the output frequency between 18 and 26 GHz. The dc power consumption is 10.5 mW with a chip size of 0.55$,times,$0.5 ${rm mm}^{2}$.      

A 0.55 V 60 dB-DR Fourth-Order Analog Baseband Filter

A 0.55 V supply voltage fourth-order low-pass continuous-time filter is presented. The low-voltage operating point is achieved by an improved bias circuit that uses different opamp input and output common-mode voltages. The fourth-order filter architecture is composed by two Active- ${rm G}_{rm m}{-}{rm RC}$ biquadratic cells, which use a single opamp per-cell with a unity-gain-bandwidth comparable to the filter cut-off frequency. The $-$ 3 dB filter frequency is 12 MHz and this is higher than any other low-voltage continuous-time filter cut-off frequency. The $-$3 dB frequency can be adjusted by means of a digitally-controlled capacitance array. In a standard 0.13 $mu{rm m}$ CMOS technology with ${V}_{THN}approx 0.25 {rm V}$ and ${V}_{THP}approx 0.3 {rm V}$, the filter operates with a supply voltage as low as 0.55 V. The filter $({rm total} {rm area}=0.47 {rm mm}^{2})$ consumes 3.4 mW. A 8 dBm-in-band IIP3 and a 13.3 dBm-out-of-band IIP3 demonstrate the validity of the proposal.      

Wideband LNA Compatible for Differential and Single-Ended Inputs

This letter presents a wideband low-noise amplifier (LNA) that supports both differential and single-ended inputs, while providing differential output. The LNA is implemented in 0.13 $mu{rm m}$ CMOS technology. For sub-1 GHz wideband applications, this LNA achieves 22.5 dB voltage gain, ${+ 1}~{rm dBm}$ IIP3, and 2.5 dB NF in the differential receiving mode, while achieving 23 dB voltage gain, ${- 0.5}~{rm dBm}$ IIP3, and 2.65 dB NF in the single-ended receiving mode. The LNA core circuit draws 2.5 mA from 1.2 V supply voltage, and occupies a small chip area of 0.06 ${rm mm}^{2}$.      

A 36–80 GHz High Gain Millimeter-Wave Double-Balanced Active Frequency Doubler in SiGe BiCMOS

This letter presents a high conversion gain double-balanced active frequency doubler operating from 36 to 80 GHz. The circuit was fabricated in a 200 GHz ${rm f}_{rm T}$ and ${rm f}_{max}$ 0.18 $mu$m SiGe BiCMOS process. The frequency doubler achieves a peak conversion gain of 10.2 dB at 66 GHz. The maximum output power is 1.7 dBm at 66 GHz and ${-}3.9$ dBm at 80 GHz. The maximum fundamental suppression of 36 dB is observed at 60 GHz and is better than 20 dB from 36 to 80 GHz. The frequency doubler draws 41.6 mA from a nominal 3.3 V supply. The chip area of the active frequency doubler is 640 $mu$m $,times,$424 $mu$m (0.272 mm $^{2}$) including the pads. To the best of authors' knowledge, this active frequency doubler has demonstrated the highest operating frequency with highest conversion gain and output power among all other silicon-based active frequency doublers reported to date.      

Millimeter Wave Varistor Mode Schottky Diode Frequency Doubler in CMOS

The first mm-wave varistor mode Schottky diode frequency doubler fabricated in CMOS is demonstrated. The doubler exhibits 14 dB conversion loss, $-11~{rm dBm}$ output power at 132 GHz and 6 GHz 3-dB output bandwidth from 128 to 134 GHz. The input matching is better than $-10~{rm dB}$ and the rejection of fundamental signal at output is greater than 14 dB from 62 to 70 GHz.      

A Low Loss High Isolation DC-60 GHz SPDT Traveling-Wave Switch With a Body Bias Technique in 90 nm CMOS Process

In this letter, a low loss high isolation broadband single-port double-throw (SPDT) traveling-wave switch using 90 nm CMOS technology is presented. A body bias technique is utilized to enhance the circuit performance of the switch, especially for the operation frequency above 30 GHz. The parasitic capacitance between the drain and source of the NMOS transistor can be further reduced using the negative body bias technique. Moreover, the insertion loss, the input 1 dB compression point (${rm P} _{{1}~{rm dB}}$), and the third-order intermodulation (IMD3) of the switch are all improved. With the technique, the switch demonstrates an insertion loss of 3 dB and an isolation of better than 48 dB from dc to 60 GHz. The chip size of the proposed switch is 0.68 $,times,$0.87 ${rm mm}^{2}$ with a core area of only 0.32$,times,$0.21 ${rm mm}^{2}$.      

A 1 V 23 GHz Low-Noise Amplifier in 45 nm Planar Bulk-CMOS Technology With High-$Q$ Above-IC Inductors

A 23 GHz electrostatic discharge-protected low-noise amplifier (LNA) has been designed and implemented by 45 nm planar bulk-CMOS technology with high-$Q$ above-IC inductors. In the designed LNA, the structure of a one-stage cascode amplifier with source inductive degeneration is used. All high- $Q$ above-IC inductors have been implemented by thin-film wafer-level packaging technology. The fabricated LNA has a good linearity where the input 1 dB compression point $({rm IP}_{{-}1~{rm dB}})$ is ${- 9.5}~{rm dBm}$ and the input referred third-order intercept point $(P _{rm IIP3})$ is ${+ 2.25}~{rm dBm}$. It is operated with a 1 V power supply drawing a current of only 3.6 mA. The fabricated LNA has demonstrated a 4 dB noise figure and a 7.1 dB gain at the peak gain frequency of 23 GHz, and it has the highest figure-of-merit. The experimental results have proved the suitability of 45 nm gate length bulk-CMOS devices for RF ICs above 20 GHz.