SPICE模拟纳米技术场效应晶体管圆角效应的建模技术

This paper presents a novel poly(PC)and active(RX)corner rounding modeling approach to SPICE simulations.A set of specially designed structures was used for measurement data collection.PC and RX corner rounding equations have been derived based on an assumption that the corner rounding area is a fragment of a circle.The equations were modified to reflect the gouging effect of physical silicon wafers.The modified general equations were implemented in the SPICE model to enable the model to describe the corner rounding effect.The good fittings between the SPICE model simulation results and the silicon data demonstrated in this paper proved that the designed corner rounding model is practical and accurate.     

Modeling mechanical stress effect on dopant diffusion in scaled MOSFETs

The effect of shallow trench isolation mechanical stress on MOSFET dopant diffusion has become significant, and affects device behavior for sub-100-nm technologies. This paper presents a stress-dependent dopant diffusion model and demonstrates its capability to reflect experimental results for a state-of-the-art logic CMOS technology. The proposed stress-dependent dopant diffusion model is shown to successfully reproduce device characteristics covering a wide range of active area sizes, gate lengths, and device operating conditions.     

Improved device variability in scaled MOSFETs with deeply retrograde channel profile

Continued scaling of transistor has resulted in severe short channel effects and transport degradation. In addition, variability in deeply scaled transistor such as threshold voltage (V_TH) variability has emerged as a major challenge for circuit and device design. Although various techniques have been suggested to alleviate these problems, such as CMOS on FDSOI or 3D transistors, they are expensive and complicated to manufacture. Recently, MOSFETs with deeply retrograde channel profile have been suggested as a mean to obtain good device characteristics on bulk substrate. In this work, V_TH variability impact of RDF on 65 nm-node deeply retrograde MOSFETs and conventional planar bulk MOSFETs were studied by using TCAD simulation. The simulated results showed that the deeply retrograde MOSFETs have 5 mV lower σ-V_TH (ΔA_VT between two devices is 1.06  mV·μm) than conventional planar bulk MOSFETs at the same I_off level (0.2 nA/μm). The ideal BOX profile structure simulated results showed that the thinner the low doping surface layer for deeply retrograde MOSFETs, the higher the V_TH variability. Our finding suggest that deeply retrograde MOSFETs are inherently less sensitive to V_TH variability due to RDF and channel length than conventional planar bulk MOSFETs and can be feasible for post-CMOS technology.     

Extraction of gate-edge workfunction of metal gate and its impact on scaled MOSFETs

The gate-edge properties of a metal/high-k gate stack are of crucial importance, but they have not been quantitatively investigated. In this paper, we have proposed a new method for extracting the local workfunction of the gate electrode by using a sideways overturned stack. We revealed that the TaSiN workfunction on their 10-nm long gate-edges shifted for 0.1 eV after a 1000 °C annealing. Based on these parameters, we simulated the impact of the gate-edge metamorphoses (GEM) and found that GEM increased the threshold voltage for scaled devices with a 60-nm long or shorter gate without suppressing a short-channel effect.     

The influence of stud bumping stress on device degradation in scaled MOSFETs

This paper presents the effect of area bumping on device degradation in scaled metal-oxide-semiconductor field-effect transistors (MOSFETs). We have investigated the gate channel length dependence of g_m degradation after stud bumping above the MOSFETs and changes in the charge pumping currents for those devices. The von Mises’s equivalent stress is used to simulate the distribution of mechanical stress at the gate edges. From the relationship between the distribution of the von Mises’s equivalent stress and the change in the charge pumping currents after stud bumping, we show that stress concentrates within 0.1 μm of the gate edges. Furthermore, by estimating the amount of increased interface-state density we predicted that stud bumping stress greatly influences the device degradation of scaled MOS devices.     

A gigabit MOS logic circuit with buried channel MOSFETs

An MOS frequency divider operating with gigabit clock rate has been realized to show the potential of MOS logic circuits for high-speed applications. The divider was constructed with buried channel MOSFETs as the basic elements. A master-slave flip-flop that was constructed with the enhancement/depletion type NAND gates was used for the divider. The basic gates were designed using full 1 /spl mu/m patterning rules. For the fabrication of these very fine circuits, photomasks made by an electron-beam system were applied and sputter etching was employed to form fine patterns such as the polysilicon gate and contact holes. The maximum counting frequency of 1.64 GHz and the shortest propagation delay time of 72.5 ps/gate with a fundamental gate were obtained.     

源端射频干扰下SRAM的抗扰性分析

目前已有一些在ESD和电磁干扰下存储器行为的表征研究,但对静态随机存取存储器(SRAM)的连续波抗扰度的频率响应特性的研究很少.文章研究了 SRAM在射频电磁干扰下的失效行为与机理.对SRAM芯片进行射频干扰测试发现,SRAM失效行为与其工作模式相关.使用Hspice进行晶体管级仿真.结果表明,SRAM处于数据保持时,...     

Band gap engineered resistor for mitigating linear energy transfer sensitivities in scaled submiron CMOS technology SRAM cells

Use of cross-coupling latch resistors is a prime method of mitigating single event upsets (SEU). Scaling has dramatically reduced ability of using this technique because of the large area needed as well as high temperature coefficient of resistance (TCR) of lightly doped polysilicon resistors. We present results of a study of the electrical properties of Al_1?xIn_xN films resistor which offers distinct advantage over polysilicon resistors. The films were grown on silicon nitride by magnetron sputter deposition at room temperature. Sheet resistance in the range of 8–10 kΩ/□ was reproducibly grown. The resistor film is thermally stable with TCR of less than minus 0.09%/°C for temperature range of minus 55 °C to +125 °C.     

Effects of wave function penetration into the gate-oxide onself-consistent modeling of scaled MOSFETs

Effects of wave function penetration into gate-oxide on properties of scaled nMOS devices in deep submicron regime are studied, taking into account the penetration effects on the solutions of both Schrodinger's and Poisson's equations. Numerical results show that penetration effects on properties of inversion layers become more important with scaling down of device dimensions. These effects are also more pronounced at strong inversion     

Analysis and optimization of SDOI structure to maximize the intrinsic performance of extremely scaled MOSFETs

The advantages of using elevated S/D formed on oxide shallow trench isolation are studied in detail. By careful design, the short channel short channel effects can be suppressed by the elevated source/drain (S/D) structure. In addition, the S/D region parasitic capacitance is significantly suppressed by the silicon-on-insulator (SOI)-like S/D structure. Tradeoff between series resistance and gate-to-drain Miller capacitance can be achieved by carefully selecting the gate spacer thickness. With careful optimization of device geometry, both the gate-delay and power consumption can be significantly reduced together. Design guideline and potential performance gain with the S/D-on-insulator structure is discussed.     

Weighing in on logic scaling trends

In this paper, scaling trends and the associated challenges are discussed from the perspective of the 2001 International Technology Roadmap for Semiconductors (ITRS) for both high-performance and low-power logic technologies. Starting from the overall chip circuit requirements, MOSFET and front-end process integration technology requirements, scaling trends, and challenges are discussed, as well as some of the key potential solutions to the challenges, along with the long-term issues and possible solutions for mobility improvement and optimal scaling for very small transistors. Potential solutions include eventual use of high-k gate dielectrics, metal gate electrodes, and perhaps nonclassical MOSFET devices such as double-gate SOI     

Low-voltage transient bipolar effect induced by dynamicfloating-body charging in scaled PD/SOI MOSFETs

An increased significance of the parasitic bipolar transistor (BJT) in scaled floating-body partially depleted SOI MOSFETs under transient conditions is described. The transient parasitic BJT effect is analyzed using both simulations and high-speed pulse measurements of pass transistors in a sub-0.25 μm SOI technology. The transient BJT current can be significant even at low drain-source voltages, well below the device breakdown voltage, and does not scale with technology. Our analysis shows that it can be problematic in digital circuit operation, possibly causing write disturbs in SRAMs and decreased retention times for DRAMs. Proper device/circuit design, suggested by our analysis, can however control the problems     

Characteristics of the full CMOS SRAM cell using body-tied TG MOSFETs (bulk FinFETs)

In this paper,the operational six-transistor SRAM cell characteristic was demonstrated using body-tied triple-gate MOSFETs (bulk FinFETs). A cell size of 0.79 /spl mu/m/sup 2/ was achieved with 90-nm node technology, using four levels of W and Al interconnects. A static noise margin of 280 mV was obtained at V/sub CC/ of 1.2 V by applying bulk FinFETs, and compared with those of typical optimized control devices and nanoscale planar channel MOSFETs. The characteristics of the bulk FinFETs were compared with those of nanoscale planar channel MOSFETs, and analyzed in detail by changing nanoscale active width (or fin width). Fabrication process issues for the bulk FinFETs were explained in terms of poly-Si gate over-etching and silicidation on nanoscale fin bodies. Also, input and output characteristics of the individual and parallel arrayed transistors were shown and analyzed.     

High-Voltage Auxiliary Power Supply Using Series-Connected MOSFETs and Floating Self-Driving Technique

This paper deals with high-voltage auxiliary switching-mode power supplies (SMPSs). An overview of the state of the art is given, and a novel solution is proposed. The proposed solution is based on a single-ended flyback or forward topology with the main switch arranged as a series connection of two metal-oxide-semiconductor field-effect transistors (MOSFETs). The bottom MOSFET is driven directly by an ordinary control circuit and gate driver, while the top MOSFET is driven by a floating self-supplied gate driver. The floating gate driver is connected to the input filter capacitors' midpoint. This gate driver plays two roles: driving of the top MOSFET and control of distribution of the blocking voltage among the series-connected MOSFETs, in steady state as well as during commutation. The series connection of lower voltage MOSFETs has two important advantages compared to that of a single high-voltage MOSFET: lower conduction losses and lower cost. When several switches are series connected, each switch supports a fraction of the total blocking voltage, and therefore, each switch can be rated for lower voltage. The total on-state resistance and the cost of such a switch arrangement are lower compared to that of a single switch that supports the full blocking voltage. The proposed SMPS is theoretically analyzed and experimentally verified. The experimental results are presented and discussed.     

Separation of effects of statistical impurity number fluctuationsand position distribution on Vth fluctuations in scaled MOSFETs

We have investigated the effect of the statistical “position” distribution of dopant atoms on threshold voltage (V_th) fluctuations in scaled MOSFETs. The effects of impurity “number” fluctuations and impurity “position” distribution are successfully separated in two-dimensional simulation for fully-depleted (FD) SOI MOSFETs. It is found that the contribution by the position distribution is closely related to the charge sharing factor (CSF) and the effect of the impurity position distribution becomes dominant as CSF is degraded. Consequently, the contribution ratio of the impurity position distribution is kept almost constant when the device is properly scaled     

A 1.5-ns 256-kb BiCMOS SRAM with 60-ps 11-K logic gates

A 1.5-ns address access time, 256-kb BiCMOS SRAM has been developed. To attain this ultra-high-speed access time, an emitter-coupled logic (ECL) word driver is used to access 6-T CMOS memory cells, eliminating the ECL-MOS level-shifter time delay. The RAM uses a low-power active pull down ECL decoder. The chip contains 11-K, 60-ps ECL circuit gates. It provides variable RAM configurations and general logic functions. RAM power consumption is 18 W; chip power consumption is 35 W. The chip is fabricated by using a 0.5-μm BiCMOS process. The memory cell size is 58 μm² and the chip size is 11×11 mm     

Single-trap-induced random telegraph noise for FinFET,Si/Ge Nanowire FET,Tunnel FET,SRAM and logic circuits

In this paper, we comprehensively review the impacts of single-trap-induced random telegraph noise (RTN) on FinFET, Ge/Si Nanowire FET and Tunnel FET (TFET). The resulting influences on the thermionic-based current conduction such as FinFET, Si-NW FET and Ge-NW FET (at low drain bias) as well as interband tunneling dominated current conduction such as TFET and high-drain-biased Ge-NW FET are extensively addressed in device and circuit level. The location of the trap is shown to have profound impacts and the impacts vary with bias conditions and trap types. The worst-case analysis of the stability/performance and leakage/delay for all possible trapping/detrapping RTN combinations are investigated for FinFET, Si-/Ge-NW FETs and TFET based 6T/8T SRAM cells and logic circuits.     

A scaled, high-performance (4.5 fJ) bipolar device in a 0.35 μmhigh-density BiCMOS SRAM technology

We present the performance improvements obtained both by scaling the Selectively Compensated Collector (SCC) BJT and by using a modified Current-Mode Logic (CML) gate configuration. Scaling the perimeter parameter by using the (tighter) bitcell design rules results in a ~30% reduction in parasitic capacitances, and a 23% lower power-delay product; reducing it from 48 fJ to 37 fJ. The greatest return comes from using a modified CML gate, which has an n-MOS current source. At a supply voltage of 1.1 V, and at 40 μA switching current, the minimum power-delay product of this CML gate is a silicon-substrate bipolar record 4.5 fJ     

一种SRAM单双端口转换电路的设计与实现

介绍了一种用于单端口SRAM的单双端口转换电路.利用该转换电路,可以使单端口SRAM实现双端口SRAM的功能.这种转换电路将外部两个端口的信号进行转换和优先权分配,使外部两个端口的并行操作在内部用单端口SRAM依次完成.这样,从外部看来,单端口SRAM就具有了双端口SRAM的全部功能.用这种转换电路生成的双端口SRAM与相同容量的传统双端口SRAM相比,面积显著减少.基于SMIC 0.13μm标准CMOS工艺,设计了转换电路.后仿真结果显示,该转换电路实现了预期功能.