2D grid architectures for the DFT and the 2D DFT

New algorithms for the DFT and the 2-dimensional DFT are presented. The DFT and the 2-dimensional DFT matrices can be expressed as the Kronecker product of DFT matrices of smaller dimension. These algorithms are synthesized by combining the efficient factorization of the Kronecker product of matrices with the highly hardware efficient recursive implementation of the smaller DFT matrices, to yield these algorithms. The architectures of the processors implementing these algorithms consist of 2-dimensional grid of processing elements, have temporal and spatial locality of connections. For computing the DFT of sizeN or for the 2D DFT of sizeN=N ₁ byN ₁, these algorithms require 2N multipliers and adders, take approximately computational steps for computing a transform vector, and take approximately computation steps between the computation of two successive transform vectors.     

Orthogonal cycle transforms of stochastic matrices

In this paper we investigate new Fourier series with respect to orthonormal families of directed cycles , which occur in the graph of a recurrent stochastic matrixP. Specifically, it is proved thatP may be approximated in a suitable Hilbert space by the Fourier series . This approach provides a proof in terms of Hilbert space of the cycle decomposition formula for finite stochastic matricesP.     

Finite-Memory Systems

Let K be a field, k and n positive integers and let matrices with coefficients in K. For any function

BIBO Stability of D-Dimensional Filters

Consider the class of d-dimensional causal filters characterized by a d-variate rational function analytic on the polydisk . The BIBO stability of such filters has been the subject of much research over the past two decades. In this paper we analyze the BIBO stability of such functions and prove necessary and sufficient conditions for BIBO stability of a d-dimensional filter. In particular, we prove if a d-variate filter H(z) analytic on has a Fourier expansion that converges uniformly on the closure of , then H(z) is BIBO stable. This result proves a long standing conjecture set forth by Bose in [3].     

On the Scalability of 2-D Discrete Wavelet Transform Algorithms

The ability of a parallel algorithm to make efficient use of increasing computational resources is known as its scalability. In this paper, we develop four parallel algorithms for the 2-dimensional Discrete Wavelet Transform algorithm (2-D DWT), and derive their scalability properties on Mesh and Hypercube interconnection networks. We consider two versions of the 2-D DWT algorithm, known as the Standard (S) and Non-standard (NS) forms, mapped onto P processors under two data partitioning schemes, namely checkerboard (CP) and stripped (SP) partitioning. The two checkerboard partitioned algorithms (Non-standard form, NS-CP), and as (Standard form, S-CP); while on the store-and-forward-routed (SF-routed) Mesh and Hypercube they are scalable as (NS-CP), and as (S-CP), respectively, where M ² is the number of elements in the input matrix, and (0,1) is a parameter relating M to the number of desired octaves J as . On the CT-routed Hypercube, scalability of the NS-form algorithms shows similar behavior as on the CT-routed Mesh. The Standard form algorithm with stripped partitioning (S-SP) is scalable on the CT-routed Hypercube as M ² = (P ²), and it is unscalable on the CT-routed Mesh. Although asymptotically the stripped partitioned algorithm S-SP on the CT-routed Hypercube would appear to be inferior to its checkerboard counterpart S-CP, detailed analysis based on the proportionality constants of the isoefficiency function shows that S-SP is actually more efficient than S-CP over a realistic range of machine and problem sizes. A milder form of this result holds on the CT- and SF-routed Mesh, where S-SP would, asymptotically, appear to be altogether unscalable.     

Linear phase FIR approximation of magnitude response |1/ω| for maximal flatness at an arbitrary frequency ω0, 0<ω0<π*

In many signal processing situations, the desired (ideal) magnitude response of the filter is a rational function: (a digital integrator). The requirements of a linear phase response and guaranteed stable performance limit the design to a finite impulse response (FIR) structure. In many applications we require the FIR filter to yield a highly accurate magnitude response for a narrow band of frequencies with maximal flatness at an arbitrary frequency ₀ in the spectrum (0, ). No techniques for meeting such requirements with respect to approximation of are known in the literature. This paper suggests a design by which the linear phase magnitude response can be approximated by an FIR configuration giving a maximally flat (in the Butterworth sense) response at an arbitrary frequency ₀, 0<₀<^*. A technique to compute exact weights for the design has also been given.     

Planar defects and double-domain epitaxy in epitaxial YSi<Subscript>2−x</Subscript> and ErSi<Subscript>2−x</Subscript> thin films on Si substrates

Interfacial reactions of Y and Er thin films on both (111)Si and (001)Si have been studied by transmission electron microscopy (TEM). Epitaxial rare-earth (RE) silicide films were grown on (111)Si. Planar defects, identified to be stacking faults on planes with 1/6 displacement vectors, were formed as a result of the coalescence of epitaxial silicide islands. Double-domain epitaxy was found to form in RE silicides on (001)Si samples resulting from a large lattice mismatch along one direction and symmetry conditions at the silicide/(001)Si interfaces. The orientation relationships are [0001]RESi_2−x// Si, RESi_2−x//(001)Si and [0001]RESi_2−x/ Si, RESi_2−x//(001)Si. The density of staking faults in (111) samples and the domain size in (001) samples were found to decrease and increase with annealing temperature, respectively.     

Effect of off-orientation of seed crystal on silicon carbide (SiC) single-crystal growth on the (11 $$\bar 2$$ 0) surface0) surface

The effect of off-orientation growth has been investigated in terms of stacking fault formation during physical vapor transport (PVT) growth of silicon carbide (SiC) single crystals on the (11 0) seed crystal surface. Occurrence of stacking fault formation is largely dependent on the direction of off-orientation, and basal plane stacking fault density is significantly reduced by growing the crystals on a (11 0) seed crystal off-oriented toward 〈0001〉. The density of the basal plane stacking faults rapidly decreases from 100–150 cm⁻¹ to ∼10 cm⁻¹ as the degree of off-orientation is increased from 0 to 10 deg. The results are interpreted in the framework of microscopic facet formation during PVT growth, and the introduction of off-orientation of seed crystal is assumed to prevent (01 0) and (10 0) microfacet formation on the (11 0) growing surface through modification of the surface growth kinetics and to suppress the stacking fault formation. An erratum to this article is available at .     

CORDIC-Based Computation of ArcCos

CORDIC-based algorithms to compute cos and are proposed. The implementation requires a standard CORDIC module plus a module to compute the direction of rotation, this being the same hardware required for the extended CORDIC vectoring, recently proposed by the authors [T. Lang and E. Antelo, IEEE Transactions on Computers, vol. 47, no. 7, 1998, pp. 736–749.]. Although these functions can be obtained as a special case of this extended vectoring, the specific algorithm we propose here presents two significant improvements: (1) it uses the same datapath width as the standard CORDIC, even when t has 2n bits (to achieve a granularity of 2^–n for the whole range). In contrast, the extended vectoring unit requires about 2n bits. (2) no repetitions of iterations are needed (the extended vectoring needs some repetitions). The proposed algorithm is compatible with the extended vectoring and, in contrast with previous implementations, the number of iterations and the delay of each iteration are the same as for the conventional CORDIC algorithm.     

Potentials on the hexagonal grid

The aim of this paper is to give an explicit computation for the potential generated by a dipole on a hexagonal grid. Such a computation will be expressed as the Fourier transform of a distribution on the bidimensional torus .     

A Symbolic Circuit Analysis-Oriented Algorithm for Finding a Common Tree of the Current and Voltage Graphs

A fundamental problem of symbolic analysis of electric networks when using the signal-flow (SFG) graph method is to find the common tree of the current and voltage graph ( and , respectively). In this paper we introduce a novel method in order to determine a common tree of both graphs, which may be used to obtain the symbolic network transfer function when carrying out the small-signal analysis of linear(ised) circuits.     

How to construct constant-round zero-knowledge proof systems for NP

Constant-round zero-knowledge proof systems for every language in are presented, assuming the existence of a collection of claw-free functions. In particular, it follows that such proof systems exist assuming the intractability of either the Discrete Logarithm Problem or the Factoring Problem for Blum integers.     

Use of TCP Decoupling in Improving TCP Performance over Wireless Networks

We propose using the TCP decoupling approach to improve a TCP connection's goodput over wireless networks. The performance improvement can be analytically shown to be proportional to , where MTU is the maximum transmission unit of participating wireless links and HP_Sz is the size of a packet containing only a TCP/IP header. For example, on a WaveLAN [32] wireless network, where MTU is 1500 bytes and HP_Sz is 40 bytes, the achieved goodput improvement is about 350%. We present experimental results demonstrating that TCP decoupling outperforms TCP reno and TCP SACK. These results confirm the analysis of performance improvement.     

A 5.8 GHz Low Noise Amplifier for Wireless LAN Applications in Silicon Bipolar Technology

A monolithic integrated low-noise amplifier for operation in the 5.8-GHzband is described. Two different versions have been implemented where the biasing wasadapted to allow operation over a different range of supply voltage. At 5-V, theamplifiers gain is about 17-dB, with a noise figure of 4.2-dB and 1-dB compressionpoint at –15-dBm input power. The circuits have been designed utilizing a0.6-micron silicon bipolar production technology, featuring npn transistors with and of about20-GHz.     

The Design of a 2-V 900-MHz CMOS Bandpass Amplifier

A 900 MHz low-power CMOS bandpassamplifier suitable for the applications of RFfront-end in wireless communication receiversis proposed and analyzed. In this design, thetemperature compensation circuit is used tostabilize the amplifier gain so that theoverall amplifier has a good temperaturestability. Moreover, the compact tunablepositive-feedback circuit is connected to theintegrated spiral inductor to generate thenegative resistance and enhance its value. The simple diode varactor circuit isadopted for center-frequency tuning. These twoimproved circuits can reduce the powerdissipation of the amplifier. An experimentalchip fabricated by 0.5 mdouble-poly-double-metal CMOS technologyoccupies a chip area of ; chip area. The measuredresults have verified the performance of thefabricated CMOS bandpass amplifier. Under a2-V supply voltage, the measured quality factoris tunable between 4.5 and 50 and the tunablefrequency range is between 845 MHz and 915 MHz. At , the measured is 20 dB whereas thenoise figure is 5.2 dB in the passband. Thegain variation is less than 4 dB in the rangeof 0–80^°C. The dc powerdissipation is 35 mW. Suitable amplifier gain,low power dissipation, and good temperaturestability make the proposed bandpass amplifierquite feasible in RF front-endapplications.     

A kinetic study of structured surface relief patterning of GaP (\bar 1\bar 1\bar 1)

Orientation dependent etching of photolithographically patterned GaP was investigated using solutions of HCl:CH₃COOH:H₂O₂. The pattern was prepared using standard ultraviolet lithography and was a two-dimensional grid with an 18 μm repeat, consisting of 15 μm squares separated by 3 μm spaces. The mask sides were aligned along the and directions. Under appropriate etching conditions, high quality arrays of pyramids were prepared. These pyramids were defined by , and facets. It was shown that the etching process depended on the degree of solution aging after initial mixing. For a freshly prepared solution, the etching rate showed an inverse dependence on time. For short etching times (below 5 min), an intermediate etching profile was followed, while for long times (greater than 5 min) etching was kinetically controlled. We demonstrated that controlled etching at extremely low rates (0.1–0.5 μm/min) is feasible with this new approach.     

Creep behavior of eutectic Sn-Cu lead-free solder alloy

Tensile creep behavior of precipitation-strengthened, tin-based eutectic Sn-0.7Cu alloy was investigated at three temperatures ranging from 303–393 K. The steady-state creep rates cover six orders of magnitude (10⁻³−10⁻⁸ s⁻¹) under the stress range of σ/E=10⁻⁴−10⁻³. The initial microstructure reveals that the intermetallic compound Cu₆Sn₅ is finely dispersed in the matrix of β-Sn. By incorporating a threshold stress, σ _th, into the analysis, the creep data of eutectic Sn-Cu at all temperatures can be fitted by a single straight line with a slope of 7 after normalizing the steady-state creep rate and the effective stress, indicating that the creep rates are controlled by the dislocation-pipe diffusion in the tin matrix. So the steady-state creep rate, , can be expressed as exp , where Q_c is the activation energy for creep, G is the temperature-dependent shear modulus, b is the Burgers vector, R is the universal gas constant, T is the temperature, σ is the applied stress, A is a material-dependent constant, and , in which σ _OB is the Orowan bowing stress, and k_R is the relaxation factor. An erratum to this article is available at .     

Practical Aspects of Off-Axis Illumination in Optical Nanolithography

The practical aspects are analyzed of off-axis illumination in optical lithography below the Rayleigh resolution. For major light-source aperture configurations, fundamental lower limits are identified on the lithographic factor , where L is the mask linewidth,NA is the numerical aperture of the objective, and is the wavelength. A practical approach is discussed to the calculation of the attainable values of k ₁ for different aperture configurations, allowing for the forbidden-pitch phenomenon.