一类动态S盒的构造与差分性质研究

该文对有限域的逆与仿射变换复合得到的动态S盒进行了研究。首先给出了动态S盒变换差分概率的刻画方法,并给出了动态S盒变换的差分对应是不可能差分对应的充分必要条件及不可能差分的个数。接着给出了动态S盒变换最大差分概率的上界及可达性。最后利用模拟实验的方法研究了由随机S盒来构造的动态S盒的差分性质。理论和实验分析都表明,这类动态S盒变换具有远好于单个S盒的差分特性。     

布尔函数法实现S盒在FPGA中的应用

S盒是一种非线性部件,在密码算法中占有重要的地位.在密码算法的FPGA实现过程中,S盒的实现一定程度上决定了算法的运行性能.传统的方法是利用FPGA内部集成的存储块生成查找表的方式实现.采用布尔函数方法实现S盒目前应用较少,该方法在某些情况下能提高FPGA中算法的运行性能,在实现输入位宽越小的S盒时越具有优势.文中以AES算法的S盒为例,给出了基于布尔函数实现S盒的步骤及仿真结果和电路延时分析.     

基于增强型延时感知CSE算法的AES S盒电路优化设计

针对高级加密标准（AES）S-盒优化,提出了一种增强型延时感知公共项消除（CSE）算法.该算法能够在不同延时约束条件下优化多常数乘法运算电路,并给出从最小延时到最小面积全范围的面积-延时设计折中.采用该算法优化了基于冗余有限域算术的S盒实现电路,确定了延时最优、面积最优的两种S盒构造.实例优化结果表明所提出算法的优化效率高、优化结果整体延时小.所设计的S盒电路基于65nm CMOS工艺库综合,结果表明,对比于已有文献中S盒复合域实现电路,所提出面积最优S盒电路的面积-延时积最小,比目前最小面积与最短延时的S盒组合逻辑分别减少了17.58%和19.74%.     

AES类S盒与Camellia类S盒的代数复杂度分析

S盒是很多分组密码算法唯一的非线性部件,它的密码学性质对分组密码的安全性至关重要。该文主要研究与有限域上逆变换仿射等价S盒的代数复杂度问题,利用有限域上的线性化多项式给出了两类S盒的最大代数复杂度,并得到了Camellia类S盒退化为AES类S盒的一个充分必要条件。     

基于S函数的BP神经网络PID控制器及Simulink仿真

BP网络在人工神经网络中应用最为广泛,文中给出基于MATLAB语言的BP神经网络PID控制器的S函数实现,在此基础上建立BP神经网络PID控制器的Simulink仿真模型,最后给出了该仿真模型应用在非线性对象中的仿真结果.     

可分特征的刻画及其自动化分析应用

基于可分性质的自动化分析是评估分组密码抵抗积分分析能力的有效方法,其关键在于建立自动化分析模型时对密码部件和基本运算的可分特征刻画。通过研究可分性质的传播规律,给出其可分特征的线性不等式刻画,首次实现S盒和逻辑与运算的等价刻画,给出自动化积分分析的基本思想和分析流程,并应用于ISO标准分组算法CLEFIA,得到10轮的积分区分器,是目前最长的积分区分器。     

Keccak类S盒的线性性质研究

该文将Keccak的S盒一般化为n元Keccak类S盒，研究了Keccak类S盒的线性性质。证明了这类S盒的相关优势的取值都为0或\begin{document}${2^{ - k}}$\end{document}，其中且，并且对于此范围内的任意k，都存在输入输出掩码使得相关优势取到；证明了当输出掩码确定时，其非平凡相关优势都相等；给出了非平凡相关优势为最大值时的充要条件与计数，解决了这类S盒的Walsh谱分布规律问题。     

基于多项式基的Camellia算法S盒硬件优化

该文提出一种基于不可约多项式的Camellia算法S盒的代数表达式，并给出了该表达式8种不同的同构形式。然后，结合Camellia算法S盒的特点，基于理论证明给出一种基于多项式基的S盒优化方案，此方法省去了表达式中的部分线性操作。相对于同一种限定门的方案，在中芯国际(SMIC)130 nm工艺库中，该文方案减少了9.12%的电路面积；在SMIC 65 nm工艺库中，该文方案减少了8.31%的电路面积。最后，根据Camellia算法S盒设计中的计算冗余，给出了2类完全等价的有限域的表述形式，此等价形式将对Camellia算法S盒的优化产生积极影响。     

域元素分量代数表达式的研究

本文提出了有限域上的一个新性质:用变元为域元素的多项式表示域元素的分量.基于等价类的划分、线性方程组的求解和标准基之对偶基的计算,提出了域元素分量代数表达式的三种求法.以此解释了Rijndael算法S盒代数表达式复杂度低的本质原因,给出其分量函数间等价关系的一种直接证明方法.     

对AES算法的S盒布尔函数分析

分组密码的安全性很大程度上取决于分组密码中唯一的非线性结构S盒。论文对AES的S盒的代数性质进行分析,采用布尔函数的方法,先得到S盒的真值表,再求解S盒的布尔函数表达式,根据布尔函数表达式计算得出S盒的平衡性、正交性、线性性、差分均匀性质、鲁棒性、非线性性等代数性质,说明AES的S盒的安全性。     

Structural Cryptanalysis of SASAS

In this paper we consider the security of block ciphers which contain alternate layers of invertible S-boxes and affine mappings (there are many popular cryptosystems which use this structure, including the winner of the AES competition, Rijndael). We show that a five-layer scheme with 128-bit plaintexts and 8-bit S-boxes is surprisingly weak against what we call a multiset attack, even when all the S-boxes and affine mappings are key dependent (and thus completely unknown to the attacker). We tested the multiset attack with an actual implementation, which required just 2¹⁶ chosen plaintexts and a few seconds on a single PC to find the 2¹⁷ bits of information in all the unknown elements of the scheme.     

一种基于多态忆阻器的电压型神经网络电路

提出了一种基于多态忆阻器的神经网络电路硬件实现方法。采用2⁸ bit的惠普忆阻模型来构建存储权重的双忆阻稳定结构,结合了低功耗轨到轨运放技术以及寄存器技术,设计了模值与极性分离的绝对值电路,以及以忆阻器为核心、可进行正负浮点数运算的权值网络矩阵电路。通过Verilog-A编写激活单元,实现了多层忆阻神经网络。该电路采用并行输入和模拟信号处理方式,控制简单,无需中间数据缓存。实验结果表明,该方法有效提升了以忆阻器为核心的人工神经网络的稳定性和运行效率。     

Area, Delay, and Power Characteristics of Standard-Cell Implementations of the AES S-Box

Cryptographic substitution boxes (S-boxes) are an integral part of modern block ciphers like the Advanced Encryption Standard (AES). There exists a rich literature devoted to the efficient implementation of cryptographic S-boxes, wherein hardware designs for FPGAs and standard cells received particular attention. In this paper we present a comprehensive study of different standard-cell implementations of the AES S-box with respect to timing (i.e. critical path), silicon area, power consumption, and combinations of these cost metrics. We examine implementations which exploit the mathematical properties of the AES S-box, constructions based on hardware look-up tables, and dedicated low-power solutions. Our results show that the timing, area, and power properties of the different S-box realizations can vary by up to almost an order of magnitude. In terms of area and area-delay product, the best choice are implementations which calculate the S-box output. On the other hand, the hardware look-up solutions are characterized by the shortest critical path. The dedicated low-power implementations do not only reduce power consumption by a large degree, but they also show good timing properties and offer the best power-delay and power-area product, respectively.     

Robust low-sensitivity Adaline neuron based on Continuous Valued Number System

In this article Continuous Valued Number System is studied as an alternative method for implementing Analog Neural Networks. Continuous Valued Number System is analog in nature and employs digit level analog modular arithmetic. The information redundancy among the digits allows efficient operations using analog circuitry with arbitrary accuracy. The general operations in this number system are more precise than regular analog operations, thus enabling us to implement large size analog neural networks with more precision. In this article, function evaluation properties of the Continuous Valued Number System are introduced. These key properties are used for developing analog Adaline with a nonlinear activation function. Stochastic modeling of a network of such elements is carried out which indicates that the proposed network has low sensitivity to implementation errors.     

一种实现最佳用户检测的非线性优化神经网络

本文提出并讨论了实现码分多址（CDMA）系统上最佳多用户检测（MUD）的一种神经网络方法。该方法通过将最佳多用户检测视为非线性优化组合问题，利用神经网络能有效求解非线性优化问题的优势，导出了一种非线性优化神经网络来实现最佳多用户检测，理论分析和计算机模拟表明，所提出的神经网络具有可实时应用的动态性能和较传统方法优越得多的误码率性能和抗多址干扰的性能。     

A prototype 3D optically interconnected neural network

We report the implementation of a prototype three-dimensional (3D) optoelectronic neural network that combines free-space optical interconnects with silicon-VLSI-based optoelectronic circuits. The prototype system consists of a 16-node input, 4-neuron hidden, and a single-neuron output layer, where the denser input-to-hidden-layer connections are optical. The input layer uses PLZT light modulators to generate optical outputs which are distributed over an optoelectronic neural network chip through space-invariant holographic optical interconnects. Optical interconnections provide negligible fan-out delay and allow compact, purely on-chip electronic H-tree type fan-in structure. The small prototype system achieves a measured 8-bit electronic fan-in precision and a calculated maximum speed of 640 million interconnections per second. The system was tested using synaptic weights learned off system and was shown to distinguish any vertical line from any horizontal one in an image of 4×4 pixels. New, more efficient light detector and small-area analog synapse circuits and denser optoelectronic neuron layouts are proposed to scale up the system. A high-speed, feed-forward optoelectronic synapse implementation density of up to 10⁴/cm² seems feasible using new synapse design. A scaling analysis of the system shows that the optically interconnected neural network implementation can provide higher fan-in speed and lower power consumption characteristics than a purely electronic, crossbar-based neural network implementation     

神经记忆的电阻网络综合

本文提出了从神经系统功能进行网络综合的观点。对神经网络的记忆功能进行了研究,建立了数学模型,并用分段线性电阻网络进行综合。所得到的非线性电阻网络除具有并行性、实时性、分布性和自适应等一系列人工神经网络的特点外,网络中各参数由网络所应记忆模式和特征向量的解析式给出,这比传统的人工神经网络具有较强的直观性,便于实际应用。     

神经网络用于相关噪声的自适应抵消

本文提出了一种在自适应噪声抵消器中应用模拟神经网络计算自适应线性滤波器权值的方法，权值的计算时间随线性滤波器的阶数的增加而减小。由于神经网络的实时处理能力。该网络可以用于愉速的噪声抵消。当噪声的自相关时间较线性滤波抽头的总地时间为小时时，此时的神经网络相当于一细胞神经网络，这就大大简化了该网络ＶＬＳＩ的实施。本文最后给出了实例模拟。结果令人十分满意。     

Holographic implementation of a fully connected neural network

A holographic implementation of a fully connected neural network is presented. This model has a simple structure and is relatively easy to implement, and its operating principles and characteristics can be extended to other types of networks, since any architecture can be considered as a fully connected network with some of its connections missing. The basic principles of the fully connected network are reviewed. The optical implementation of the network is presented. Experimental results which demonstrate its ability to recognize stored images are given, and its performance and analysis are discussed based on a proposed model for the system. Special attention is focused on the dynamics of the feedback loop and the tradeoff between distortion tolerance and image-recognition capability of the associative memory     

密钥控制的多S盒Rijndael算法

根据AESS盒的设计思想构造出了一批密码性能良好的S盒,并从方差的角度对它们的雪崩概率进行了分析。在此基础上,对Rijndael算法中的字节代换步骤SubBytes进行改进,从而提出了一种基于密钥控制的多S盒的Rijndael算法。实验结果表明,改进后的算法对差分攻击的抵抗能力有所提高,雪崩效应更趋合理。