一种高转换速率衬底电位选择电路的设计

本文基于0.5μm 5V DPTM CMOS工艺设计了一款用于LED驱动芯片的衬底电位选择电路。该电路采用峰值电流镜作为偏置,使其在低电压下能够正常工作,并运用源端输入带正反馈的比较器,使得电路具有一定的迟滞和高的转换速率,最后巧妙的设计了输出级,使输出结果尽可能的与芯片中的最高电压相等。仿真结果显示,比较器的转换速率为55.7V/μs,并且具有0.2V的迟滞,满足设计要求。     

一种增益提升和摆率增强的电流镜放大器

针对低压低功耗条件下传统电流镜运算放大器电压增益和摆率严重降低的问题,提出了一种新型增益提升和摆率增强的CMOS电流镜放大器,并对其小信号增益和摆率进行了详细分析。理论分析表明,在不影响单位增益频率和相位裕度等小信号特性的同时,极大地提高了增益和摆率。仿真结果表明,与传统的CMOS电流镜放大器相比,该新型CMOS电流镜放大器的增益提高了15 dB,正、负摆率分别提高到传统放大器的146倍和187倍。     

Process corner detection by skew inverters for 500 MHZ 2×VDD output buffer using 40-nm CMOS technology

A PVT detection and compensation technique is proposed to automatically adjust the slew rate of a high-speed 2×VDD output buffer. Based on the detected PVT (Process, Voltage, Temperature) corner, the output buffer will turn on different current paths correspondingly to either increase or decrease the output driving current such that the slew rate of the output signal is adaptive. The proposed design is implemented using a typical 40 nm CMOS process to justify the slew rate compensation performance. By on-silicon measurements, the data rate is 500/460 MHz given 0.9/1.8 V supply voltage with a 20 pF load. Particularly, the maximum slew rate improvement is 8%, the core area of the proposed design is 0.052×0.254 mm², the maximum slew rate is 0.53 (V/ns), and the area overhead is only 31% for one single output buffer.     

Multibit resonant tunneling diode SRAM cell based on slew-rateaddressing

We propose and demonstrate a resonant-tunneling diode (RTD) based memory cell in which N bits are stored in a series combination of N RTDs without internal node contacts. The slew rate of an applied voltage signal determines the circuit switching dynamics and allows addressing of the bits. We verify slew rate dependent switching order of up to four series RTDs experimentally and through SPICE simulation incorporating a physics-based RTD model. The new addressing scheme allows N bits to be stored in a stack of N vertically integrated RTDs compared to log₂ (N) bits in previous demonstrations. We demonstrate a two-bit two-RTD static memory cell based on the new method     

A CMOS voltage buffer with slew-rate enhancement

A high slew-rate CMOS voltage buffer has been presented in this article. The slew-rate enhancement is achieved by an embedded driver stage activated by internal nodes in the voltage buffer through capacitive coupling. The capacitive coupling provides one-shot auto-off feature for the driver stage. Therefore, the drive stage can be turned off automatically after activation. The auto-off feature of the proposed driver stage guarantees a reliable operation. The proposed voltage buffer is implemented in a commercial 0.35-μm CMOS technology. The active chip area is 345 μm × 246 μm. The single supply voltage is 3.3 V, and the quiescent current is about 7 μA. When the proposed buffer drives a capacitive load of 220 pF, the measured positive and negative slew rates are 0.714 and 1.548 V/μs, respectively. The improvement corresponds to about 22 times for the positive slew rate and 48 times for the negative slew rate when comparing with the voltage buffer without the proposed the slew-rate enhancement circuit.     

改进型折叠式共源共栅运算放大器电路的设计

在套筒式共源共栅、折叠式共源共栅运放中,折叠式共源共栅运算放大器凭借较大的输出摆幅和偏置电压的较低等优点而得到广泛运用。但是,折叠式的这些优势是以牺牲较大的功耗、较低的电流利用率而换取的。本文以提高电流利用率为着手点设计了一种改进的折叠式共源共栅运算放大器,在相同的电压和负载下改进的折叠式共源共栅运算放大器能显著提升跨导、压摆率和噪声性能。仿真结果表明在相同功耗和面积的条件下,改进的折叠式共源共栅运算放大器的单位增益带宽和压摆率是折叠式共源共栅运放的3倍。     

大电流、高稳定性的LDO线形稳压器

以设计输出电流为800mA的高稳定线性稳压器(low-dropout voltage regulator,LDO)为目标,利用工作在线性区的MOS管具有压控电阻特性,构造零点跟踪电路以抵消随输出电流变化的极点,并且采用了改进型米勒补偿方案使电路系统具有60°的相位裕度,达到了大输出电流下的高稳定性要求.另外,分析了电路在转换发生时电路结构参数和负载整流特性的关系,提出了一种能在瞬间提供大电流的转换速率加强电路,达到了在负载电流从800mA到10mA跳变时,输出电压的跳变量控制在60mY以内,并且最长输出电压恢复时间在500μs以内.芯片采用CSMC公司的0.6μm CMOS数模混合信号工艺设计,并经过流片和测试,测试结果验证了设计方案.     

Analysis of the power delivery path from the 12-V VR to the microprocessor

This paper offers a thorough analysis of the power delivery path. Based on the power delivery path model, the current slew rate of each loop is derived. The relationship between the inductor current slew rate of the voltage regulator (VR) and the bandwidth is also derived. Then, the level of the voltage spike across the capacitors of each loop is determined, after which the relationship between the bandwidth and the capacitance can be plotted. We find that for today's power delivery structure, the bulk capacitors can be eliminated as long as the bandwidth is pushed beyond 350 kHz. The experimental results of a 2-MHz two-stage 12-V VR verify this analysis.     

An Output-Capacitorless Low-Dropout Regulator With Direct Voltage-Spike Detection

An output-capacitorless low-dropout regulator (LDO) with a direct voltage-spike detection circuit is presented in this paper. The proposed voltage-spike detection is based on capacitive coupling. The detection circuit makes use of the rapid transient voltage at the LDO output to increase the bias current momentarily. Hence, the transient response of the LDO is significantly enhanced due to the improvement of the slew rate at the gate of the power transistor.      

A Power‐Efficient CMOS Adaptive Biasing Operational Transconductance Amplifier

This paper presents a two‐stage power‐efficient class‐AB operational transconductance amplifier (OTA) based on an adaptive biasing circuit suited to low‐power dissipation and low‐voltage operation. The OTA shows significant improvements in driving capability and power dissipation owing to the novel adaptive biasing circuit. The OTA dissipates only 0.4 μW from a supply voltage of ±0.6 V and exhibits excellent high driving, which results in a slew rate improvement of more than 250 times that of the conventional class‐AB amplifier. The design is fabricated using 0.18‐μm CMOS technology.     

Micropower CMOS S&H circuit for ambient intelligence applications

A novel sample and hold (S&H) circuit is presented based on the use of a class AB CMOS operational transconductance amplifier with very high slew rate and very low static power consumption. The circuit has been fabricated in a 0.5 /spl mu/m double-poly CMOS technology. The quiescent power consumption is only 80 /spl mu/W using a dual supply voltage of /spl plusmn/1.35 V. The S&H occupies 0.075 mm/sup 2/ of silicon area.     

A novel architecture for improving slew rate in FinFET-based op-amps and OTAs

A new architecture for improvement of slew rate (SR) of an op-amp or an operational transconductance amplifier (OTA) in FinFET technology is proposed. The principle of operation of the proposed architecture is based on a set of additional current sources which are switched on, only when OTA should provide a high current, usually for charge or discharge of large load capacitor. Therefore, the power overhead is less compared to conventional high SR designs. The commonly used two-stage Miller-compensated op-amp, designed and optimized in sub 45 nm FinFET technology with 1 V single supply voltage, is used as an example for demonstration of the proposed method. For the same FinFET technology and with optimal design, it is shown that the slew rate of the op-amp is significantly improved. The slew rate is improved from 273 to $5590\mathrm{V}/\mathrm{\mu }\mathrm{s}$ for an input signal with a rise time of 100 ps. The other performance measures such as gain and phase margin remain unchanged with the additional circuitry used for slew rate enhancement.     

交流提升与有源反馈补偿的无片外电容CMOS低压差稳压器

A capacitor-free CMOS low-dropout （LDO） regulator for system-on-chip （SoC） applications is presented. By adopting AC-boosting and active-feedback frequency compensation （ACB-AFFC）, the proposed LDO regulator, which is independent of an off-chip capacitor, provides high closed-loop stability. Moreover, a slew rate enhancement circuit is adopted to increase the slew rate and decrease the output voltage dips when the load current is suddenly switched from low to high. The LDO regulator is designed and fabricated in a 0.6 μm CMOS process. The active silicon area is only 770 × 472 μm2. Experimental results show that the total error of the output voltage due to line variation is less than ±0.197%. The load regulation is only 0.35 mV/mA when the load current changes from 0 to 100 mA.     

A wide-band, low-power, high slew rate voltage-feedback operationalamplifier

A wide-band low-power voltage-feedback operational amplifier on a 3 GHz, 40 V complementary bipolar technology is described. The class AB input stage takes advantage of some current-boost transistors which enhance and linearize the slew-rate during large-signal operation without increasing the power consumption. The triple-buffered output stage provides 100 mA of load current maintaining good linearity. Since the circuit design and technology development were concurrent, several different circuits were stepped into one wafer to fully characterize the process and identify the best product candidates. The low-current version of this chip has a quiescent current of 2.5 mA, 2000 V/μs slew rate and gain bandwidth of 110 MHz. The medium-current version draws only 6.5 mA of current at the same supply voltage while the slew rate increases to 3500 V/μs and bandwidth to 210 MHz. Both parts are operational from +/-2.75 V to +/-18 V supply range. Die size is 51 mils by 76 mils on a poly-emitter CB process     

Frequency compensation of two stage CMOS circuit using negative capacitance and flipped voltage follower

This paper presents a new and compact two stage CMOS structure with enhanced gain-bandwidth product (GBW) and high slew rate. The frequency compensation technique employed here comprises of a negative capacitance cell and a flipped voltage follower (FVF). The use of negative capacitance lowers the parasitic capacitance of preceding stage and thereby achieves significant improvement in GBW. The FVF acts as a voltage buffer and exploits pole-zero cancellation technique. The required compensation capacitor is very small so it can save chip area. The workability of the proposed circuit has been verified by using Mentor Graphics Eldo simulation tool with TSMC CMOS 0.18 µm process parameters. The simulated results show a GBW of 1.2 GHz and average slew rate of 88 V/µs with a power consumption of 6.3 mW.     

High slew rate current mode transconductance error amplifier for low quiescent current output-capacitorless CMOS LDO regulator

This paper presents a CMOS low quiescent current output-capacitorless low-dropout regulator (LDO) based on a high slew rate current mode transconductance amplifier (CTA) as error amplifier. Using local common-mode feedback (LCMFB) in the proposed CTA, the order of transfer characteristic of the circuit is increased. Therefore, the slew rate at the gate of pass transistor is enhanced. This improves the LDO load transient characteristic even at low quiescent current. The proposed LDO topology has been designed and post simulated in HSPICE in a 0.18 µm CMOS process to supply the load current between 0 and 100 mA. The dropout voltage of the LDO is set to 200 mV for 1.2–2 V input voltage. Post-layout simulation results reveal that the proposed LDO is stable without any internal compensation strategy and with on-chip output capacitor or lumped parasitic capacitances at the output node between 10 and 100 pF. The total quiescent current of the LDO including the current consumed by the reference buffer circuit is only 3.7 µA. A final benchmark comparison considering all relevant performance metrics is presented.     

Hybrid charge control for stick-slip piezoelectric actuators

The article describes an analog electronic circuit for driving stick-slip piezoelectric linear actuators. The task for the amplifier is to provide a high-voltage asymmetric sawtooth-like signal and feed it into a capacitive load. Generation of excessive heat must be avoided while maximizing the slew rate. In order to guarantee a steady translation, the hysteretic behaviour of the piezoelectric material must be compensated. Combination of a charge control scheme with switching is proposed as an efficient solution. Laboratory experiments confirm the superiority of this tailored solution over other existing techniques based on versatile linear voltage amplifiers.     

Switched-capacitor FSK modulator and demodulator in CMOS technology

A switched-capacitor FSK modulator/demodulator built in silicon-gate CMOS technology is described. The modulator is based on a programmable harmonic oscillator using two stray-insensitive integrators. The centerpiece of the FSK demodulator is a switched-capacitor voltage-controlled oscillator. A simple post-detection processor restores the digital data. Both circuits have been designed for the 600-baud modem channel with 1500 Hz center frequency and /spl plusmn/200 Hz frequency shifts, but the demodulator operates in the 1200-baud channel as well. Due to dynamic biasing the operational amplifiers feature high slew rate, high voltage gain, and low power for capacitive loads.     

A Buck-Derived Topology With Improved Step-Down Transient Performance

The slew rate of the inductor current is limited by the inductance value and the voltage across the inductor. In a buck converter, when the controller is saturated, the voltage across the inductor during a step-up load transient is $V_{rm in}-V_{rm out}$, while during a step-down load transient, it is $-V_{rm out}$. Thus, a buck converter with a large conversion ratio offers asymmetrical step-up and step-down transients. Since the rate of fall of the inductor current is much slower than the rate of rise of the inductor current, the step-down transient lasts longer than the step-up transient for the same change in the load current. The step-down slew rate can be increased by reducing the inductance, but it results in higher inductor current ripple, and hence, higher losses in the power converters. In this paper, we present a novel topology for improving the step-down load transients without reducing the inductance value. The scheme operates only during load transients and restores to the normal operating conditions during steady-state operation. It provides reduced voltage overshoots and faster settling times in output voltage during such transients. The proposed scheme is tested on a 1-V/12-A buck converter switching at 1 MHz, and the experimental results are presented.      

Low-voltage micropower super class AB CMOS OTA

Novel class AB OTA topologies result from the combined use of local common-mode feedback and class AB input stages. They can operate at low supply voltage and feature very low static power consumption, bandwidth enhancement, and very high slew rate. Measurement results of a 0.5 /spl mu/m CMOS prototype show slew rate and unity-gain bandwidth enhancement factors of 180 and 4.5, respectively, compared to a conventional one-stage OTA.