异质外延碲镉汞薄膜的位错抑制技术

本文简述了MBE异质外延碲镉汞薄膜位错形成机理、位错在外延层中的演化过程以及位错抑制理论,总结了国内外CdTe缓冲层的位错抑制技术、HgCdTe薄膜的位错抑制技术,分析了热循环退火技术各个要素与位错密度变化之间的关系。     

Si/CdTe复合衬底HgCdTe液相外延材料的生长与性能分析

通过改进推舟液相外延技术,成功地在(211)晶向Si/CdTe复合衬底上进行了HgCdTe液相外延生长,获得了表面光亮的HgCdTe外延薄膜.测试结果表明,(211)Si/CdTe复合衬底液相外延HgCdTe材料组分及厚度的均匀性与常规(111)CdZnTe衬底HgCdTe外延材料相当;位错腐蚀坑平均密度为(5～8)×105 cm-2,比相同衬底上分子束外延材料的平均位错密度要低一个数量级;晶体的双晶半峰宽达到70″左右.研究结果表明,在发展需要低位错密度的大面积长波HgCdTe外延材料制备技术方面,Si/CdTe复合衬底HgCdTe液相外延技术可发挥重要的作用.     

Si/CdTe复合衬底HgCdTe液相外延材料的生长与性能分析

通过改进推舟液相外延技术,成功地在(211)晶向Si/CdTe复合衬底上进行了HgCdTe液相外延生长,获得了表面光亮的HgCdTe外延薄膜.测试结果表明,(211)Si/CdTe复合衬底液相外延HgCdTe材料组分及厚度的均匀性与常规(111)CdZnTe衬底HgCdTe外延材料相当;位错腐蚀坑平均密度为(5～8)×105 cm-2,比相同衬底上分子束外延材料的平均位错密度要低一个数量级;晶体的双晶半峰宽达到70″左右.研究结果表明,在发展需要低位错密度的大面积长波HgCdTe外延材料制备技术方面,Si/CdTe复合衬底HgCdTe液相外延技术可发挥重要的作用.     

CdTe/Si复合衬底Ex-situ退火研究

复合衬底CdTe/ZnTe/Si的晶体质量是导致随后外延的HgCdTe外延膜高位错密度的主要原因之一,因此如何提高复合衬底CdTe/Si晶体质量是确保硅基碲镉汞走上工程化的关键所在。降低复合衬底CdTe/Si位错密度方法一般有:生长超晶格缓冲层、衬底偏向、In-situ退火和Ex-situ退火等,本文主要研究Ex-situ退火对复合衬底CdTe/Si晶体质量的影响。研究表明复合衬底经过Ex-situ退火后位错密度最好值达4.2×105cm-2,双晶半峰宽最好值达60arcsec。     

Si基CdTe/HgCdTe分子束外延材料的位错抑制

基于GaAs/Si材料中位错的运动反应理论,修正获得CdTe/Si和HgCdTe/Si外延材料中的位错运动反应模型.采用快速退火方法对Si基HgCdTe外延材料进行位错抑制实验研究,实验结果与理论曲线基本吻合,从理论角度解释了不同高温热处理条件对材料体内位错的抑制作用.对于厚度为4～10μnn的CdTe/Si进行500...     

MBE生长中波HgCdTe薄膜材料温度控制

报道在品格失配GaAs衬底上分子束外延CdTe缓冲层和中波HgCdTe薄膜的温度控制过程.通过红外测温仪监测样品表面温度,来改变加热功率,从而把温度控制在需要的生长温度范围.通过此方法,可以把CdTe生长时样品的表面温度控制在±5℃,MCT生长时可以达到±1℃.生长得到的样品,表面光亮,组分、厚度均匀性好,X射线双晶回摆曲线半峰宽为72 arcsec.     

HWE 生长大面积CdTe/ CdZnTe/ Si 薄膜的结构和形貌分析

用热壁外延法(HWE) 生长直径30mm 的CdTe/ CdZnTe/ Si 薄膜,经XRD 测试说明它是 晶面为(111) 取向的立方闪锌矿结构。SEM对Si 衬底、CdZnTe 缓冲层和CdTe 薄膜三层分别测试,结果发现: Si 衬底表面结构粗糙,CdZnTe 缓冲层较Si 衬底表面结构细致,CdTe 薄膜较CdZnTe 缓冲层表面结构光滑细密,即缺陷较CdZnTe 缓冲层少很多。通过对该片子照像看出其表面如镜面。由此说明大面积CdTe/ CdZnTe/ Si 薄膜可用HWE 技术制备。     

多层HgCdTe异质外延材料的热退火应力分析

前期研究采用高温热处理方法,获得了抑制位错的最佳退火条件.通过比对实验,发现不同衬底上HgCdTe表面的CdTe钝化层在热处理过程中对位错的抑制作用各有不同.结合晶格失配应力和热应力对不同异质结构进行理论计算,借助X射线摇摆曲线的倒易空间分析,解释了CdTe钝化层对HgCdTe位错抑制的影响作用.     

溅射AlN技术对GaN基LED性能的影响

研究了在图形蓝宝石衬底(PSS)上利用磁控溅射制备AlN薄膜的相关技术,随后通过采用金属有机化学气相沉积(MOCVD)在相关AlN薄膜上生了长GaN基LED.通过一系列对比实验,分析了AlN薄膜的制备条件对GaN外延层晶体质量的影响,研究了AlN薄膜溅射前N2预处理功率和溅射后热处理温度对GaN基LED性能的作用机制.实验结果表明:AlN薄膜厚度的增加,导致GaN缓冲层成核密度逐渐升高和GaN外延膜螺位错密度降低刃位错密度升高;N2处理功率的提升会加剧衬底表面晶格损伤,在GaN外延膜引入更多的螺位错;AlN热处理温度的升高粗化了表面并提高了GaN成核密度,使得GaN外延膜螺位错密度降低刃位错密度升高;而这些GaN外延膜位错密度的变化又进一步影响到LED的光电特性.     

HWE 生长大面积CdTe/ CdZnTe/ Si 薄膜的结构和形貌分析

用热壁外延法(HWE)生长直径30mm的CdTe／CdZnTe／Si薄膜，经XRD测试说明它是晶面为(111)取向的立方闪锌矿结构。SEM对Si衬底、CdZnTe缓冲层和CdTe薄膜三层分别测试，结果发现：Si衬底表面结构粗糙，CdZnTe缓冲层较Si衬底表面结构细致，CdTe薄膜较CdZnTe缓冲层表面结构光滑细密，即缺陷较CdZnTe缓冲层少很多。通过对该片子照像看出其表面如镜面。由此说明大面积CdTe／CdZnTe／Si薄膜可用HWE技术制备。     

Modeling of in situ monitored laser reflectance during MOCVD growth of HgCdTe

An effective way to in situ monitor the metalorganic chemical vapor deposition (MOCVD) of HgCdTe/CdTe/ZnTe on GaAs or GaAs/Si substrates is presented. Specular He-Ne laser reflectance was used to in situ monitor the growth rates, layer thickness, and morphology for each layer in the grown multilayer structure. In situ monitoring has enabled precise measurements of ZnTe nucleation and CdTe buffer layer thicknesses. Monitoring the constancy of reflectance during the thicker CdTe buffer growth where absorption in the CdTe reduces reflectance to just the surface component has led to optimum buffer growth ensuring good quality of subsequently grown HgCdTe. During the interdiffused multilayer process (IMP) HgCdTe growth, because multiple interfaces are present within the absorption length, a periodic reflectance signal is maintained throughout this growth cycle. A theoretical model was developed to extract IMP layer thicknesses from in situ recorded experimental data. For structures that required the growth of a larger band gap HgCdTe cap layer on top of a smaller band gap active layer, in situ monitored reflectance data allowed determination of alloy composition in the cap layer as well. Continuous monitoring of IMP parameters established the stability of growth conditions, translating into depth uniformity of the grown material, and allowed diagnosis of growth rate instabilities in terms of changes in the HgTe and CdTe parts of the IMP cycle. A unique advantage of in situ laser monitoring is the opportunity to perform “interactive” crystal growth, a development that is a key to real time MOCVD HgCdTe feedback growth control.     

Dislocation profiles in HgCdTe(100) on GaAs(100) grown by metalorganic chemical vapor deposition

We studied dislocation etch pit density (EPD) profiles in HgCdTe(lOO) layers grown on GaAs(lOO) by metalorganic chemical vapor deposition. Dislocation profiles in HgCdTe(lll)B and HgCdTe(lOO) layers differ as follows: Misfit dislocations in HgCdTe(lll)B layers are concentrated near the HgCdTe/CdTe interfaces because of slip planes parallel to the interfaces. Away from the HgCdTe/CdTe interface, the HgCdTe(111)B dislocation density remains almost constant. In HgCdTe(lOO) layers, however, the dislocations propagate monotonically to the surface and the dislocation density decreases gradually as dislocations are incorporated with increasing HgCdTe(lOO) layer thicknesses. The dislocation reduction was small in HgCdTe(lOO) layers more than 10 μm from the HgCdTe/CdTe interface. The CdTe(lOO) buffer thickness and dislocation density were similarly related. Since dislocations glide to accommodate the lattice distortion and this movement increases the probability of dislocation incorporation, incorporation proceeds in limited regions from each interface where the lattice distortion and strain are sufficient. We obtained the minimum EPD in HgCdTe(100) of 1 to 3 x 10⁶ cm^-2 by growing both the epitaxial layers more than 8 μm thick.     

Heteroepitaxy of HgCdTe(112) infrared detector structures on Si(112) substrates by molecular-beam epitaxy

High-quality, single-crystal epitaxial films of CdTe(112)B and HgCdTe(112)B have been grown directly on Si(112) substrates without the need for GaAs interfacial layers. The CdTe and HgCdTe films have been characterized with optical microscopy, x-ray diffraction, wet chemical defect etching, and secondary ion mass spectrometry. HgCdTe/Si infrared detectors have also been fabricated and tested. The CdTe(112)B films are highly specular, twin-free, and have x-ray rocking curves as narrow as 72 arc-sec and near-surface etch pit density (EPD) of 2 × 10⁶ cm⁻² for 8 μm thick films. HgCdTe(112)B films deposited on Si substrates have x-ray rocking curve FWHM as low as 76 arc-sec and EPD of 3-22 × 10⁶ cm⁻². These MBE-grown epitaxial structures have been used to fabricate the first high-performance HgCdTe IR detectors grown directly on Si without use of an intermediate GaAs buffer layer. HgCdTe/Si infrared detectors have been fabricated with 40% quantum efficiency and R₀A = 1.64 × 10⁴ Ωm₂ (0 FOV) for devices with 7.8 μm cutoff wavelength at 78Kto demonstrate the capability of MBE for growth of large-area HgCdTe arrays on Si.     

Orientation dependence of HgCdTe epitaxial layers grown by MOCVD on Si substrates

Orientation dependence of HgCdTe epilayers grown by MOCVD on Si substrates was studied. Substrate orientation is considered to be one of the most sensitive factors to enable hetero-epitaxial growth on silicon substrates, especially in the case of a low temperature growth process. The present work was carried out with characterized features of a low temperature process for HgCdTe growth on Si and using a thin CdTe buffer layer. The (100), (100) misoriented toward [110], (311), (211), (111), and (331) oriented Si substrates were used in the present work. The best results were obtained on (211)Si substrates with an x-ray full width at half maximum of 153 arc sec for a 5 (im thickness HgCdTe layer and 69 arc sec for a 10 um thickness layer. It was found that the effective lattice mismatch of CdTe/Si heterosystem was reduced to 0.6% (for the 611 lattice spacing of CdTe and 333 spacing of Si) in the case of (133)CdTe/(211)Si.     

GaSb: A New Alternative Substrate for Epitaxial Growth of HgCdTe

In this work, GaSb is proposed as a new alternative substrate for the growth of HgCdTe via molecular beam epitaxy (MBE). Due to the smaller mismatch in both lattice constant and coefficient of thermal expansion between GaSb and HgCdTe, GaSb presents a better alternative substrate for the epitaxial growth of HgCdTe, in comparison to alternative substrates such as Si, Ge, and GaAs. In our recent efforts, a CdTe buffer layer technology has been developed on GaSb substrates via MBE. By optimizing the growth conditions (mainly growth temperature and VI/II flux ratio), CdTe buffer layers have been grown on GaSb substrates with material quality comparable to, and slightly better than, CdTe buffer layers grown on GaAs substrates, which is one of the state-of-the-art alternative substrates used in growing HgCdTe for the fabrication of mid-wave infrared detectors. The results presented in this paper indicate the great potential of GaSb to become the next generation alternative substrate for HgCdTe infrared detectors, demonstrating MBE-grown CdTe buffer layers with rocking curve (double crystal x-ray diffraction) full width at half maximum of ～60 arcsec and etch pit density of ～10⁶ cm^?2.     

Growth and properties of Hg1-xCdxTe on GaAs,with x − 0.27

The organometallic vapor phase epitaxy of HgCdTe onto (100)2°-(110) GaAs substrates is described in this paper. A buffer layer of CdTe has been grown prior to the growth of HgCdTe, to take up the large lattice mismatch with the GaAs. Considerations for the thickness of this buffer layer are outlined, and it is shown by quantitative Secondary Ion Mass Spectroscopy that there is negligible diffusion of gallium from the GaAs substrate for the growth conditions described. Hall effect measurements give mobilities comparable to those reported for bulk grown crystals. An extrinsicn-type carrier concentration of 2 × 10¹⁶/cm³ is obtained, and is mainly due to residual impurities in the starting chemicals. The alloy composition has been determined at 298 K by Fourier transform infrared transmission (FTIR) spectrometry; this is found to be extremely uniform over a 15 × 7 mm area, as evidenced by an overlapping of FTIR plots taken over this area. HgCdTe layers have been grown on buffer layers varying in thickness from 0.1 to 1.9μm. It is found that a buffer thickness of about 1.9μm or larger is required to obtain high quality HgCdTe, both in terms of the electrical characteristics (mobility and carrier concentration) and the infrared transmission curves (peak transmission).     

Recent Progress in MBE Growth of CdTe and HgCdTe on (211)B GaAs Substrates

Alternate substrates for molecular beam epitaxy growth of HgCdTe including Si, Ge, and GaAs have been under development for more than a decade. MBE growth of HgCdTe on GaAs substrates was pioneered by Teledyne Imaging Sensors (TIS) in the 1980s. However, recent improvements in the layer crystal quality including improvements in both the CdTe buffer layer and the HgCdTe layer growth have resulted in GaAs emerging as a strong candidate for replacement of bulk CdZnTe substrates for certain infrared imaging applications. In this paper the current state of the art in CdTe and HgCdTe MBE growth on (211)B GaAs and (211) Si at TIS is reviewed. Recent improvements in the CdTe buffer layer quality (double crystal rocking curve full-width at half-maximum?≈?30?arcsec) with HgCdTe dislocation densities of ≤10⁶?cm^?2 are discussed and comparisons are made with historical HgCdTe on bulk CdZnTe and alternate substrate data at TIS. Material properties including the HgCdTe majority carrier mobility and dislocation density are presented as a function of the CdTe buffer layer quality.     

Growth and Analysis of HgCdTe on Alternate Substrates

Dislocations generated at the HgCdTe/CdTe(buffer layer) interface are demonstrated to play a significant role in influencing the crystalline characteristics of HgCdTe epilayers on alternate substrates (AS). A dislocation density >10⁸?cm^?2 is observed at the HgCdTe/CdTe interface. Networks of dislocations are generated at the HgCdTe/CdTe interface. The dislocation networks are observed to entangle. Significant dislocation reduction occurs within a few microns of the HgCdTe/CdTe interface. The reduction in dislocation density as a function of depth is enhanced by annealing. Etch pit density and x-ray diffraction full-width at half-maximum values increase as a function of the lattice mismatch between HgCdTe epilayer and the buffer layer/substrate. The experimental results suggest that only by reducing HgCdTe/CdTe lattice mismatch will the desired crystallinity be achieved for HgCdTe epilayers on AS.     

Si Wafer Thinning Techniques Compatible With Epitaxy of CdTe Buffer Layers

Reduction of threading dislocation density is critical for improving the performance of HgCdTe detectors on lattice-mismatched alternative substrates such as Si. CdTe buffer layers grown by molecular beam epitaxy (MBE), with thicknesses on the order of 8 μm to 12 μm, have helped reduce dislocation densities in HgCdTe layers. In this study, the reduction of threading dislocation densities in CdTe buffer layers grown on locally thinned Si substrates was examined. A novel Si back-thinning technique was developed that maintained an epiready front surface and achieved Si thicknesses as low as 1.9 μm. Threading dislocation densities, acquired by defect decoration techniques, were reduced by as much as 60% for CdTe buffer layers grown on these thinned regions when compared with unthinned regions. However, this reduction is inconsistent with prior notions that threading dislocation propagation is dominated by image forces. Instead, the thickness gradient of thinned Si may play a larger role.