Physical design of testable CMOS digital integrated circuits

A methodology for physical testability assessment and enhancement, implemented with a set of test tools, is presented. The methodology, which can improve the physical design of testable CMOS digital ICs, is supported in realistic fault-list generation and classification. Two measures of physical testability, weighted class fault coverage and fault incidence, and one measure of fault hardness are introduced. The testability is evaluated prior to fault simulation; difficult-to-detect faults are located on the layout and correlated with the physical defects which originate them; and suggestions for layout reconfiguration are provided. Several design examples are described, ascertaining the usefulness of the proposed methodology. The proposed methodology demonstrated that stuck-at test sets only partially cover the realistic faults in digital CMOS designs. Moreover, it is shown that classical fault models of arbitrary faults are insufficient to describe the realistic fault set. Simulation results have shown that the fault set strongly depends on the technology and on the layout style     

测试性技术分析与试验验证刍议

测试性质量特性是武器装备试验考核内容之一,攸关武器装备能否快速地检测故障并隔离故障。文中阐述了装备测试技术设计、测试性试验需求和靶场验证方法,着重研究了测试性定性检查、定量检查的基本准则和实施途径。并指出故障特征的分析提取和样本集的有效生成是测试验证的关键,旨在为提升武器装备测试性试验能力提供参考。     

Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability

Path delay fault model is the most suitable model for detectingdistributed manufacturing defects which can cause delayfaults. However, the number of paths in a modern design can beextremely large and the path delay testability of many practicaldesigns is very low. In this paper we show how to resynthesize acombinational circuit in order to reduce the total number of paths inthe circuit. Our results show that it is possible to obtain circuitswith a significant reduction in the number of paths while notincreasing area and/or delay of the longest sensitizable path in thecircuit.Research on path delay testing shows that in many circuits a largeportion of paths does not have a test that can guarantee detection ofa delay fault. The path delay testability of a circuit would increaseif the number of such paths is reduced. We show that addition of asmall number of test points into the circuit can help reducing thenumber of such paths in the given design.     

悬臂梁光纤光栅磁场传感器

介绍一种新的磁场传感器的原理,传感元件为贴在等腰三角梁上的光纤光栅。实验上测得该传感器的灵敏度为18．1T/nm,与理论值17．6T／nm相吻合。     

Balance testing and balance-testable design of logic circuits

We propose a low-cost method for testing logic circuits, termed balance testing, which is particularly suited to built-in self testing. Conceptually related to ones counting and syndrome testing, it detects faults by checking the difference between the number of ones and the number of zeros in the test response sequence. A key advantage of balance testing is that the testability of various fault types can be easily analyzed. We present a novel analysis technique which leads to necessary and sufficient conditions for the balance testability of the standard single stuck-line (SSL) faults. This analysis can be easily extended to multiple stuck-line and bridging faults. Balance testing also forms the basis for design for balance testability (DFBT), a systematic DFT technique that achieves full coverage of SSL faults. It places the unit under test in a low-cost framework circuit that guarantees complete balance testability. Unlike most existing DFT techniques, DFBT requires only one additional control input and no redesign of the underlying circuit is necessary. We present experimental results on applying balance testing to the ISCAS 85 benchmark circuits, which show that very high fault coverage is obtained for large circuits even with reduced deterministic test sets. This coverage can always be made 100% either by adding tests or applying DFBT.This research was supported by the National Science Foundation under Grant No. MIP-9200526. Parts of this paper were published in preliminary form in Proc. 23rd Symp. Fault-Tolerant Computing, Toulouse, June 1993, and in Proc. 31st Design Automation Conf, San Diego, June 1994.     

A Strategy for Optimal Test Point Insertion in Analog Cascaded Filters

This paper presents a strategy for synthesizing analog cascaded filters with optimal test point insertion. The strategy is based on the implementation of a selective divide-and-conquer approach that permits to ensure high fault detection capabilities while limiting DFT penalties and reducing test time. The proposed solution relies on the evaluation of the filter testability at the different inputs and outputs of the cascaded blocks in order to add DFT only when this testability is not sufficient. Efficient testability evaluation is provided through high-level fault modeling and simulation.This revised version was published online in March 2005 with corrections to the first authors name and the cover date.     

一种布拉格光纤光栅加速度传感器

本文介绍了一种基于布拉格光纤光栅 (FBG)的加速度传感器设计。为了克服等截面悬臂梁的局限性 ,该设计采用等强度悬臂梁的形式。结果表明 :该种光纤加速度传感器具有良好的稳定性和较高的分辨率 (0 .0 0 5g) ,适合海洋平台等大型工程结构的加速度测量。     

Effects analysis of bias and excitation conditions on power output of an environmental vibration energy harvesting device using Fe-Ga slice

With the advent of low power VLSI designs and the mass manufacture of CMOS, the power consumption of wireless sensor nodes has been significantly reduced from mW to μW. This opens up a new and interesting research field, that is, the possibility of converting environmental vibration energy to electrical energy for supplying power to the sensors. In this paper, using magnetostrictive materials slice, that is Fe-Ga alloy, a device for harvesting environmental vibration energy is designed and tested. Compared with piezoelectric materials and Terfenal-D alloy, Fe-Ga alloy offers excellent properties for surviving in tough ambient vibration conditions, including higher energy conversion efficiency, longer life cycles, excellent toughness, reduced depolarization and higher flexibility, etc. The designing of vibration energy harvesting process is based on the coupling characteristics of magnetostrictive inverse effect and Faraday electromagnetic induction. The device consists of a Fe-Ga alloy cantilever beam with a magnetostrictive direction throughout the length. It has magnetostrictive inverse effect during vibration and the internal magnetization state will change. A cantilever beam is surrounded by a pickup coil and voltage is induced due to the magnetic field according to Faraday's law. The energy conversion principle among mechanical, magnetic and electric energy is described through a dynamic equation of motion and in conjunction with an electromagnetic conversion equation. The influence law of bias and excitation conditions on output voltage, power and other characteristics of device are investigated in comprehensive experiments. By knowing these influence laws, it is possible to choose an appropriate number of pick up coil for a definite load resistance, to set an appropriate working frequency range, pre-tightening force and pre-magnetized magnetic field such that a maximum power can be harvested. The results derived here can be used as a design guideline for future studies in optimal design and the modeling of vibration energy harvester and force sensor.     

测试性设计的主要目的和具体的实施方法

测试性设计的主要目的,就是要求反映被测对象的工作状态和隔离故障到现场更换模块。这两项任务,要求由机内检测设备(BITE)来实现。测试性设计不能局限于满足BITE的故障检测率和故障隔离率,它更关注故障隔离的平均时间。对预测和设计故障隔离时间和虚警率提出了一种实用方法,对落实测试性设计具有重要的意义。     

Yield improvement of a large area magnetic field sensor array usingredundancy schemes

The circuit design of a large area magnetic field sensor array (LAMSA) is described. This prototype is developed for applications in magnetic field mapping and tactile sensor arrays. To enable the production of such a large sensor system, redundancy schemes are implemented and a laser interconnection post fabrication technique is used for fault repairs. The design restructurable capabilities rely on local redundancy schemes for the sensor grid and global redundancy schemes for the surrounding control circuits. Experimental results obtained on a laser restructurable subarray of magnetic field sensor cells are shown. A study of the robustness of the local sensor grid redundancy schemes is presented     

Testable design of BiCMOS circuits for stuck-open fault detectionusing single patterns

Single BJT BiCMOS devices exhibit sequential behavior under transistor stuck-OPEN (s-OPEN) faults. In addition to the sequential behavior, delay faults are also present. Detection of s-OPEN faults exhibiting sequential behavior needs two-pattern or multipattern sequences, and delay faults are all the more difficult to detect. A new design for testability scheme is presented that uses only two extra transistors to improve the circuit testability regardless of timing skews/delays, glitches, or charge sharing among internal nodes. With this design, only a single vector is required to test for a fault instead of the two-pattern or multipattern sequences. The testable design scheme presented also avoids the requirement of generating tests for delay faults     

数字调谐系统芯片DTSO614的可测性设计

介绍了集成电路可测性设计的概念和分类方法,然后以数字调谐系统芯片DTS0614为例,具体介绍了其中的一种即针对性可测性设计方法,包括模块划分、增加控制线和观察点.最后给出了提高电路可测性的另一种方法--内建自测试方法.     

Tutorial on semiconductor memory testing

This article is a tutorial introduction to the field of semiconductor memory testing. It begins by describing the structure and operation of the main types of semiconductor memory. The various ways in which manufacturing defects and failure mechanisms can cause erroneous memory behavior are then reviewed. Next we describe the different contexts in which memories are tested together with the corresponding different types of tests. The closely related processes of fault modeling and test development are then summarized. Various design for testability strategies for memories are also presented. Finally, current trends in the design and testing of memory are outlined.This work was supported by the Natural Sciences and Engineering Research Council of Canada under grant OGP 0105567.     

二维纳米材料磁性探测的双臂微悬臂梁设计

磁共振弱力探测技术能够对物质实现非破坏性的高精度结构信息探测,在物理、生物、医学等领域有着非常重要的应用。该技术中,超灵敏悬臂梁是实现弱力探测的核心组成之一。近年来,二维纳米材料由于其奇特的物理特性得到了越来越多的关注。为实现对二维纳米材料磁性的探测,基于单臂微悬臂梁模型,利用差动放大的方法,提出了双臂微悬臂梁的设计,并分析了双臂微悬臂梁中上下球形磁探针内外部的磁场分布,最后以单晶硅悬臂梁和钐钴合金磁球探针为例,对该悬臂梁进行数值模拟,发现该方案能够显著提高悬臂梁的探测灵敏度。     

CNI外场检验仪的设计

基于第三代战机高性能电子战的特殊要求,设计CNI分系统（通信导航识别分系统）.为了方便外场检测CNI分系统内所有下挂设备总线数据通信情况以及满足分系统维护和排故,从硬件、软件、结构、电磁兼容性、可靠性、维修性、测试性、安全性等方面设计CNI外场检验仪,并针对了设计中的监控解析软件包开发等关键性问题进行分析并提出了解决措施.应用表明,该检验仪解决了CNI系统大数据量实时采集难、故障不易追溯的问题,在国内处于领先水平.     

航空电子系统的测试性及仿真研究

论述了仿真故障注入在测试性设计中的重要作用以及利用仿真进行测试性设计的几个重要环节。结合某飞机的凋堰电路给出了利用Pspice仿真软件研究电子产品测试性设计的方法，为测试设备的研制和开发提供一些新的思路。     

Constrained parity testing

A generalized testing technique called constrained parity testing is presented for detecting multiple stuck-at faults in any single-output irredundant combinational network by verifying the subparities of the network. Implementation independent testability conditions are established for single- and multiple-input stuck-at faults. A spanning parity signature (SPS) is introduced to detect vacuous faults, which include all the input stuck-at faults and a majority of all other multiple stuck-at faults. The SPS is considered for testing all stuck-at faults in networks with small numbers of fanout lines, and a method of deriving tests for nonvacuous faults is proposed. For networks with large fanouts, a hybrid scheme by combining with syndrome testing is suggested to eliminate or reduce the need for expensive fault simulation. The proposed technique is a theoretical generalization of many existing methods and offers advantages such as versatility, flexibility, low test volume, low test time, high fault coverage, and reduced fault simulation and test generation costs.     

Magnetic In-circuit Testing of Multiple Power and Ground Pins for Open Faults

The viability of magnetically detecting open faults among multiple power and ground pins of an integrated-circuit package is investigated. The experimental technique is based on injecting current to the leadframe through the chip, and individually sensing the lateral magnetic field of each VDD or GND lead on top of the package. Field distribution in sensor plane is analyzed in order to determine the interference conditions under which correct classification of pin continuity is possible. It is shown that field-based classification benefits from a mildly subtractive interference. Also proposed is a model-based algorithm by which lead currents are calculated from field readings. Classification on the basis of current is shown to be robust against interference. Predictions are verified with experimentation conducted on a PQFP package with a moving Hall sensor.     

Controller Resynthesis for Testability Enhancement of RTL Controller/Data Path Circuits

In this paper, we propose a controller resynthesis technique to enhance the testability of register-transfer level (RTL) controller/data path circuits. Our technique exploits the fact that the control signals in an RTL implementation are don't cares under certain states/conditions. We make an effective use of the don't care information in the controller specification to improve the overall testability (better fault coverage and shorter test generation time). If the don't care information in the controller specification leaves little scope for respecification, we add control vectors to the controller to enhance the testability. Experimental results with example benchmarks show an average increase in testability of 9% with a 3–4 fold decrease in test generation time for the modified implementation. The area, delay and power overheads incurred for testability are very low. The average area overhead is 0.4%, and the average power overhead is 4.6%. There was no delay overhead due to this technique in most of the cases.