Effects of neutral buried p-layer on high-frequency performance ofGaAs MESFETs

Fully ion-implanted n⁺ self-aligned GaAs MESFETs with Au/WSiN refractory metal gates have been fabricated by adopting neutral buried p-layers formed by 50-keV Be-implantation. S-parameter measurements and equivalent circuit fittings are discussed. When the Be dose is increased from 2×10¹² cm^-2 to 4×10¹² cm^-2, the maximum value of the cutoff frequency with a 0.2-μm gate falls off from 108 to 78 GHz. This is because a neutral buried player makes the intrinsic gate-source capacitance increase markedly, while its influence on gate-drain capacitance and gate-source fringing capacitance is negligible. The maximum oscillation frequency recovers, however, due primarily to the drain conductance suppression by the higher-concentration buried p-layer. An equivalent value of over 130 GHz has been obtained for both 0.2-μm-gate GaAs MESFETs     

Improvement of alpha-particle-induced soft-error immunity in a GaAsSRAM by a buried p-layer

Alpha-particle-induced soft-error immunity in a 1-kB GaAs SRAM was improved by a buried p-layer, which was formed in isolation regions as well as in FET regions and was designed to be completely depleted. The mean time between failures exceeded 10⁴ at an alpha-particle fluence of about 2.0×10⁴ cm^-2-s^-1 with a 1.0-μCi²⁴¹Am source. The alpha-particle energy had a peak at 4.0 MeV and was distributed from nearly 0 to 4.6 MeV. This value is five orders of magnitude better than that for a conventional SRAM without a buried p-layer. This improvement in the soft-error immunity can be achieved without increasing the access time or the power consumption by depleting the p-layer completely. Also discussed is the possibility of using a conductive p-layer scheme for higher integration of GaAs SRAMs     

Electrical properties of Si p+-n junctions for sub-0.25μm CMOS fabricated by Ga FIB implantation

p⁺-n junction diodes for sub-0.25-μm CMOS circuits were fabricated using focused ion beam (FIB) Ga implantation into n-Si (100) substrates with background doping of N_b=(5-10)×10 ¹⁵ and N_b⁺=(1-10)×10¹⁷ cm^-3. Implant energy was varied from 2 to 50 keV at doses ranging from 1×10¹³ to 1×10¹⁵ cm^-2 with different scan speeds. Rapid thermal annealing (RTA) was performed at either 600 °C or 700°C for 30 s. Diodes fabricated on N_b⁺ with 10-keV Ga⁺ exhibited a leakage current (^I_R) 100× smaller than those fabricated with 50-keV Ga⁺. Tunneling was determined to be the major current transport mechanism for the diodes fabricated on N_b⁺ substrates. An optimal condition for I_R on N_b⁺ substrates was obtained at 15 keV/1×10¹⁵ cm^-2. Diodes annealed at 600°C were found to have an I_R 1000× smaller than those annealed at 700°C. I-V characteristics of diodes fabricated on N_b substrates with low-energy Ga⁺ showed no implant energy dependence. I-V characteristics were also measured as a function of temperature from 25 to 200°C. For diodes implanted with 15-keV Ga ⁺, the cross-over temperatures between I_diff and I_g-r occurred at 106°C for N_b ⁺ and at 91°C for N_b substrates     

Characteristics including electron velocity overshoot for0.1-μm-gate-length GaAs SAINT MESFET's

Short-channel effects, substrate leakage current, and average electron velocity are investigated for 0.1-μm-gate-length GaAs MESFETs fabricated using the SAINT (self-aligned implantation for n⁺-layer technology) process. The threshold-voltage shift was scaled by the aspect ratio of the channel thickness to the gate length ( a/L_g). The substrate leakage current in a sub-quarter-micrometer MESFET is completely suppressed by the buried p layers and shallow n⁺-layers. The average electron velocity for 0.1- to 0.2-μm-gate-length FETs is estimated to be 3×10⁶ cm/s from the analysis of intrinsic FET parameters. This high value indicates electron velocity overshoot. Moreover, a very high f_T of 93.1 GHz has been attained by the 0.1-μm SAINT MESFET     

Electron transport in 0.15-μm gate In0.52Al0.48As/In0.53Ga0.47As HEMT

Magneto-transport and cyclotron resonance measurements were made to determine directly the density, mobility, and the effective mass of the charge carriers in a high-performance 0.15-μm gate In_0.52 Al_0.48As/In_0.53Ga_0.47As high-electron-mobility transistor (HEMT) at low temperatures. At the gate voltage V_G=0 V, the carrier density n _g under the gate is 9×10¹¹ cm^-2, while outside of the gate region n_g=2.1×10¹² cm^-2. The mobility under the gate at 4.2 K is as low as 400 cm²/V-s when V_G<0.1 V and rapidly approaches 11000 cm²/V-s when V_G>0.1 V. The existence of this high mobility threshold is crucial to the operation of the device and sets its high-performance region in V_G>0.1 V     

A possible scaling limit for enhancement-mode GaAs MESFETs in DCFLcircuits

A possible scaling limit for ion-implanted GaAs MESFETs with buried p-layer LDD structure has been numerically investigated. A Schottky-contact model with a thin interfacial layer and interface states was used to simulate the Schottky-barrier height of a scaled-down MESFETs. When enhancement-mode MESFETs in direct-coupled FET logic (DCFL) circuits are scaled down, the gate length can be reduced to 0.21 μm at an interface-state density of 6.6×10¹² cm^-2·eV^-1, when the barrier height is greater than 0.6 V, the threshold voltage is less than 0.1 V, and the channel aspect ratio is 8     

The new two-dimensional electron gas base HBT (2DEG-HBT):two-dimensional numerical simulation

The bipolar/FET characteristics of the 2DEG-HBT are analyzed extensively by a two-dimensional numerical simulator based on a drift-diffusion model. For bipolar operations at high collector current densities, it is confirmed that the cutoff frequency f_T is determined mainly by the collector transit time of holes and by the charging time of the extrinsic base-collector capacitance C _bc^EXT. The charging times of the emitter and base regions and the base transit time are shown to be negligible. A high cutoff frequency F_T (88 GHz) and current gain h_FE (760) are obtained for an emitter size of 1×10 μm², and undoped collector thickness of 150 nm, and a collector current density J_c of 10⁵ A/cm². The FET operation of the same 2DEG-HBT structure shows a threshold voltage V_th of 0.74 V, the transconductance G_m^max of 80 mS/mm, and maximum cutoff frequency F_T^max of 15 GHz. The dependence of the device performance on material parameters is analyzed extensively from a device design point of view     

0.2-μm gate-length atomic-planar doped pseudomorphic Al0.3Ga0.7As/In0.25Ga0.75As MODFETswith fT over 120 GHz

The authors report the DC and RF performance of nominally 0.2-μm-gate length atomic-planar doped pseudomorphic Al_0.3Ga_0.7As/In_0.25Ga_0.75As modulation-doped field-effect transistors (MODFETs) with f_T over 120 GHz. The devices exhibit a maximum two-dimensional electron gas (2 DEG) sheet density of 2.4×10¹² cm^-2, peak transconductance g _m of 530-570 mS/mm. maximum current density of 500-550 mA/mm, and peak current-gain cutoff frequency f_T of 110-122 GHz. These results are claimed to be among the best ever reported for pseudomorphic AlGaAs/InGaAs MODFETs and are attributed to the high 2 DEG sheet density, rather than an enhanced saturation velocity, in the In_0.25Ga_0.75As channel     

High-performance self-aligned (Al,Ga)As/(In,Ga)As pseudomorphicHIGFETs

Transconductance as high as 676 mS/mm at 300 K was observed to 0.7×10-μm² n-channel devices (HIGFETs) made on epilayers with Al_0.3Ga_0.7As insulator thickness of 200 Å and In_0.15Ga_0.85As channel thickness of 150 Å. An FET K value (K=W_g Uε/2aL_g) as large as 10.6 mA/V ² was also measured from another device with transconductance of 411 mS/mm. The high K values are achieved under normal FET operation without hole-injection or drain-avalanche breakdown effects. These results demonstrate the promise of pseudomorphic (Al,Ga)As/(In,Ga)As HIGFETs for high-performance circuit applications     

The sublinear relationship between index change and carrier densityin 1.5 and 1.3 μm semiconductor lasers

The carrier-induced index change was measured using a novel injection-reflection technique in combination with differential carrier lifetime data. The observed relation between index change and injected carrier density at bandgap wavelength is nonlinear and is approximately given by δn_act=-6.1×10^-14 ( N)^0.66 for a 1.5-μm laser and δn _act=-1.3×10^-14 (N)^0.68 for a 1.3-μm laser. The carrier-induced index change for a 1.3-μm laser at 1.53-μm wavelength is smaller and is given by δn _act=-9.2×10^-16 (N)^0.72      

A GaAs MESFET with a partially depleted p layer for SRAMapplications

A GaAs MESFET with a partially depleted p layer that has a specific application to SRAMs has been developed. The short-channel effect is well suppressed for gate lengths down to 0.5 μm by a rather dense p layer buried under the channel. Its acceptor ion dose is as high as 2×10¹² cm^-2, which corresponds to a partially depleted condition. As for applications for SRAMs, it is possible to attain fully functional 7-ns 4-kb SRAMs that are operative at 75°C by using the FET with a 1-μm gate. A chip yield of 22% has been achieved in a 3-in wafer     

Erase/write cycle tests of n-MOSFETs with Si-implantedgate-SiO2

To discuss the applicability of a MOSFET with Si-implanted gate-SiO₂ of 50 nm thickness to a non volatile random access memory (NVRAM) operating more than 3.3×10¹⁵ erase/write (E/W) cycles, E/W-cycle tests were performed up to 10¹¹ cycles by measuring the hysteresis curve observed in a source follower MOSFET in which a sine-wave voltage of 100 kHz was supplied to the gate. Degradations in the threshold-voltage window of 15 V and gain factor were scarcely observed in a MOSFET with Si-implantation at 50 keV/1×10¹⁶ cm^-2 at a gate voltage of ±40 V. Those degradations observed in a MOSFET with 25 keV/3×10¹⁶ cm^-2 were improved by lowering the gate voltage from ±40 V to ±30 V in sacrificing the smaller threshold-voltage window from 20 to 8.5 V     

Ultrahigh-frequency performance of submicrometer-gate ion-implantedGaAs MESFETs

A study of the high-frequency performance of short-gate ion-implanted GaAs MESFETs with gate lengths of 0.3 and 0.5 μm is discussed. Excellent DC and microwave performance have been achieved with an emphasis on the reduction of effective gate length during device fabrication. From f_t of 83 and 48 GHz for 0.3-0.5-μm gate devices, respectively, an electron velocity of 1.5×10⁷ cm/s is estimated. An f_t of 240 GHz is also projected for a 0.1-μm-gate GaAs MESFET. These experimental results are believed to be comparable to those of the best HEMTs (high-electron-mobility transistors) reported and higher than those generally accepted for MESFETs     

Minority-carrier transport parameters in heavily doped p-typesilicon at 296 and 77 K

Minority-carrier electron lifetime, mobility and diffusion length in heavily doped p-type Si were measured at 296 and 77 K. It was found that a 296 K μ_n (pSi)≈μ_n (nSi) for N _AA≲5×10¹⁸ cm^-3, while μ_n (pSi)/μ_n (nSi)≈1 to 2.7 for higher dopings. The results also show that for N_AA≲3×10¹⁹ cm^-3, D (pSi) at 77 K is smaller than that at 296 K, while for higher dopings D_n (pSi) is larger at 77 K than at 296 K. μ_n (pSi) at 77 K increases with the increasing doping above N_AA>3×10¹⁸ cm^-3, in contrast to the opposite dependence for μ_n (nSi) in n⁺ Si     

High-performance submicrometer undergated thin-film transistorswithout high-temperature rapid thermal annealing or plasma hydrogenation

High-performance submicrometer undergated thin-film transistors (TFTs) are fabricated without using high-temperature rapid thermal annealing or plasma hydrogenation. These processes are used in the state-of-the-art devices, but avoided in current manufacturing. For a 0.35-μm×0.35-μm device and a 0.7-μm×0.5-μm device, I_ON of 3 and 1.2 μA are obtained with ON/OFF current ratios of 4×10⁵ and 1.2×10⁸ , respectively, very close to that of state-of-the-art devices. A new lightly-doped-drain (LDD) structure is employed to improve I_ON reproducibility, which is difficult to achieve for deep-submicrometer devices with the conventional lightly-doped-offset (LDO) structure     

Electrical characterisation of Si-dopedGaAs0.5Sb0.5 on InP grown by molecular beamepitaxy

Between the growth temperatures of 490-520°C Si-doped GaAs_0.5Sb_0.5 changes from 1×10¹⁷ cm^-3 n-type to 2×10¹⁷ cm^-3 p-type. The scattering mechanisms of the n and p-type epilayers are investigated. The reproducibility and potential applications of the observed conduction type change are demonstrated by the fabrication of a pn diode     

Reduction of oxide charge and interface-trap density in MOScapacitors with ITO gates

The electrical properties of MOS capacitors with an indium tin oxide (ITO) gate are studied in terms of the number density of the fixed oxide charge and of the interface traps N_f and N _it, respectively. Both depend on the deposition conditions of ITO and the subsequent annealing procedures. The fixed oxide charge and the interface-trap density are minimized by depositing at a substrate temperature of 240°C at low power conditions and in an oxygen-rich ambient. Under these conditions, as-deposited ITO films are electrically conductive. The most effective annealing procedure consists of a two-step anneal: a 45-s rapid thermal anneal at 950°C in N₂, followed by a 30 min anneal in N₂/20% H₂ at 450°C. Typical values obtained for N_it and N_f are 4.2×10¹⁰ cm^-2 and 2.8×10¹⁰ cm^-2, respectively. These values are further reduced to 1.9×10¹⁰ cm^-2 and ≲5×10⁹ cm^-2, respectively, by depositing approximately 25 nm polycrystalline silicon on the gate insulation prior to the deposition of ITO     

A 0.4-μm gate-length AlGaAs/GaAs P-channel HIGFET with 127-mS/mmtransconductance at 77 K

WN-gate, p-channel AlGaAs-GaAs heterostructure insulated-gate field-effect transistors (HIGFETs) fabricated on a metalorganic vapor-phase epitaxy (MOVPE) wafer are discussed. A self-aligned Mg ion implantation (80 keV, 6×10¹³ cm^-2) annealed at 850°C in an arsine atmosphere and the control of the SiO₂ sidewall dimensions allow the fabrication of p-channel HIGFETs with a gate length smaller than 0.5 μm with low subthreshold current. P-channel HIGFETs with 0.4-μm gate lengths exhibit extrinsic transconductances as high as 127 mS/mm at 77 K and 54 mS/mm at 300 K     

Low-threshold-current-density 1.5 μm lasers using compressivelystrained InGaAsP quantum wells

A low-threshold current density (J_th) of 140 A/cm² for broad-area 1.5-μm semiconductor lasers with uncoated facets is demonstrated at a cavity length of 3.5 mm. This was achieved by the use of a single InGaAsP quantum well (QW) of 1.8% compressive strain inside a step-graded InGaAsP waveguide region. Low-cavity losses of 3.5 cm^-1 and a relatively wide quantum well as compared to InGaAs wells of equivalent strain contribute to this high performance. Double QW devices of 2 mm length showed threshold current densities of 241 A/cm². Quaternary single and double QWs of similar width but only 0. 9% strain gave slightly higher threshold current density values, but allowed growth of a 4 QW structure with a J_th of 324 A/cm² at L=1.5 mm     

High-transconductance insulating-gate InP/InGaAs buried p-bufferDH-MODFETs grown by MOVPE

Buried p-buffer double heterostructure modulation-doped field-effect transistors (BP DH-MODFETs) with an InGaAs quantum-well channel were fabricated with high transconductance and good breakdown voltage, by placing the metal gate directly on Fe-doped InP insulating layer. Excellent extrinsic DC transconductance of 560 mS/mm and a high gate-to-drain diode breakdown voltage (greater than 20 V) were achieved at room temperature with FETs of 1.2-μm gate length. Unity currently gain cutoff frequency f_T of 24 GHz and maximum oscillation frequency f_max of 60 GHz were demonstrated for a drain to source voltage V_DS=4 V, which corresponds to an average electron velocity of 2.2×10⁷ cm/s in the quantum well