共查询到18条相似文献,搜索用时 125 毫秒
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Si-SiGe材料三维CMOS集成电路技术研究 总被引:1,自引:0,他引:1
根据SiGe材料的物理特性,提出了一种新有源层材料的三维CMOS集成电路.该三维CMOS集成电路前序有源层仍采用Si材料,制作nMOS器件;后序有源层则采用SiGe材料,以制作pMOS器件.这样,电路的本征性能将由Si nMOS决定.使用MEDICI软件对Si-SiGe材料三维CMOS器件及Si-SiGe三维CMOS反相器的电学特性分别进行了模拟分析.模拟结果表明,与Si-Si三维CMOS结构相比,文中提出的Si-SiGe材料三维CMOS集成电路结构具有明显的速度优势. 相似文献
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根据SiGe材料的物理特性,提出了一种新有源层材料的三维CMOS集成电路.该三维CMOS集成电路前序有源层仍采用Si材料,制作nMOS器件;后序有源层则采用SiGe材料,以制作pMOS器件.这样,电路的本征性能将由Si nMOS决定.使用MEDICI软件对Si-SiGe材料三维CMOS器件及Si-SiGe三维CMOS反相器的电学特性分别进行了模拟分析.模拟结果表明,与Si-Si三维CMOS结构相比,文中提出的Si-SiGe材料三维CMOS集成电路结构具有明显的速度优势. 相似文献
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制备了氧化铪(HfO2)高k介质栅Si基Ge/SiGe异质结构肖特基源漏场效应晶体管(SB-MOSFET)器件,研究了n型掺杂Si0.16Ge0.84层对器件特性的影响,分析了n型掺杂SiGe层降低器件关态电流的机理。使用UHV CVD沉积系统,采用低温Ge缓冲层技术进行了材料生长,首先在Si衬底上外延Ge缓冲层,随后生长32 nm Si0.16Ge0.84和12 nm Ge,并生长1 nm Si作为钝化层。使用原子力显微镜和X射线衍射对材料形貌和晶体质量进行表征,在源漏区沉积Ni薄膜并退火形成NiGe/Ge肖特基结,制备的p型沟道肖特基源漏MOSFET,其未掺杂Ge/SiGe异质结构MOSFET器件的空穴有效迁移率比相同工艺条件制备的硅器件的高1.5倍,比传统硅器件空穴有效迁移率提高了80%,掺杂器件的空穴有效迁移率与传统硅器件的相当。 相似文献
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压阻加速度计的Au-Si共晶键合 总被引:3,自引:1,他引:3
通过将压阻加速度计上帽与结构片的键合 ( 36 5℃保温 10min) ,再进行下帽与结构片的键合 ( 380± 10℃保温2 0min) ,成功进行了三层键合 .测得的键合强度约为 2 30MPa.硅片 基体 /SiO2 /Cr/Au层和硅片之间键合时 ,SiO2 溶解而形成CrSi2 硅化物 .共晶反应因Cr层而被推迟 ,键合温度高出共晶温度 2 0℃左右 ,从而避免了由于Au元素向硅中扩入而造成的污染 ,进而避免可能造成的对集成微电子器件性能的影响 .试验还证明硅基体 SiO2 /Cr/Au/Poly Si/Au键合层结构设计模型也遵循这一键合过程中的原子扩散理论. 相似文献
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本文提出一种沟道长度为0.125 μm的异质结CMOS(HCMOS)器件结构.在该结构中,压应变的SiGe与张应变的Si分别作为异质结PMOS(HPMOS)与异质结NMOS(HNMOS)的沟道材料,且HPMOS与HNMOS为垂直层叠结构;为了精确地模拟该器件的电学特性,修正了应变SiGe与应变Si的空穴与电子的迁移率模型;利用Medici软件对该器件的直流与交流特性,以及输入输出特性进行了模拟与分析.模拟结果表明,相对于体Si CMOS器件,该器件具有更好的电学特性,正确的逻辑功能,且具有更短的延迟时间,同时,采用垂直层叠的结构此类器件还可节省约50%的版图面积,有利于电路的进一步集成. 相似文献
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随着CMOS器件特征尺寸的不断缩小,SiO2作为栅介质材料已不能满足集成电路技术高速发展的需求,利用高k栅介质取代SiO2栅介质成为微电子技术发展的必然.但是,被认为最有希望替代SiO2的HfO2由于结晶温度低等缺点,很难集成于现有的CMOS工艺中,新型Hf基高k栅介质的研究成为当务之急.据报道,在HfO2中引入N、Si、Al和Ta可大大改善其热力学稳定性,由此形成的高k栅介质具有优良的电学特性,基本上满足器件的要求.本文综述了这类先进的Hf基高k栅介质材料的最新研究进展. 相似文献
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InP材料被广泛的应用于光电子领域,但其材料脆、工艺不成熟、成本高,而Si基外延InP材料能良好的改善该技术瓶颈。论文中对不同介质、不同厚度的介质键合制备Si/InP材料进行了分析。其中以SiO2键合制备的Si/InP材料应力转化率最高,且SiO2制备工艺简单、亲水,材料键合强度大,机械特性好,是键合制备Si/InP材料的首选。而且,SiO2键合介质越薄,其应力转化率越高,材料对力学信号就越敏感,制备的Si/InP材料的机械性能越好。 相似文献
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在未来10~15年内有两条主流将引导IC产业的发展:一条是延续摩尔定律、纳米SiCMOS技术,以提高芯片的速度和频率;另一条是超越摩尔定律。后者分成三个支流:双核和多核处理器、纳米SiCMOS技术,以提高芯片性能;在单个封装内集成整个系统,纳米SiCMOS技术,以提高芯片容量和功能;采用纳米技术研发纳米CMOS器件以外的纳米器件,如碳纳米管、共振隧穿器件等,以突破SiCMOS技术为主。 相似文献
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《Solid-State Circuits, IEEE Journal of》2009,44(1):208-216
A 3-dimensional double stacked 4 gigabit multilevel cell NAND flash memory device with shared bitline structure have successfully developed. The device is fabricated by 45 nm floating-gate CMOS and single-crystal Si layer stacking technologies. To support fully compatible device performance and characteristics with conventional planar device, shared bitline architecture including Si layer-dedicated decoder and Si layer-compensated control schemes are also developed. By using the architecture and the design techniques, a memory cell size of 0.0021 mum2/bit per unit feature area which is smallest cell size and 2.5 MB/s program throughput with 2 kB page size which is almost equivalent performance compared to conventional planar device are realized. 相似文献
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The large mismatches among the coefficients of thermal expansion (CTE) of the metal via, insulator liner, and Si substrate of the through-silicon via (TSV) induce thermal stresses within and around the TSV during thermal-cycled fabrication processes. Reduction of thermal stress in the Si substrate is important for minimizing the deviations in the device characteristics. An annular-trench-isolated (ATI) structure was proposed for the TSV to solve the thermal issues, which occur during the three-dimensional (3D) integrated circuit (IC) integration, by stress redistribution. The concept of ATI TSV is based on retaining a Si-ring between the metal core and insulator layer during the fabrication process. We realized the ATI TSV using a via-last fabrication approach, with two deep silicon etching processes (Bosch processes) for the insulator layer and the metal core. Parylene-HT was utilized as the insulator to achieve high uniformity. With a vacuum-assisted filling system, the vias were filled with a solder material. ATI TSVs with diameters of 10 μm and 2-μm-thick Parylene-HT insulation layers were demonstrated. Studies on the thermal stress levels of the ATI TSV were carried out by finite-element method (FEM) simulation, along with comparisons with regular and annular TSVs. We revealed that the ATI TSV shows lower thermal stresses in the Si substrate than the regular and annular TSVs. The ATI TSV is a possible candidate for 3D IC integration with stress-sensitive devices. 相似文献
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SIMOX技术是最具有发展前途的SOI技术之一。在发展薄硅层、深亚微米OMOS/SOI集成电路中,SIMOX技术占有极其重要的地位。本文综述了SIMOX基片的形成、高质量SIMOX基片的制备方法。阐述了薄硅层OMOS/SIMOX器件的工艺特点以及器件的性能特点。本文也就SIMOX技术及GMOS/SIMOX器件的研究现状及发展趋势进行了讨论。 相似文献
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Dixit A. Kottantharayil A. Collaert N. Goodwin M. Jurczak M. De Meyer K. 《Electron Devices, IEEE Transactions on》2005,52(6):1132-1140
The multiple-gate field-effect transistor (FET) is a promising device architecture for the 45-nm CMOS technology node. These nonplanar devices suffer from a high parasitic resistance due to the narrow width of their source/drain (S/D) regions. We analyze the parasitic S/D resistance behavior of the multiple-gate FETs using a novel, S/D geometry-based analytical model, which is validated using three-dimensional device simulations and experimental results. The model predicts limits to parasitic S/D resistance scaling, which reveal that the contact resistance between the S/D silicide and Si-fin dominates the parasitic S/D resistance behavior of multiple-gate FETs. It is shown that the selective epitaxial growth of Si on S/D regions alone may be insufficient to meet the semiconductor roadmap target for parasitic S/D resistance at the 45-nm CMOS technology node. 相似文献
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本文研究了一种应变SiGe沟道的NMOS器件,通过调整硅帽层、SiGe缓冲层,沟道掺杂和Ge组分变化,并采用变能量硼注入形成P阱的方式,成功完成了应变NMOS器件的制作。测试结果表明应变的NMOS器件在低场(Vgs=3.5V, Vds=0.5V)条件下,迁移率极值提升了140%,而PMOS器件性能保持不变。文中对硅基应变增强机理进行了分析。并利用此NMOS器件研制了一款CMOS倒向器,倒向器特性良好, 没有漏电,高低电平转换正常。 相似文献