Linear dynamic self-heating in SOI MOSFETs

A model for small-signal dynamic self-heating is derived for the general case of a two-port device and then specialized to the case of an SOI MOSFET. The model is fitted to measured data for an SOI MOSFET and shown to accurately describe the frequency dependence of the self-heating. For this device, three time constants of 0.25 μs, 17 ns, and 90 ps adequately characterize the thermal response, showing that self-heating effects are active over a very wide frequency range     

Measurement and modeling of self-heating in SOI nMOSFET's

Self-heating in SOI nMOSFET's is measured and modeled. Temperature rises in excess of 100 K are observed for SOI devices under static operating conditions. The measured temperature rise agrees well with the predictions of an analytical model and is a function of the silicon thickness, buried oxide thickness, and channel-metal contact separation. Under dynamic circuit conditions, the channel temperatures are much lower than predicted from the static power dissipation. This work provides the foundation for the extraction of device modeling parameters for dynamic operation (at constant temperature) from static device characterization data (where temperature varies widely). Self-heating does not greatly reduce the electromigration reliability of SOI circuits, but might influence SOI device design, e.g., requiring a thinner buried oxide layer for particular applications and scaled geometries     

High-temperature and self-heating effects in fully depleted SOI MOSFETs

In this paper, the high-temperature and self-heating effects in the fully depleted enhancement lightly doped SOI n-MOSFETs are investigated over a wide range of temperatures from 300 to 600 °K by using the SILVACO¹ TCAD tools. In particular, we have studied their current-voltage characteristics (I_D-V_GS and I_D-V_DS), threshold voltages and propagation delays. Simulation results show that there exists a biasing point where the drain current and the transconductance are temperature independent. Such a point is known as the zero temperature coefficient (ZTC) bias point. The drain current ZTC bias points are identified in both the linear and saturation regions whereas the transconductance ZTC bias point exists only in the saturation region. We have observed that decreasing the film thickness could reduce the threshold voltage sensitivity of the SOI MOSFET with temperature and that the drain current decreases with increasing temperature. We have also noted that due to the self-heating effects, the drain current decreases with increasing drain bias exhibiting a negative conductance and that the self-heating effects reduced at a higher operating temperature. Self-heating effects are more pronounced for higher gate biases and thinner silicon films whereas the bulk device shows negligible self-heating effects.     

DC self-heating effects modelling in SOI and bulk FinFETs

DC thermal effects modelling for nanometric silicon-on-insulator (SOI) and bulk fin-shaped field-effect transistors (FinFETs) is presented. Among other features, the model incorporates self-heating effects (SHEs), velocity saturation and short-channel effects. SHEs are analysed in depth by means of thermal resistances, which are determined through an equivalent thermal circuit, accounting for the degraded thermal conductivity of the ultrathin films within the device. Once the thermal resistance for single-fin devices has been validated for different gate lengths and biases, comparing the modelled output characteristics and device temperatures with numerical simulations obtained using Sentaurus Device, the thermal model is extended by circuital analysis to multi-fin devices with multiple fingers.     

Unified physical I-V model including self-heating effect for fullydepleted SOI/MOSFET's

A physically based analytical I-V model that includes self-heating effect (SHE) is presented for fully depleted SOI/MOSFET's. The incorporation of SHE is done self-consistently in a fully closed form, making the model very suitable for use in circuit simulators. The model also accounts for the drain induced conductivity enhancement (DICE) and drain induced barrier lowering (DIBL), channel length modulation (CLM), as well as parasitic series resistances (PSR). Another advantage is the unified form of the model that allows us to describe the subthreshold, the near-threshold and the above-threshold regimes of operation in one continuous expression. A continuous transition of current and conductance from the linear to the saturation regimes is also assured. The model shows good agreement with measured data for a wide range of channel lengths (down to 0.28 μm) and film thicknesses (94 nm-162 nm)     

SPICE model and parameters for fully-depleted SOI MOSFET'sincluding self-heating

A simple methodology to accurately extract constant temperature model parameters from static measurements of fully-depleted SOI MOSFET current-voltage characteristics is demonstrated. Self-heating is included in an existing physically-based, short-channel bulk MOSFET model, PCIM, by allowing the temperature to change linearly with power dissipation at each bias point. Only a simple modification of the channel bulk charge in PCIM is necessary to adapt it for SOI. The temperature dependence of the physical parameters (mobility, flatband voltage, and saturation velocity) are also fitted and included in the model. Excellent fit to experimental fully-depleted SOI data is shown over a large range of bias conditions and channel lengths. Once the static SOI data is fitted, the constant temperature model parameters appropriate for circuit simulation are easily extracted     

Time-resolved measurements of self-heating in SOI and strained-silicon MOSFETs using photon emission microscopy

A simple noninvasive optical technique for characterization of self-heating dynamics in advanced metal-oxide-semiconductor field-effect transistors is reported for the first time. The technique uses time-resolved photon emission microscopy to measure the temperature-dependent luminescence of off-state leakage current. It measures the temperature of the device channel, independent of surrounding materials or interconnects. The technique has been used to measure, for the first time, self-heating dynamics in silicon-on-insulator and strained-silicon n-field-effect transistors.     

Spatial temperature profiles due to nonuniform self-heating inLDMOS's in thin SOI

Temperature profiles resulting from self-heating in SOI-LDMOS devices with uniformly doped and linearly graded drift regions were measured using a resistance thermometry technique. Two-dimensional electrothermal device simulations were performed and the results agreed with the experiments. Because of the different power dissipation profiles, RESURF devices with a uniformly doped drift region assume a fairly uniform temperature distribution while devices with a linearly graded drift region have a much higher temperature rise near the source than the drain. This local hot spot near the source raises reliability issues in device design     

Study of thermal effects and self-heating phenomena in planar power SOI MOS transistors

Heat removal problems, thermal effects, and self-heating phenomena occurring during operation of planar power SOI MOS transistors are considered. Using device-technological simulating methods, the transistor characteristics and safe operation range were studied. It was shown that limitations of the safe operation range are mostly associated with structure self-heating rather than with the parasitic bipolar transistor.     

Wafer level measurements and numerical analysis of self-heating phenomena in nano-scale SOI MOSFETs

We present an experimental technique and a Finite Element thermal simulation for the determination of the temperature elevation in Silicon on Insulator (SOI) MOSFETs due to self-heating. We evaluate the temperature elevation in two steps, as we calibrate the gate resistance over temperature with the transistor at off state at a first stage, and then we deduce the temperature elevation through gate resistance measurements. We simulate the self-heating phenomena in a Finite Elements Method (FEM) environment, both with 2D and 3D models. In order to set up the simulations, we weight the effects of several parameters, such as thermal material properties, the modeling of heat generation and a careful setting of boundary conditions. We present typical temperature fields and local heat fluxes, thus giving concrete indications for solving thermal reliability issues. Simulation results show temperature elevations up to approximately 120 K in the hot spot, 70 K in the gate and 7 K in the Back End of Line (BEoL). The 3D model gives results that are satisfying over the whole set of MOSFETs we consider in this work. Temperature elevation strongly depends on physical dimensions, where transistors endowed with shorter gates suffer from more severe self-heating. We propose a simplified model based on geometrical parameters that predict maximum and gate temperatures, obtaining satisfying results. Since correlation with measurements confirms the correctness of our model, we believe that our simulations could be a useful tool to determine accurate reliability rules and in a context of thermal aware design.     

Measurement of I-V curves of silicon-on-insulator (SOI) MOSFET'swithout self-heating

A new method for measuring the output (I_D-V_D) characteristics of SOI MOSFET's without self-heating is described. The method uses short pulses with a low repetition rate, and a reverse transient loadline construction. The technique is demonstrated by measuring 0.25 μm bulk and SOI MOSFET's with 5-nm gate oxide. Application of the method to the extraction of device temperature as a function of DC power is also illustrated     

Study of novel techniques for reducing self-heating effects in SOI power LDMOS

Self-heating effects in silicon-on-insulator (SOI) power devices have become a serious problem when the active silicon layer thickness is reduced and buried oxide thickness is increased. Hence, if the temperature of the active region rises, the device electrical characteristics can be seriously modified in steady state and transient modes. In order to alleviate the self heating, two novel techniques which lead to a better heat flow from active silicon layer to silicon substrate through the buried oxide layer in SOI power devices are proposed. No significant changes on device electrical characteristics are expected with the inclusion of the novel techniques. The electro-thermal performance of lateral power devices including the proposed techniques is also presented.     

Physical modeling of temperature dependences of SOI CMOS devicesand circuits including self-heating

To simulate and examine temperature and self-heating effects in Silicon-On-Insulator (SOI) devices and circuits, a physical temperature-dependence model is implemented into the SOISPICE fully depleted (FD) and nonfully depleted (NFD) SOI MOSFET models. Due to the physical nature of the device models, the temperature-dependence modeling, which enables a device self-heating option as well, is straightforward and requires no new parameters. The modeling is verified by DC and transient measurements of scaled test devices, and in the process physical insight on floating-body effects in temperature is attained. The utility of the modeling is exemplified with a study of the temperature and self-heating effects in an SOI CMOS NAND ring oscillator. SOISPICE transient simulations of the circuit, with floating and tied bodies, reveal how speed and power depend on ambient temperature, and they predict no significant dynamic self-heating, irrespective of the ambient temperature     

Use of noise thermometry to study the effects of self-heating insubmicrometer SOI MOSFETs

The authors report the direct measurement of the silicon island temperature in both long and submicrometer thin-film silicon-on-insulator (SOI) MOSFETs as a function of bias conditions using noise thermometry. They show that the device island temperature increases with drain voltage and that this results in a reduction of drain current. Using standard models of the drain current and velocity/field expression, they show that a thermally induced fall in mobility quantitatively accounts for the loss in drain current drive observed     

An analytical fully-depleted SOI MOSFET model considering theeffects of self-heating and source/drain resistance

In this paper, we present a new and analytical drain current model for submicrometer SOI MOSFET's applicable for circuit simulation. The model was developed by using a two-dimensional (2-D) Poisson equation, and considering the source/drain resistance and the self-heating effect. Using the present model, we can clearly see that the reduction of drain current with the parasitic series resistance and self-heating effect for typical SOI devices. We also can evaluate the impact of series resistance and self-heating effects. The accuracy of the presented model has been verified with the experimental data of SOI MOS devices with various geometries     

Measurement of the effect of self-heating in strained-siliconMOSFETs

The self-heating of strained-silicon MOSFETs is demonstrated experimentally. Output characteristics measured by a pulse technique, in which self-heating is absent, show as much as 15% greater drain current (for 15% Ge content) than the corresponding static measurements. Comparison of the current measured this way with the static measurements allows an estimate of the channel temperature during the static operation. The temperature rise is compared to a simple estimate of the thermal resistance of the FET     

Deep submicrometer SOI MOSFET drain current model including seriesresistance, self-heating and velocity overshoot effects

We have developed a new analytical ultrashort channel SOI MOSFET for circuit simulation where the effects of series resistance, self-heating and velocity overshoot are included. We have reproduced experimental measurements validating our model. Its simplicity allowed us to study the contribution of each effect separately in an easy way     

Reduction of self-heating effect on SOIM devices

The silicon-on-insulator (SOI) power devices have an inherent self-heating effect, which limits their operation at high current levels. This is a consequence of the very low thermal conductivity of the thick buried oxide layer. A novel solution to reduce the self-heating effect is proposed in this paper, based on silicon-over-insulator-multilayer (SOIM) emerging technology. A significant reduction of the insulator layer thermal resistance is achieved while keeping constant the electrical behaviour of integrated power devices in comparison to the conventional SOI counterparts. The effectiveness of the proposed solution has been corroborated with numerical simulations. Moreover, no additional steps in fabrication processes are required with regard to the conventional SOI technology.     

Noise measurements in ion implanted mosfets

An example is given for 1/f noise in MOSFETs caused by a non-uniform channel that is noisiest at the drain. The device is an ion implanted unit and therefore the noise shows generation-recombination bumps superimposed on a 1/f noise background. A similar device shows a very shapp peak in the noise at saturation, followed by a new peak beyond saturation. The noise if the 1/f fype with some indication of generation-recombination noise bumps at the highest drain voltage. Non-ion implanted devices do not show these effects.