Advances in bipolar VLSI

Bipolar IC processes are reviewed, and the impact of BiCMOS technology on bipolar VLSI is discussed. The discussion covers standard emitter-coupled-logic (ECL) circuit configuration, on-chip line driving, output circuitry, series gating, ECL versus CML (current-mode logic), differential logic, noise margins, interconnect capacitance, bipolar VLSI transistor design and scaling, and processes for ECL VLSI     

Advancements in bipolar VLSI circuits and technologies

Due to their inherent speed advantage over FETs, bipolar circuits are widely used for high-performance masterslice and custom logic and for high-speed static memory arrays. For logic, traditional circuits such as transistor-transistor logic and emitter-coupled logic are still mostly used, but new circuit technologies such as integrated injection logic or merged transistor logic and Schottky transistor logic or integrated Schottky logic have been devised to manage the VLSI technology constraints. For high-speed memory applications such as caches, local stores, or registers, conventional memory cells are increasingly being replaced by more advanced memory devices allowing higher bit densities and lower power dissipation. Significant progress can be expected through technology extensions such as dielectric isolation, multilayer metallization, and polysilicon techniques, in addition to shrinking the devices to 1 /spl mu/m dimensions or below.     

New symmetrical buffer design for VLSI applications

Novel fast buffers by the transient part circuit technique are described in this paper. The proposed circuits are fully symmetrical in their structure, therefore the design is straightforward and the well balanced speed can be easily obtained. As compared with prior work, the delay ratio of this work is over 300% and 10% balance improvement, respectively. While based on a design criterion of the same area the proposed buffer circuit shows 27% and 76% average speed enhancements on propagation delays with only 7.3% average increase in its power consumption.     

Physical timing modeling for bipolar VLSI

An approach for the analytical timing modeling of bipolar VLSI circuits that is based on average branch current analysis and the parametric correction scheme is presented. The combination of these techniques permits complex delay-sensitive effects of bipolar digital circuits to be incorporated in the derivation of the bipolar delay models. The delay functions of two basic bipolar subcircuit configurations (the series-gated structure and the emitter follower) are derived using the proposed techniques. It is shown that accurate timing information for the high-speed bipolar digital circuit, such as ECL, CML, and BiCMOS, can be obtained by repeated processing of these subcircuit delay functions. The delay estimates obtained with these timing models have been shown to be accurate typically within 10% of SPICE estimates. Applications include switch-level timing simulation, timing analysis and verification cell optimization, and technology mapping     

A fully implanted NMOS, CMOS, bipolar technology for VLSI of analog-digital systems

A fully ion-implanted process allows high-density integration of NMOS, CMOS, and bipolar transistors for VLSI of analog-digital systems. Supply voltage can be 20 V. Thresholds are ± 1.5 V for p- and n-channel enhancement transistors, respectively. Standard deviation per wafer is 15 mV for the NMOS threshold, while the NMOS gain constant is 30 µAV^-2. The bipolar transistors have a low-resistance base contact. Current gain βFcan be set independently. Forbeta_{F} = 90, the Early voltage isV_{A} = 110V. No epi layer, isolation diffusions, or channel stoppers are required. The mask count is 6 for structure definition plus 2 for the masking of implants. The process can be scaled along the learning curve of digital MOS VLSI.     

A fully implanted NMOS, CMOS, bipolar technology for VLSI of analog-digital systems

A fully ion-implanted process allows high-density integration of NMOS, CMOS, and bipolar transistors for VLSI of analog-digital systems. Supply voltage can be 20 V. Thresholds are /spl plusmn/1.5 V for p- and n-channel enhancement transistors, respectively. Standard deviation per wafer is 15 mV for the NMOS threshold, while the NMOS gain constant is 30 /spl mu/AV/SUP -2/. The bipolar transistors have a low-resistance base contact. Current gain can be set independently. For current gain=90, the Early voltage if V/SUB A/=110 V. No epi layer, isolation diffusions, or channel stoppers are required. The mask count is 6 for structure definition plus 2 for the masking of implants. The process can be scaled along the learning curve of digital MOS VLSI.     

A simplified fully implanted bipolar VLSI technology

An implanted n-p-n bipolar transistor structure named Isoplanar Z II (currently, being marketed as FAST-Z technology) with reduced process and masking steps is described. The simplification is achieved by employing self-aligned-transistor (SAT) masking, ion-implantation techniques to provide impurity doping, and using one common annealing cycle for collector, base, and emitter implantations. The device structure reduces design constraints through use of self-aligned field implantation and SAT mask for contact window definition. Submicrometer emitter widths are obtained by step and repeat optical photolithographic tool and two-dimensional effect on current gain due to sidewall injection is also studied. This technology is used to demonstrate 13-15 ns TAA, 4K static RAM and minimum delay of 250 ps per gate, gate array products.     

Low-output-impedance class AB bipolar voltage buffer

A new ±1.5 V class AB bipolar voltage buffer that can drive low load impedance is presented. A current compensation technique is used for achieving a low output impedance, resulting in a large unitary gain bandwidth and low distortion. Simulation results are included demonstrating the circuit performance     

OXIL, a versatile bipolar VLSI technology

A bipolar VLSI technology, for Oxide Isolated Logic (OXIL) circuits has been developed which combines high-frequency conventional down-transistors with inverted up-transistors which are fabricated in a common process on the same chip site. The up-transistor is especially designed to optimize I²L circuits for high packing density, speed, and performance. High-pressure-steam oxide isolation and an up-diffused active base are combined to fabricate the up-transistor withf_{t} > 500MHz andbeta = 100, which allows I²L delays down to 3 ns atFO = 1and 7 ns atFO = 6. The down-transistor is an oxide-isolated implanted-base transistor with an As emitter. It exhibits gains of 100-150 atf_{t} = 2GHz and supports subnanosecond CML, high-current buffer circuitry, and linear interfacing.     

Signal resynchronization in VLSI systems

A simple extension to the standard nonoverlapping two phase clocking strategy, allowing a considerable clock skew between different isochronic regions is suggested. It is shown how this strategy can be further extended to other clocking strategies and to clock skews of more than half a clock period.     

Improved bipolar transistor performance in a VLSI CMOS process

Bipolar n-p-n transistors have been successfully fabricated on a high-performance n-well VLSI CMOS process incorporating an additional mask and implant step. A double active-base implant was utilized to control the base surface concentration and the transistor characteristics separately. High forward common-emitter current gain and collector-emitter breakdown voltage can be achieved by this process. n-p-n transistors with βf= 100, BVCE0= 9.0 V, and BVCB0= 23 V can be easily fabricated on this scaled VLSI CMOS process.     

VLSI scaling methods and low power CMOS buffer circuit

Device scaling is an important part of the very large scale integration(VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit’s performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate(LPTG) approach and tested it on complementary metal oxide semiconductor(CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model(BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability.     

Self-aligned bipolar transistors for high-performance and low-power-delay VLSI

An n-p-n bipolar transistor structure with the emitter region self-aligned to the polysilicon base contact is described. The self-alignment results in an emitter-to-base contact separation less than 0.4 µm and a collector-to-emitter area ratio about 3:1 for a two-sided base contact. This ratio can be less than 2:1 for a base contacted only on one side. The vertical doping profile can be optimized independently for high-performance and/or high-density and low-power-delay circuit applications. The technology, using recessed oxide isolation, was evaluated using 13-stage nonthreshold logic (NTL) and 11-stage merged-transition logic (MTL) ring-oscillator circuits designed with 2.5 µm design rules. For transistors with 200-nm emitter junction depth the common-emitter current gain for polysilicon emitter contact is typically 2-4 times that for Pd2Si emitter contact. There is no observable circuit performance degradation attributable to the polysilicon emitter contact. Typical observed per-stage delays were 190 ps at 1.3 mW and 120 ps at 2.3 mW for the NTL (FI = FO = 1) circuits and 1.3 ns at 0.15 mA for the MTL (FO = 4) circuits.     

Fault tolerant VLSI systems

A wide variety of fault tolerance techniques for VLSI technology are examined. Device-, gate-, and function-levels fault models are described. The basic methods available to the designer of fault tolerance measures are introduced by surveying redundancy techniques. Techniques of fault detection that use space, time, and information redundancies, algorithm-based fault tolerance, in VLSI components, large-scale processor-level implementations of fault detection, fault tolerance in automated VLSI production systems are discussed. Reconfiguration of the system and recovery of system operation are described. Issues relating to the reconfiguration after discovery of a fault in fabrication or in operation are discussed. Recovery capabilities of a VLSI microprocessor are reviewed     

MOS and bipolar VLSI technologies using electron-beam lithography

Key issues for micrometer and submicrometer MOS and bipolar device fabrication are discussed, including lithography, device and circuit scaling limitations, and process considerations. Lithographic requirements are presented in terms of an overall technology-machine, resist and pattern transfer methods-and an electron-beam alice writing technology is described which satisfies those needs. Viable micrometer and submicrometer MOS and bipolar process technologies are demonstrated by scaling complex LSI circuits to VLSI density using electron lithography. For the MOS case, scaling of static memories is discussed in detail, including fabrication of a 4K SRAM with 1.5-µm minimum feature sizes, 12-15-ns access times, and a chip size of only 6K mil². A discussion of bipolar device and process scaling issues is highlighted by the successful fabrication of a scaled 16-bit integrated injection logic (I²L) microprocessor with 1.25-µm minimum feature sizes and a clock frequency of 10 MHz with a chip current of only 250 mA.     

Self-aligned transistors with polysilicon emitters for bipolar VLSI

A new bipolar process technology for fabricating self-aligned transistors with polysilicon contacted emitters is described. The extrinsic base regions of the transistor are self-aligned to the emitter contact by exploiting the effects of concentration-dependent oxidation to selectively oxidize the polysilicon. The shallow emitter is fabricated with a thin oxide layer at the polysilicon-silicon interface, thereby enhancing the emitter efficiency and thus the current gain of the device. It is demonstrated that this gain enhancement can be traded for a considerable increase in active base doping, with a resulting decrease in base resistance and potential improvement in switching performance. Under certain circumstances, non-ideal electrical characteristics can be obtained from the self-aligned transistor which are caused by lateral spread of the extrinsic base region beneath the sidewall oxide of the polysilicon emitter contact. This leads to the formation of p⁺-n⁺junction at the periphery of the emitter and hence to tunneling of carriers across this region. It is shown that the same tunneling mechanism also limits the extent to which the active base doping can be increased. In order to avoid the formation of the peripheral p⁺-n⁺junction, a polysilicon base contact is employed which allows a self-aligned extrinsic base region to be fabricated with negligible lateral movement.     

A new high temperature stable bipolar VLSI metallization

High performance bipolar analog/digital circuits require metallization capable of with-standing several hour anneals in the temperature range of 400–500° C without causing any device degradation. A new VSi₂/Ti: W/Pd/Rh/Au metallization scheme for use in bipolar circuits is described. This metallization scheme (which evolved from Pd₂Si/Ti:W/ Pd/Au metallization) offers high electrical conductivity, high electromigration and corrosion resistances and is capable of withstanding long anneals at temperatures up to 500° C without degradation of minority carrier devices. The metallization integrity and majority carrier devices are not affected up to 600° C.     

CAD systems for VLSI in Japan

With the advent of the VLSI era, computer-aided design (CAD) is increasing its importance, and much effort is now being expended on CAD by many IC manufacturers and laboratories in Japan. This paper reviews the historical aspect of the CAD systems developed in this field, and describes the current status of VLSI CAD systems and technologies, from device to system levels, in Japan. The CAD development activities for IC's were initiated in the late 1960's. At present, VLSI CAD systems and related CAD technologies in Japan seem to be in the adolescent stage-partly capable of practical use and partly still in the immature state.     

Performance-directed synthesis of VLSI systems

The two tasks involved in the design of VLSI systems, synthesizing the circuit and then analyzing it to verify the desired behavior and performance, are becoming intertwined, and performance constraints are being used to drive synthesis. This approach requires the ability to explore efficiently many design options and to find global optima over the several consistently aligned representation levels simultaneously. General requirements for performance-directed synthesis are characterized, followed by an overview of algorithms used for performance optimizations both within and between the several levels of representation. The need for techniques for simultaneous constraint optimization and a perspicuous characterization of the total design space is highlighted     

Closed-form physical model for VLSI bipolar devices consideringenergy transport

A closed-form physical model is reported for VLSI bipolar devices considering energy transport. Based on the model, for a base width of 810 Å, the bipolar device, biased at V_cb=2 V, has a peak electron temperature of over 700 K, which results in a 5% reduction in the collector current