薄膜双栅MOSFET体反型现象的研究

通过对QM模型的介绍，说明了薄膜双栅MOSFET体反型现象是量子效应的结果，并对QM模型中提出的反型层质心概念进行了剖析，阐述了其重要的物理意义和应用价值。利用反型层质心概念，提出了一组形式非常简单，且与体硅单沟道MOSFET表达式十分相似的薄膜双栅MOSFET亚阈值区反型层载流子浓度和亚阈值电流的表达式。与MEDICI模拟结果的比较证明了其精确性。应用反型层质心及所提出的亚阈值区模型，对薄膜双栅MOSFET体反型现象进行了深入的分析，提出了一个能够较好体现体反型作用的硅膜厚度范围。     

Comparison of Uniaxial Wafer Bending and Contact-Etch-Stop-Liner Stress Induced Performance Enhancement on Double-Gate FinFETs

Longitudinal piezoresistance (pi) coefficients for n- and p-type double-gate (DG) FinFETs with sidewall channels along (110) surface and (110) channel direction are measured via wafer-bending experiments (51.4 and -37 X 10 ^-11 Pa^-1 for n- and p-FinFETs, respectively) and are found to differ from bulk Si (110) (31.2 and -71.8 X 10 ^-11 Pa^-1 for n- and p-Si, respectively). Compressive and tensile contact-etch-stop liners (CESLs) are fabricated on DG FinFETs and are found to induce higher channel stress than in planar MOSFETs, with 30% enhancement in the saturation current for the shortest channel-length devices in both n- and p-MOSFETs, whereas the long devices show little or no enhancement. The channel-length dependence of the enhancement suggests that stress coupling into the FinFET channels from the CESL occurs via the fin extensions and not through the gate.     

Analysis of Geometry-Dependent Parasitics in Multifin Double-Gate FinFETs

This paper analyzes the geometry-dependent parasitic components in multifin double-gate fin field-effect transistors (FinFETs). Parasitic fringing capacitance and overlap capacitance are physically modeled as functions of gate geometry parameters using a conformal mapping method. Also, a physical gate resistance model is presented, combined with parasitic capacitive couplings between source/drain fins and gates. The effects of geometrical parameters on FinFET design under different device configurations are thoroughly studied     

Modeling and Analysis of Parasitic Resistance in Double-Gate FinFETs

A comprehensive model is presented to analyze the three-dimensional (3-D) source-drain (S/D) resistance of undoped double-gated FinFETs of wide and narrow S/D width. The model incorporates the contribution of spreading, sheet, and contact resistances. The spreading resistance is modeled using a standard two-dimensional (2-D) model generalized to 3-D. The contact resistance is modeled by generalizing the one-dimensional (1-D) transmission line model to 2-D and 3-D with appropriate boundary conditions. The model is compared with the S/D resistance determined from 3-D device simulations and experimental data. We show excellent agreement between our model, the simulations, and experimental data.     

Experimental Evaluation of Circuit-Based Modeling of the NBTI Effects in Double-Gate FinFETs

In this work, an example of practical implementation of the auxiliary sub-circuit (ASC) for modeling of the NBTI effects in DG FinFETs is described. A good agreement between the simulated and measured electrical characteristics of p-type DG FinFETs fabricated in SOI technology has been obtained using the industry-standard BSIM-CMG model with ASC. The oxide and interface trap densities are extracted in Spice simulations by tuning the ASC trapped charge parameters to fit the NBTI experimental data. The increase of oxide and interface trapped charge in p-type DG FinFET device is found to follow the logarithmic dependence with NBTI stress time.     

The Potential of FinFETs for Analog and RF Circuit Applications

CMOS downscaling in the nanoscale era will necessitate drastic changes to the planar bulk CMOS transistor to keep pace with the required speed increase while at the same time maintaining acceptable performance in terms of leakage, variability and analog parameters such as gain, noise and linearity. For the gate electrode and the gate dielectric, which classically use polysilicon and with some amount of nitridation, new materials might be needed. Also, a new transistor architecture might be required that deviates from the planar structure. Thanks to their inherent suppression of short-channel effects, reduced drain-induced barrier lowering and good scalability, multi-gate devices such as fin-shaped field-effect transistors (FinFETs) are considered as possible candidates for device scaling at the end of International Technology Roadmap for Semiconductors. As such, they form a first step between a planar architecture and a silicon nanowire. In this paper, we demonstrate with functional prototypes of analog and RF circuits that the combination of a new gate stack with a FinFET transistor architecture outperforms comparable circuit realizations in planar bulk CMOS for low to moderate speed. Further, the FinFETs exhibit less leakage and show less intra-die variability than their planar bulk counterpart. In the microwave and millimeter-wave frequency region, planar bulk CMOS is still superior. The main challenge for FinFET performance in the coming years is the improvement of the maximum cutoff frequency, which is nowadays limited to 100 GHz.     

Design Optimization and Performance Projections of Double-Gate FinFETs With Gate–Source/Drain Underlap for SRAM Application

Physical device/circuit simulations are used to explore 6T-SRAM cell design and scaling using double-gate (DG) FinFETs with optimized gate-source/drain (G-S/D) underlap. The underlap is designed for the control of threshold voltage (V_t) in the nanoscale FinFET with undoped ultrathin body (UTB). DG FinFETs with underlap are first characterized in terms of for various S/D-extension lengths (L_ext), lateral doping-density straggles (sigma_L), and fin-UTB thicknesses (w_Si). The relation between and read-static noise margin (SNM) is established to define an optimal SRAM cell, for the Semiconductor Industry Association's International Technology Roadmap for Semiconductors (ITRS) HP45 node with L_g=18 nm, with large SNM as well as large write-0 margin and good immunity to process-induced variations of L_ext, sigma_L, w_Si, and L_g. Then, a scalability study of the DG FinFET-based SRAM cell is done, showing a continual significant benefit of the optimally designed doable underlaps to the end of the ITRS. In addition to the SRAM application, the novel idea of FinFET V_t control via underlap design is stressed, and its application to high-performance CMOS is discussed.     

Extraction of Substrate Resistance in Bulk FinFETs Through RF Modeling

A new method to extract substrate resistance (R_sub) for small-sized nano-scale metal oxide semiconductor field effect transistors (MOSFETs) including bulk FinFETs is proposed and compared with conventional method. The R_sub's extracted from small-size MOSFETs by using the proposed method are shown to have frequency independent characteristics, unlike those from the conventional method. Proposed equivalent circuit explains well the R_sub behavior with body width. The proposed model showed very good agreement (error in Y₂₂~3%) with three-dimensional device simulation     

Inversion charge modeling in n-type and p-type Double-Gate MOSFETs including quantum effects: The role of crystallographic orientation

We have developed an advanced inversion charge model for both n-type and p-type symmetrical Double-Gate MOSFETs where quantum mechanical effects (QMEs) have been included. By doing so, the role of different crystallographic orientations was successfully taken into account. Self-consistent Poisson and Schrödinger simulators were used to check the accuracy of the model presented. As a starting point, a classical inversion charge centroid model was considered. Afterwards, an inversion charge model was developed including QMEs by means of a corrected oxide capacitance. The validity of the model was checked for the three common wafer orientations (1 0 0), (1 1 0) and (1 1 1) and for devices with different silicon layer (t_Si) and oxide (t_ox) thicknesses. As it will be shown, the model reproduces correctly the simulation data both in the subthreshold and in the strong inversion operation regime.     

Impact of High-k Gate Dielectrics on the Device and Circuit Performance of Nanoscale FinFETs

The impact of high-k gate dielectrics on device short-channel and circuit performance of fin field-effect transistors is studied over a wide range of dielectric permittivities k. It is observed that there is a decrease in the parasitic outer fringe capacitance C_of in addition to an increase in the internal fringe capacitance C_if with high-k dielectrics, which degrades the short-channel effects significantly. It is shown that fin width scaling is the most suitable approach to recover the degradation in the device performance due to high-k integration. Furthermore, from the circuit perspective, for the 32-nm technology generation, the presence of an optimum k for a given target subthreshold leakage current has been identified by various possible approaches such as fin width scaling, fin-doping adjustment, and gate work function engineering     

RF Performance of T-DAB Receivers

In every wireless system, the weakest link determines the performance of the network. In this paper the Radio Frequency (RF) performance of both band III and L-band Terrestrial Digital Audio Broadcasting (T-DAB) consumer receivers are discussed. The receivers have been tested based on the EN 50248 standard. The test results show that the average consumer receiver for band III meets the requirements set by EN 50248, except for the non-adjacent interferer experiments. In this experiment, the average consumer receiver performs up to 10 dB worse than required. In addition, the experiments reveal that there is a large difference in performance between consumer receivers. Besides band III, also L-band consumer receivers have been evaluated. The results of the L-band experiments show that the consumer receivers are not capable of decoding a DAB signal with a COST207 rural area channel model in case of T-DAB mode IV. Network operators should for this reason use mode II for the L-band and should expect a larger influence of non-adjacent interference on receiver performance in band III than anticipated based on EN 50248.     

不稳定因子对射频振荡器性能影响的研究

为解决射频振荡器低复杂度的问题,减少集总变容器件的使用,研究了不稳定因子对射频振荡器性能的影响,提出了一种新型低复杂度射频振荡器的设计方法,通过调整不稳定因子,实现频率可调。分析了反馈电感与不稳定区位置的相互关系,给出了不稳定区域匹配点选择、终端网络阻抗与振荡器性能的变化规律。仿真结果表明:当终端网络电抗变化范围为－36～36 Ω时,振荡频率变化范围为1.8～1.994 GHz(10.2%);当终端网络电阻变化范围为6～35 Ω时,振荡频率变化范围为1.8～2.222 GHz(21%)。该研究为射频振荡器的设计提供了参考。     

DTMB接收终端射频性能测试问题解析

针对目前DTMB接收终端测试中射频解调和信道解码性能部分的相关测试技术进行阐述,结合测试经验和仪器使用知识,对实际测试过程中经常遇到的关键问题和难点进行分析解释,并提出相应的解决方法,为DTMB接收终端的接收解调模块的研发和测试提供参考.     

雷达发射机射频性能分析

现代雷达发射机多半采用O型管放大链来放大固定载频信号，射频信号通过放大链会产生频率域或时间域失真。频率域失真是由放大链本身的非线性所引起的，而时间域失真主要是由幅度调制和相位调制引起的。     

Performance trends of Si-based RF transistors

This paper discusses several aspects of the performance of advanced Si-based RF transistors. The RF performance of SiGe HBTs and Si RF MOSFETs is reviewed and compared to that of III–V RF transistors. The speed – breakdown voltage tradeoff which is typical for bipolar transistors is discussed with special emphasis on SiGe HBTs. On the field-effect transistor side, we review the performance of state-of-the-art Si RF MOSFETs and show that these devices are highly competitive in terms of speed and cutoff frequency.     

雷达发射机射频性能分析

现代雷达发射机多半采用O型管放大链来放大固定载频信号,射频信号通过放大链会产生频率域或时间域失真。频率域失真是由放大链本身的非线性所引起的,而时间域失真主要是由幅度调制和相位调制引起的。     

可满足高性能数字接收机动态性能要求的ADC和射频器件

针对数字式接收机对其所采用器件的动态性能要求，给出了一个欠采样接收机的结构图。乒时给出了满足该高性能数字接收机动态性能要求的新型器件及主要性能参数。     

射频功率模块的热性能分析

随着高密度电子组装技术的不断发展,电子设备的体积越来越小,而功率却越来越大。热功耗的显著增加将对半导体芯片的正常工作产生很大的影响。对装有功率放大器芯片的射频模块热性能进行了分析,提出了有效热控制的解决方法,为射频功率模块的可靠、稳定工作提供了保障。     

SiC/GaN IMPATT二极管的交流性能研究

利用p型宽带隙材料SiC替代p型GaN,制作了一种p-SiC/n-GaN异质结双漂移(DDR)IMPATT二极管.对器件的交流大信号输出特性进行数值模拟仿真.结果表明,相比传统GaN单漂移(SDR)IMAPTT二极管,p-SiC/n-GaN新结构DDR器件的击穿电压、最佳负电导、交流功率密度和直流-交流转换效率都获得了...