Chirp reduction of directly modulated semiconductor lasers at 10Gb/s by strong CW light injection

The influence of strong light injection on the reduction of the dynamical linewidth broadening of directly current-modulated semiconductor lasers at high bit rates is theoretically investigated and experimentally verified for 10 Gb/s NRZ pseudorandom modulation with a large current swing of 40 mA pp. Significant chirp reduction and single-mode operation are observed for bulk DFB, quantum well DFB lasers at 10 Gb/s and a weakly coupled bulk DFB laser at 8 Gb/s, so that an improvement of the transmission performance using standard monomode fibers in the 1.55 μm low-loss wavelength region can be achieved for all these laser types, where dispersion otherwise causes severe penalties for long-haul transmission. The properties of injection-locked bulk DFB and quantum well DFB lasers with respect to high bit rate modulation have been systematically studied by the use of the rate equation formalism. A dynamically stable locking range of more than 30 GHz under modulation has been found for both laser types with injection ratios higher than 0.5     

2.5Gb/s和3.125Gb/s速率级0.35μmCMOS限幅放大器

采用了TSMC0.35μm CMOS工艺实现了可用于SONET/SDH2.5Gb/s和3.125Gb/s速率级光纤通信系统的限幅放大器。通过在芯片测试其最小输入动态范围可达8mVp—p，单端输出摆幅为400mVp-p，功耗250mW，含信号丢失检测功能，可以满足商用化光纤通信系统的使用标准。     

2.5Gb/s混合集成光发射机

介绍了适用于光纤通信系统且具有完全自主知识产权的混合集成光发射机的研制.该发射机采用薄膜电路和激光焊接耦合技术将高速集成电路和光电子器件进行混合集成,其中高速集成电路是采用0.35μm硅CMOS工艺实现的单片4∶1复接器加激光驱动器芯片,光电子器件是采用湿法腐蚀、聚合物平坦和lift-off等技术实现的激光器芯片,最终混合集成模块采用蝶形管壳进行封装,体积小、性能优良.该发射机工作速率为2.5Gb/s,波长为1550nm,输出光功率为5.5dBm,消光比为9.4dB.     

2.5Gb/s Reed-Solomon译码器的VLSI优化实现

研究了基于改进的欧氏算法的高速Reed-Solomon(255，239)译码器的VLSI优化实现。采用管线方式减少关键方程获取模块中的有限域乘法器数量，并对乘法器结构进行优化。同时提出了基于全局优化的公共项提取算法，并用该算法对伴随式计算模块进行优化。结果表明，与直接实现方法相比，关键方程模块的面积节省了约30％，用于伴随式计算的各单元电路面积也普遍减少20％以上。该Reed-Solomon译码器已用Synopsys综合工具综合并用TSMC 0．25μm CMOS工艺实现，其端口处理速率可达2．5Gb/s。     

2.5—10Gb/s光发射机驱动电路HEMT IC中器件模型参数

对高速调制器驱动电路 HEMT IC中器件参数进行了研究 ,着重讨论了 HEMT器件直流参数、交流参数对外调制驱动电路特性的影响 ,给出了满足电路性能要求的器件参数范围 ;对 2 .5— 10 Gb/ s PHEMT IC光驱动电路进行了计算机仿真 ,眼图模拟结果表明满足 2 .5— 10 Gb/ s高速光纤通信系统需要     

2.5-10Gb/s光发射机驱动电路HEMT IC中器件模型参数

对高速调制器驱动电路HEMTIC中器件参数进行了研究,着重讨论了HEMT器件直流参数、交流参数对外调制驱动电路特性的影响,给出了满足电路性能要求的器件参数范围;对2.5-10Gb/sPHEMTIC光驱动电路进行了计算机仿真,眼图模拟结果表明满足2.5-10Gb/s高速光纤通信系统需要.     

2.5 Gb/s laser-driver GaAS IC

A laser-diode driver GaAs IC incorporating an optional NRZ/RZ (non-return-to-zero/return-to-zero) conversion facility, having ECL (emitter-coupled logic) and SCFL (source-coupled FET logic)-compatible inputs and providing a 0-60-mA adjustable output current into a 50-Ω/5-V termination at bit rates up to 2 Gb/s NRZ and maintaining a clear eye opening of 50 mA at 2.5 Gb/s NRZ bit rate has been designed, using a commercial 1-μm gate-length (F_τ=12 GHz) GaAs MESFET foundry service. The high maximum output current is obtained by implementing the output driver as a cascode differential amplifier. The logic circuitry implemented using a novel, DCAL (diode-clamped active-load) SCFL family, which is based on gate-width scaling rather than on absolute values, so that the on-chip logic voltage swing is less sensitive to process variations than conventional SCFL. A 60% improvement in noise margin is also obtained. To verify laser driving performance a back-to-back optical-fiber transmission experiment was performed, giving good optical eye diagrams at 2.5 Gb/s. The electrooptical interplay between laser-diode driver and laser-diode has been demonstrated using SPICE simulations     

2.5Gb/s限幅放大器设计

文章采用TSMC 0．35μmSiGe工艺实现了数据率达到2．5Gh／s的光纤通道限幅放大器。限幅放大器信号通道利用多级放大方式，降低了输出信号上升／下降时间，减小了级间驱动能力不匹配对信号完整性的影响：通过负反馈环路消除了信号通道上的偏移电压，采用独特的迟滞技术，使检测电路的迟滞对外接电阻变化不敏感。仿真结果证明设计方法是有效的。     

2.5Gb/s混合集成光发射机

介绍了适用于光纤通信系统且具有完全自主知识产权的混合集成光发射机的研制.该发射机采用薄膜电路和激光焊接耦合技术将高速集成电路和光电子器件进行混合集成,其中高速集成电路是采用0.35μm硅CMOS工艺实现的单片4∶1复接器加激光驱动器芯片,光电子器件是采用湿法腐蚀、聚合物平坦和lift-off等技术实现的激光器芯片,最终混合集成模块采用蝶形管壳进行封装,体积小、性能优良.该发射机工作速率为2.5Gb/s,波长为1550nm,输出光功率为5.5dBm,消光比为9.4dB.     

Inline amplifier transmission experiments over 4500 km at 2.5 Gb/s

An inline amplifier system was constructed with erbium-doped fiber amplifiers spaced at 100 km and 80 km intervals. The system transmits 2.5 Gb/s signals over 2500 km with continuous-phase frequency-shift-keying heterodyne detection and over 4500 km with intensity-modulation direct detection. With respect to amplifier output signal power levels, it is experimentally shown that there exists a dynamic range within which long-distance signal transmission can be achieved with only small receiver sensitivity degradation. The range's upper and lower limits are determined by fiber nonlinearities and amplifier noise characteristics, respectively     

High-sensitivity two-stage erbium-doped fiber preamplifier at 10Gb/s

An optical preamplifier with a record sensitivity of -38.8 dBm (102 photons/bit) at 10 Gb/s has been demonstrated. When the amplifier is employed in a practical link without an input isolator, the sensitivity is only slightly degraded to -37.6 dBm (135 photons/bit) by input coupling losses and feedback due to Rayleigh backscattering in the transmission fiber. It is predicted that this penalty can be reduced to 0.15 dB with an improved isolator in the composite EDFA     

All-Optical Packet-Switching Decoder Design and Demonstration at 10 Gb/s

A 3 times 8 all-optical decoder based on cross-polarization modulation in semiconductor optical amplifiers is demonstrated for the first time to our knowledge. The design requires a single active optical device per output. Experimental results are shown for return-to-zero modulated 10-Gb/s signals. Applications include label processing in optical packet switched optical networks     

一种2.5 Gb/s LVDS接收器设计

基于SMIC 0.18 μm 1P6M 标准CMOS工艺,设计了一种2.5 Gb/s LVDS接收器电路。仿真结果表明,所设计的LVDS电路参数符合LVDS标准,LVDS接收器的输出信号上升沿抖动约为0.76 ps,有效版图面积约为(83×44) μm²,能应用于高速数据接口。     

Eight-channel p-i-n/HBT monolithic receiver array at 2.5 Gb/s perchannel for WDM applications

We report a monolithic chip incorporating an eight channel p-i-n/HBT photoreceiver array designed for multichannel WDM applications. The p-i-n photodetectors are edge illuminated and centered at a 250 μm pitch for mating with either ribbon fiber connectors or waveguide demultiplexers. Each channel operates at 2.5 Gb/s with an electrical crosstalk of -20 dB between adjacent channels. The average sensitivity of each receiver in the array was measured to be (-20±1) dBm for a bit error rate of 10^-9 at a wavelength of 1.5 μm     

2.5Gb/s SDH/SONET指针处理器芯片实现

提出了一种2.5Gb/s同步光纤网络SDH/SONET中指针处理器芯片实现结构.指针处理器执行指针解释、通路开销性能监测功能,产生新的与系统时钟同步的STM/STS帧.指针解释模块对输入STM/STS通道的H1/H2指针进行解释,支持48通道的指针解释和每个通道的通路开销监测.采用4路总线流水线结构,77.76MHz的系统时钟,即可实时处理2.5Gb/s的SDH/SONET数据.采用TSMC 0.13μm工艺流片,技术指标符合ITU-T标准.     

2.5Gb/s SDH/SONET通路终结芯片设计

设计了一种2.5Gb/s同步光纤网络SDH/SONET中通路终结处理器芯片.采用双向4路总线流水线结构,77.76MHz的系统时钟,可实时处理2.5Gb/s的SDH/SONET数据,终结处理后输出TUG-3/VTG信号.包括通道告警、信号失效检测、性能监测和通道跟踪等.支持STS-48/STM-16、4路STS-12/STM-4和4路STS-3/STM-1的处理.     

Jitter Challenges and Reduction Techniques at 10 Gb/s and Beyond

The bandwidths of high-speed input/output (I/O) links keep increasing to meet the ever-growing demands for high-speed communications. The data rates for the leading edge high-speed I/O standards have already increased to around 10 Gb/s, including 10 GB Ethernet (GBE, 10 Gb/s, or 4 $,times,$10.3125 Gb/s, and 10$,times,$10.3125 Gb/s for Ethernet 40 G/100 G), 8$,times$ fibre channel (8.5 Gb/s), and PCI Express Gen 3 (at 8 Gb/s). At those data rates, the total available timing budget become less, data-dependent jitter gets severe, and jitter amplification becomes significant. This paper focuses on these jitter challenges and associated mitigation/reduction technologies, including jitter tracking via clock recovery, eye-opening via equalizations, and DCD cancellation via delay elements to avoid jitter amplification.      

2.5 Gb/s CMOS preamplifier for low-cost fiber-optic receivers

This paper reports an optical preamplifier intended for low-cost fiber-optic receivers. The preamplifier is based on a resistive shunt-feedback topology, is power-optimized and employs two different frequency compensation techniques, phantom zeros and shunt-peaking. The circuit is designed in a 1.8 V 0.18 μm CMOS technology. Experimental results report a transresistance of 58 dBΩ and a bandwidth of 1.5 GHz, respectively. Eye diagrams obtained at 2.5 Gb/s show a total jitter of 18 ps and a bit error rate (BER) of 10⁻¹² when the input current amplitude (I_in) is equal to or higher than 8.5 μA. Higher bit rates up to 3 Gb/s also have been tested achieving a BER of 10⁻¹² when I_in ≥9.5 μA. The power consumption and die active area are 23.7 mW and 0.017 mm², respectively.     

2.5Gb/Scmos光接收机跨阻前置放大器

给出了一种利用0.35μm CMOS工艺实现的2.5Gb/s跨阻前置放大器。此跨阻放大器的增益为59 dB*Ω,3dB带宽为2GHz,2GHz处的等效输入电流噪声为0.8×10-22 A2/Hz。在标准的5V电源电压下,功耗为250mW。PCML单端输出信号电压摆幅为200mVp-p。整个芯片面积为1.0mm×1.1mm。