FCAT—A low-voltage high-speed alterable n-channel nonvolatile memory device

The structure and principles of a new nonvolatile charge storage device are described. The Floating Si-gate Channel Corner Avalanche Transition (FCAT) memory device is an n-channel MOS transistor with a floating gate. The p⁺regions are placed outside the channel area by aligning them with the floating gate and are adjacent to the diffused n⁺source and/or drain regions. This device can operate in the write/erase modes under low-voltage (12 V) and high-speed (< 1 ms) conditions using only a pair of positive pulses. This is achieved with a novel avalanche transition at the channel corner through a relatively thin (4-6 nm thick) oxide under the open-drain condition.     

An adaptive ferroelectric transformer—A solid-state analog memory device

A new solid-state adaptive (analog memory) device is described and demonstrated. The device is a flat-band electronic transformer with adaptable voltage gain; that is, the voltage gain-frequency transfer characteristic can be "set" to different values of attenuation by the application of an adapt signal and will retain that setting after the adapt signal has been removed. Ferroelectric materials are used as the dielectric in the transformer structure composed of two capacitors bonded together so that mechanical vibrations established in one (the input capacitor) are coupled to the other (the output capacitor). Converse and direct piezoelectric effects generate the mechanical vibrations and the output voltages, respectively. Ferroelectric effects in either capacitor provide the analog memory capabilities. Experimental adaptive transformers demonstrated are suitable for audio frequency operation. The voltage and current gain-frequency transfer characteristics are flat over the entire audio frequency range. Maximum gain is typically about -20 dB. Application of a voltage pulse (100 to 300 volts) of low energy (mJ) to either side of the transformer can adapt the gains to specific lower settings (between-20 and -60 dB) within an arbitrary switching time (roughly 10⁺³to 10^-4seconds) as determined by the pulse amplitude. Gain settings are electrically stable to within a few percent of the maximum gain for periods of at least one year, and possibly indefinitely, and can be reproduced by the same or an equivalent sequence of adapting pulses.     

Atmos—An electrically reprogrammable read-only memory device

An adjustable threshold MOS (Atmos) transistor is described that can be used as an electrically reprogrammable read-only memory by changing the charge content of a floating polysilicon gate. This floating gate is charged negatively (write) by means of a nonavalanche mechanism and charged positively (erase) by the avalanche breakdown of source or drain junction and subsequent hole injection into the oxide. The write time is between 10 and 100 ms, the erase time on the order of 1 s. The charge retention of the floating gate is about 90 percent after storage for 1000 h at 125°C.     

Gridistor—A new field-effect device

This article concerns a new category of field effect transistors currently being developed which are derived from the Tecnetron (known as the Fieldtron in the U.S.A.) and which use the principal of centripetal striction and have a multichannel structure. By this development it is intended that the advantages of bipolar and field effect transistors be combined insofar as this is possible. In the theoretical part of the article the peculiarities of centripetal striction are discussed. It is shown that since the multichannel structure of the Gridistor removes the limitations arising from the restriction on the degrees of freedom, it eliminates the disadvantages of centripetal striction while retaining its advantages. The various geometries of the Gridistor and the techniques for realizing them are then described with particular attention to their remarkable suitability for integrated circuits. The results obtained are then given briefly and prospects for the future are outlined.     

The ryotron—A new cryogenic device

This paper describes a cryogenic electronic variable inductor called the ryotron. This device may be represented as a dc-isolated two-port network useful for both digital and analog circuits. Included are 1) general introduction, 2) the principle of operation, 3) experimental results, 4) device applications, and 5) discussion.     

The nesistor—A semiconductor negative resistance device

A semiconductor device similar in principle to the injecting-drain-field-effect transistor, having wide ranges of controllable negative resistance which can be used in counting, flip-flop, amplifying, and oscillator circuits, is described. The negative resistance arises from the modulation of the current between two ohmic contacts of circular symmetry, on a flat semiconductor wafer, by the effect of the collection of minority carriers on the pinching potential of a collector electrode. Families of negative resistance, of either the shunt or series type, are obtainable depending upon the mode of operation. Power gains of 60 and thermal dissipation of 1/4 watt have been achieved in liquid cooled units the size of high-frequency transistors. An improved sandwich-type base tab for mounting semiconductor wafers is shown. A theoretical analysis of the operation of the device permits prediction of the effect of various physical parameters upon the static electrical characteristics.     

The bloch-FET—A lateral surface superlattice device

We describe a lateral surface superlattice device embedded in a MOSFET structure. Control of the inversion layer density and the two-dimensional quantized inversion layer itself allows optimizing the sub-band energy level spacing for a variety of applications. In particular, the narrow bands that arise in the inversion layer itself lead to the possibility of readily achieving negative differential conductivity in the transport properties of electrons through the device.     

The ryotron—A variable inductance cryogenic device

Thin-film superconducting devices, called ryotrons, are capable of steering currents between paths by controlling the inductance in each branch. A number of different ryotron geometries are considered and analyzed. The ratio between the extreme inductance states of the ryotron is determined by the detailed configuration and by material properties. Inductance ratios as large as 146 have been observed. Using a favorable geometry, called the horseshoe ryotron, binary selection trees have been designed and operated. With a three-level, eight-output tree, the steady-state current division was achieved in 3.5×10^-9seconds.     

The COMFET—A new high conductance MOS-gated device

A new MOS gate-controlled power switch with a very low on-resistance is described. The fabrication process is similar to that of an n-channel power MOSFET but employs an n^--epitaxial layer grown on a p⁺substrate. In operation, the epitaxial region is conductivity modulated (by excess holes and electrons) thereby eliminating a major component of the on-resistance. For example, on-resistance values have been reduced by a factor of about 10 compared with those of conventional n-channel power MOSFET's of comparable size and voltage capability.     

Folded gate—A novel logic gate structure

We propose a new logic gate structure which consists of two semiconducting layers separated by an insulator. The input electrode is a rectifying contact to the top conducting layer which acts as a channel of a switching field-effect transistor. The bottom conductive layer serves as a load. The conducting layers are connected and capacitively coupled. The top layer acts as a gate for the load element whereas the bottom layer acts as a second gate for the top conductive channel. This "folded" gate is a majority-carrier device which may be implemented using different technologies and materials. It allows a CMOS-like operation with a very low power consumption in the stable states, speed comparable or higher then the speed of conventional direct-coupled field-effect transistor logic (DCFL), and a larger voltage swing.     

DIFMOS—A floating-gate electrically erasable nonvolatile semiconductor memory technology

Electrically alterable read-only memories (EAROM's) or reprogrammable read-only memories (RPROM's) can be fabricated using a single-level metal-gate p-channel MOS technology with all conventional processing steps. Given the acronym DIFMOS for dual-injector floating-gate MOS, this technology utilizes the floating-gate technique for nonvolatile storage of data. Avalanche injection of hot electrons through gate oxide from a special injector diode in each bit is used to charge the floating gates. A second injector structure included in each bit permits discharge of the floating gate by avalanche injection of holes through gate oxide. The overall design of the DIFMOS bit is dictated by the physical considerations required for each of the avalanche injector types. The end result is a circuit technology which can provide fully decoded bit-erasable EAROM-type circuits using conventional manufacturing techniques.     

Evolution of the MOSFET dynamic RAM—A personal view

The early conceptual stages and key elements in the development of the one-device MOSFET dynamic RAM are reviewed from the personal perspective of the author. Future miniaturization to the level of ¼ µm channel length and minimum lithography dimension is projected.     

A novel dynamic memory cell with internal voltage gain

A 2T1D dynamic memory cell with two transistors (T) and a gated diode (D) is presented. A gated diode is a two terminal MOS device in which charge is stored when a voltage above the threshold voltage is applied between the gate and the source, and negligible charge is stored otherwise. The gated diode acts as a nonlinear capacitance for voltage boosting, where voltage for 1-data is boosted high and voltage for 0-data stays low, achieving significant voltage gain of the internal stored voltage, higher signal margin, higher current drive and low-voltage memory operation. Details about the gated diode structure, its signal amplification, the memory cell circuits and the array structure, some hardware and test results are presented, followed by comparison to other memory cells and future directions.     

A Cr—Ag—Au metalization system

A comprehensive study of a Cr-Ag-Au metalization system, as well as a comparison with an aluminum system, is described. The Cr-Ag-Au metalization system, which can be deposited in a conventional evaporator with relatively little increase in processing complexity, has the desirable characteristics of aluminum metalization. It can be patterned more easily than equivalent thicknesses of aluminum. The Cr-Ag-Au has excellent storage characteristics at 300°C and has a much longer mean time to failure than does aluminum under high current density-high temperature stress. In addition, measurements show that with the use of an enhancement diffusion the Cr-Ag-Au produces as good as or better contact to p- and n-type silicon than does aluminum. Finally, the absence of significant metalization-oxide interaction makes Cr-Ag-Au useful for MOS devices and the ease with which contact is made between layers of this metalization indicates a number of applications for Cr-Ag-Au in multilayered devices.     

Magnetic bubbles—An emerging new memory technology

Magnetic bubbles-an emerging storage technique-promise to bridge the capacity-data retrieval time gap left vacant by magnetic core and semiconductor devices on one side and the electromechanical magnetic tape and disk on the other. Improvements in bubble materials, circuit processing, and device design have advanced bubble technology to where it is a solid candidate for applications requiring 10⁶-10⁸bits and retrieval times less than 0.005 s. Bubble chips as large as 65 kbits are currently under development. In this paper, the reader is first introduced to the topics of bubble statics and bubble dynamics, including a discussion of hard bubbles. Next, the operation of bubble devices such as propagation, generation, detection, and replication is described, as well as chip organizations using these functions. Temperature plays an important role and its effect on domain generation and data longevity is described. Fabrication techniques for bubble chips used in prototype mass memory modules and an experimental memory for a repertory telephone are given as are the overall systems' performance. Details of a 32-pin dual in-line bubble package are described. Finally, some predictions into the future are attempted for this technology. This discussion includes self-structuring propagation of bubbles and the bubble lattice file memory concept.     

A long-refresh dynamic/quasi-nonvolatile memory device with 2-nmtunneling oxide

A memory device using silicon rich oxide (SRO) as the charge trapping layer for dynamic or quasi-nonvolatile memory application is proposed. The device achieved write and erase speed at low voltage comparable to that of a dynamic-random-access memory (DRAM) cell with a much longer data retention time. This device has a SRO charge trapping layer on top of a very thin tunneling oxide (<2 nm). Using the traps in the SRO layer for charge storage, a symmetrical write/erase characteristics were achieved. This new SRO cell has an erase time much shorter than values of similar devices reported in the literature     

The buried oxide MOSFET—A new type of high-speed switching device

A MOSFET of novel structure is proposed, which has a potential advantage on its switching speed. The new structure is similar to that of SOS-MOS which essentially eliminates the junction capacitance of the MOSFET. This structure is fabricated by simultaneous deposition of single and polycrystalline silicon over silicon with selective oxidations already in place. The fabrication process and dc characteristics of the new devices are described. The speed-power characteristics are also evaluated by computer simulations.     

基于FBG传感器的新型重量动态监测装置

为了保障车用电梯安全运行,利用弹簧隔振器、缓冲垫、液压缓冲器、光纤Bragg光栅(FBG)及钢板构建了一种新型的重量实时监测装置.车重信息采用FBG进行感知.隔振器对称的安装在高强度高韧性钢板表面,FBG固定在缓冲垫上.实验研究了传感装置对不同重量车辆的响应特性,传感器受车辆碾压后Bragg谐振中心波长漂移量随时间的变...     

A lateral metal—insulator—p-Si tunnel transistor

We report the fabrication of a lateral MIS tunnel transistor whose emitter and collector are Al/SiO2/p-Si tunnel junctions. All processing is carried out at room temperature except for the growth of the passivating field oxide. The small signal common emitter current gain is 20. Two coupled gain mechanisms exist for such a lateral MIS tunnel transistor. The first mechanism relies on a high minority-carrier injection ratio of the emitter junction. Second, the minority carriers injected into the reverse-biased collector junction may produce additional gain through multiplication of majority-carrier current. Lateral MIS tunnel transistors on n-Si make use of the second mechanism. Our device takes advantage of the high minority-carrier injection ratio achievable with Al/SiO2/p-Si tunnel junctions.     

A 64 Kbit MOS dynamic RAM with novel memory capacitor

A 64 Kbit dynamic RAM is described. The RAM features a novel memory cell using a polysilicon-dielectric-polysilicon (PDP) capacitor. This structure provides performance and density advantages over the conventional approaches. A new sense amplifier configuration is also described in detail. It multiplexes two pairs of bit lines for each sense amplifier. Thus the number of memory cells per bit line is halved. This reduces the length of each bit line, thereby increasing the signal voltage available to the sense amplifier. A compatible dummy cell design is included in the discussion. Using conservative processing (3.5 /spl mu/m device channel length with 700 /spl Aring/ gate oxide thickness) a die size of 3.2 mm/spl times/7.9 mm is achieved. Experimental data are presented in the text.