A parallel 3-D discrete wavelet transform architecture using pipelined lifting scheme approach for video coding

This article presents a parallel architecture for 3-D discrete wavelet transform (3-DDWT). The proposed design is based on the 1-D pipelined lifting scheme. The architecture is fully scalable beyond the present coherent Daubechies filter bank (9,?7). This 3-DDWT architecture has advantages such as no group of pictures restriction and reduced memory referencing. It offers low power consumption, low latency and high throughput. The computing technique is based on the concept that lifting scheme minimises the storage requirement. The application specific integrated circuit implementation of the proposed architecture is done by synthesising it using 65?nm Taiwan Semiconductor Manufacturing Company standard cell library. It offers a speed of 486?MHz with a power consumption of 2.56?mW. This architecture is suitable for real-time video compression even with large frame dimensions.     

二维离散5/3小波变换并行VLSI结构设计

提出了一种基于提升算法的二维离散5/3小波变换(DWT)高效并行VLSI结构设计方法。该方法使得行和列滤波器同时进行滤波,采用流水线设计方法处理,在保证同样的精度下,大大减少了运算量,提高了变换速度,节约了硬件资源。该方法已通过了VerilogHDL行为级仿真验证,可作为单独的IP核应用在JPEG2000图像编、解码芯片中。该结构可推广到9/7小波提升结构。     

A 100-MHz 64-tap FIR digital filter in 0.8-μm BiCMOS gate array

A 64-tap FIR (finite impulse response) digital filter that has been designed using a newly developed filter compiler and fabricated in a 0.8-μm triple-level interconnect BiCMOS gate array technology is presented. The filter has been tested and is fully functional at a 100-MHz clock rate. These results are obtained by combining an optimized architecture and gate array floorplan with submicrometer BiCMOS technology. The filter occupies 49 mm², which is approximately two-thirds of the 100 K gate array core. The design uses an equivalent of 55 K gates (two-input NAND gates). The device input/output are 100 K emitter-coupled-logic (ECL) compatible     

一种基于FPGA的FIR滤波器实现结构

提出了一种在FPGA中能灵活实现各种FIR滤波器的结构。该结构以使用流水线技术的高速乘法累加器(Multiple Accumulator,MAC)为核心,通过逻辑设计中时间-空间的互换,以最优的资源消耗来实现各种性能的FIR滤波器.最后以DVB-C系统中基带成形滤波器的设计实现为例与传统实现结构进行比较,结果表明此实现结构能灵活处理综合面积和速度的约束关系,具有更优的性价比.     

Image-rejection CMOS low-noise amplifier design optimization techniques

This paper reviews and analyzes two reported image-rejection (IR) low-noise amplifier (LNA) design techniques based on CMOS technology, i.e., the second-order active notch filer and third-order passive notch filter. The analyses and discussions are based on the quality factor of filters and the ability of the frequency control. As the solution to deal with the suitable on-chip filter, this paper proposes a new notch-filter topology that can overcome the limitations of the two previous reported studies. In addition, the LNA design method satisfying the power-cons-trained simultaneous noise and input matching, as well as the linearity optimization conditions is introduced. By using the proposed notch filter and proposed design methodology, an IR LNA used in the superheterodyne architecture is implemented. The proposed IR LNA, designed based on 0.18-mum CMOS technology with total current dissipation of 4 mA under 3-V supply voltage, is optimized for a 5.25-GHz wireless local area network with IF frequency of 500-MHz applications. The measurement results show 20.5-dB power gain, lower than 1.5-dB noise figure, -5-dBm input-referred third-order intercept point and an IR of 26 dB     

FIR filter optimization using bit-edge equalization in high-speed backplane data transmission

A unique bit-edge equalization (BEE) method for mitigating intersymbol interference (ISI) in high-speed backplane applications is presented. Using a least-mean-square (LMS) adaptive algorithm as a receiver (RX) error convergence engine, the proposed BEE method aims to optimize the bit-edge amplitudes by equalizing only the edges of data bits with an adjustment of the sampling points where the error information is collected. This adjustment of sampling points in turn changes the error information and affects filter coefficients for pulse amplitude modulation. As a result, the channel's far-end 3-level bit-edge eye diagrams can be optimized. This proposed BEE method employs transmitter (TX) pre-coding in conjunction with TX pre-emphasis using a symbol-spaced FIR (SSF) filter. In this work, a detailed analytical comparison of the proposed BEE transceiver architecture with the conventional NRZ bit-centre equalization (BCE) and duobinary transceiver architectures is presented. The simulation results demonstrate that at 10+ Gbps data rates, the proposed BEE is the most effective method for mitigating ISI in relatively high-loss channels.     

A Fully Multiplexed First-Order Frequency-Planar Module for Fan, Beam, and Cone Plane-Wave Filters

A VLSI architecture for the on-chip realization of a first-order two-dimensional (2-D) or three-dimensional (3-D) infinte impulse response (IIR) fully multiplexed frequency-planar filter module (FMFPM) is proposed. Such filter modules may be used in 3-D video processing and 2-D/3-D plane-wave filtering using sensor arrays. The proposed FMFPM can potentially be used as a 2-D/3-D IIR building block circuit for the on-chip realization of second- (or higher) order frequency-planar filters, 3-D IIR beam filters, 2-D IIR fan filter banks and 3-D IIR cone filter banks.     

An adaptive inverse halftoning algorithm

A class of inverse halftoning algorithms that recovers grayscale (continuous-tone) images from halftone images is proposed. The basic structure is an optimized linear filter. Then, a properly designed adaptive postprocessor is employed to enhance the recovered image quality. Finally, a multistage space-varying algorithm is developed that uses the basic linear filter structure as before but with spatially adaptive parameters.     

An optimized blockwise nonlocal means denoising filter for 3-D magnetic resonance images

A critical issue in image restoration is the problem of noise removal while keeping the integrity of relevant image information. Denoising is a crucial step to increase image quality and to improve the performance of all the tasks needed for quantitative imaging analysis. The method proposed in this paper is based on a 3-D optimized blockwise version of the nonlocal (NL)-means filter (Buades, , 2005). The NL-means filter uses the redundancy of information in the image under study to remove the noise. The performance of the NL-means filter has been already demonstrated for 2-D images, but reducing the computational burden is a critical aspect to extend the method to 3-D images. To overcome this problem, we propose improvements to reduce the computational complexity. These different improvements allow to drastically divide the computational time while preserving the performances of the NL-means filter. A fully automated and optimized version of the NL-means filter is then presented. Our contributions to the NL-means filter are: 1) an automatic tuning of the smoothing parameter; 2) a selection of the most relevant voxels; 3) a blockwise implementation; and 4) a parallelized computation. Quantitative validation was carried out on synthetic datasets generated with BrainWeb (Collins, , 1998). The results show that our optimized NL-means filter outperforms the classical implementation of the NL-means filter, as well as two other classical denoising methods [anisotropic diffusion (Perona and Malik, 1990)] and total variation minimization process (Rudin, , 1992) in terms of accuracy (measured by the peak signal-to-noise ratio) with low computation time. Finally, qualitative results on real data are presented.     

应用于JPEG2000的5/3提升小波的VLSI结构设计

提出一种基于提升算法（lifting scheme）实现JPEG2000编码系统中的二维离散小波变换（Discrete Wavelet Transform）的并行阵列式的VLSI结构设计方法.该结构由一个行处理器和一个列处理器组成,行、列处理器通过时分复用同时进行滤波,用优化的移位加操作替代乘法操作,采用嵌入式数据延拓算法处理边界延拓.整个结构采用流水线设计方法,减少了运算量,提高了硬件资源利用率,该结构可应用于JPEG2000图像编码芯片中.     

Graphene nanoribbon crossbar architecture for low power and dense circuit implementations

Crossbar array is a promising nanoscale architecture which can be used for logic circuit implementation. In this work, a graphene nanoribbon (GNR) based crossbar architecture is proposed. This design uses parallel GNRs as device channel and metal as gate, source and drain contacts. Schottky-barrier type graphene nanoribbon field-effect transistors (SB-GNRFETs) are formed at the cross points of the GNRs and the metallic gates. Benchmark circuits are implemented using the proposed crossbar, Si-CMOS and multi-gate Si-CMOS approaches to evaluate the performance of the crossbar architecture compared to the conventional CMOS logic design. The compact SPICE model of SB-GNRFET was used to simulate crossbar-based circuits. The CMOS circuits are also simulated using 16 nm technology parameters. Simulation results of benchmark circuits using SIS synthesis tool indicate that the GNR-based crossbar circuits outperform conventional CMOS circuits in low power applications. Area optimized cell libraries are implemented based on the asymmetric crossbar architecture. The area of the circuit can be more reduced using this architecture at the expense of higher delay. The crossbar cells can be combined with CMOS cells to exhibit better performance in terms of EDP.     

Hardware architecture for an anti-traffic noise system

This work presents an energy efficient architecture for an anti-traffic noise system. The hardware is designed for a road side unit (RSU) in intelligent transportation systems. Fast Fourier Transform is the cornerstone for the suggested system. An ultra low power architecture for the FFT suitable for FPGA implementation is derived. Bit-widths for both data and twiddle factors are optimized for low-power. The architecture uses an efficient complex multiplier that has 25% less multiplications. An algorithm to compute the number of time-shared butterflies for a given FFT block size and a target throughput is elaborated. Finally synthesis results using fixed-point VHDL library and commercial IP are presented and compared with the proposed FFT processor.     

一种新偏压结构的BST电容梳状滤波器设计

介绍了一种五阶可调抽头式梳状线滤波器,设计采用共面方式接地,使用Ba0.6Sr0.4TiO3 (BST)铁电薄膜平板电容作为可调部件,并分析了平板电容结构的影响.针对梳状电调滤波器需单阶加压和外接大电阻繁琐的情况,提出利用集成在衬底上的大容量BST电容作为隔离电容,将各阶谐振器的偏压线互连来简化加压过程.运用高频电磁仿真软件HFSS进行验证,设计出的滤波器中心频率可调范围为842～960 MHz(14％),3 dB带宽为9％～10％.     

Enhanced multi-level filter algorithm and its VLSI architecture

This paper presents an enhanced multi-level filter algorithm and its Very Large Scale Integration (VLSI) architecture for infrared image processing. The modified multi-level filter algorithm resolves the splitting targets problem using Gaussian pyramid processing. Owning three filtering paths, the proposed VLSI architecture of the filter can simultaneously enhance small targets with different sizes in infrared images. Some design techniques in implementing hardwired multiplication, subsample and asynchronous FIFO have been presented. This VLSI architecture has been implemented using Semiconductor Manufacturing International Corporation (SMIC) 0.35?µm 4-layer CMOS technology. The simulation results show that it not only effectively suppresses background, eliminates noise and enhances small targets in an infrared image comparing with other small target detective methods, but also meets infrared image real-time processing requirements (5?M?～?10?M pixels/s). The implemented filter chip consists of 60,284 gates and 8?K Static Random Access Memory (SRAM), operates at 50?MHz.     

Low-Power,Low-Complexity Bit-Serial VLSI Architecture for 1D Discrete Wavelet Transform

The discrete wavelet transform (DWT) is an upcoming compression technique that has been selected for MPEG-4 and JEPG 2000, because it has no blocking effects and it efficiently determines the frequency property of the temporary signals. In this paper, we propose a low-complexity, low-power bit-serial DWT architecture, employing a two-channel lattice-based quadrature mirror filter (QMF). The filter consists of four lattices (filter length = 8), and we determine the quantization bit for the coefficients using a fixed-length peak signal-to-noise ratio analysis and propose the architecture of the bit-serial multiplier with a fixed coefficient. The canonical signed digit encoding for the coefficients is applied to minimize the number of nonzero bits, thus reducing the hardware complexity. The proposed folded one-dimensional DWT architecture processes the other resolution levels during idle periods by decimations, and it provides efficient scheduling. The proposed architecture requires only flip-flops and full adders. This architecture has been designed and verified by the Verilog HDL and synthesized using the Synopsys Design Compiler with the DongbuAnam 0.18 μm Standard Cell Library. The maximum throughput is 393 Mbps at 450 MHz with a latency of 16 clocks, and the gate count is about 5K in equivalent two-input NAND gates. The dynamic power is 7.02 mW at 1.8 V. The data scheduling using a data dependency graph, and the performance, power, and required hardware cost are discussed.     

A Low Power Architecture for HASM Motion Tracking

This paper proposes low power VLSI architecture for motion tracking that can be used in online video applications such as in MPEG and VRML. The proposed architecture uses a hierarchical adaptive structured mesh (HASM) concept that generates a content-based video representation. The developed architecture shows the significant reducing of power consumption that is inherited in the HASM concept. The proposed architecture consists of two units: a motion estimation and motion compensation units.The motion estimation (ME) architecture generates a progressive mesh code that represents a mesh topology and its motion vectors. ME reduces the power consumption since it (1) implements a successive splitting strategy to generate the mesh topology. The successive split allows the pipelined implementation of the processing elements. (2) It approximates the mesh nodes motion vector by using the three step search algorithm. (3) and it uses parallel units that reduce the power consumption at a fixed throughput.The motion compensation (MC) architecture processes a reference frame, mesh nodes and motion vectors to predict a video frame using affine transformation to warp the texture with different mesh patches. The MC reduces the power consumption since it uses (1) a multiplication-free algorithm for affine transformation. (2) It uses parallel threads in which each thread implements a pipelined chain of scalable affine units to compute the affine transformation of each patch.The architecture has been prototyped using top-down low-power design methodology. The performance of the architecture has been analyzed in terms of video construction quality, power and delay.     

一种高效的三维DWT VLSI结构设计方法

文中通过深入研究三维离散小波变换(3D DWT)核心算法并根据序列图像编码的特点,设计并实现了一种适合硬件实现的高效的三维小波变换VLSI结构。编写了相应verilog模型,并进行了仿真和逻辑综合。仿真结果表明行列滤波并行处理并采用流水线设计方法,加快了运算速度,有效降低了片内存储容量。     

MULTI-LEVEL FILTER FOR INFRARED IMAGE PROCESSING

This paper presents a new multi-level filter algorithm and its corresponding VLSI architecture for infrared image processing. The algorithm eliminates the phenomena of splitting targets by inserting Gaussian pyramid processing. Owning three filter paths, the proposed filter VLSI architecture can enhance small targets with different size in infrared images. This architecture has been implemented using SMIC 0.35μm 4-layer CMOS technology. The test result shows that the filter chip not only effectively suppresses background, eliminates noise and enhances small targets in an infrared image, but also meets infrared image real-time processing requirement(5M ～ 10M pixels/s). The implemented filter chip consists of 60,284 gates and 8K SRAM, operates at 50MHz.