电子电路故障检测技术与方法

随着电子科技的不断发展,电子产品的种类和数量越来越多。在封装、焊接和使用过程中,受到各种因素的影响,电子产品的电子电路可能会出现一定的故障,不仅影响电子产品的质量,也降低了其使用安全性和可靠性。因此,必须要加强对电子电路故障的检测。     

电子电路故障的检测方法探究

<正>在现代科技快速发展的过程中，电子电路在各种设备中的应用变得更加常见，电子电路的复杂性也越来越高。虽然现代机械设备的精度得到有效的提升，但其在工作的过程中依然基于基础的电子电路工作原理。因此，电子电路在发生故障的情况下，极易导致电子设备无法正常工作或者出现损坏的现象。在保障相关设备能够正常运行过程中，需要对电子电路常见的故障类型、故障检测方法进行有效的研究。本文针对电子电路故障的主要类型进行梳理，在此基础上对故障检测方法进行全面的分析，针对不同检测方法的作用原理进行深入的研究，从而再组合使用不同的故障检测方法，精准确定电子电路的故障，为提升相关设备的可靠性提供良好的技术保障。     

电子电路故障检测技术探索

本文深入探究电子电路障碍检测技术出现故障的原因,对电子电路故障的检测技术实施具体分析。     

电力电子电路智能故障诊断技术研究

随着我们国家经济的不断发展,很多的行业和领域中使用到了电力电子的产品或者是装置,这些产品和装置在我们国家的发展中起到了很重要的作用。虽然说电力电子产品的使用在很大程度上提升了效率,但是在使用的过程中电力电子电路也经常出现一些问题,这些问题的出现给电力电子的使用带来了很大的问题,其中电力电子电路智能故障的诊断就成了我们研究的重点,只有将这部分技术发展起来,才能在最大限度上保证电力电子电路智能故障的解决,也才能保证电力电子产品的正常使用。文章简要阐述了电力电子电路智能故障诊断技术相关的问题。     

电子电路故障检测技术研究

在电子电路的调试和应用中，不可避免的会出现各种各样的故障，那么及时有效地排除相关故障，就成为电子电路达到预定技术指标的关键技术。本文在详细分析了电子电路产生故障的原因以及出现故障时存在的一些外显表现后，结合多年工作经验，总结了对于一般性故障的多种检测方法以及相关注意事项，并对电子电路故障检测方法的系统化进行了积极探索。对相关工作人员能够迅速、准确地分析、寻找并排除电子电路的故障，有一定借鉴意义。     

故障检测技术在电子电路的研究

本文首先说明并分析电子电路的故障表现和故障原因;接着列举出在电子电路中应用的故障检测技术都有哪些,并对这些技术做出一定的阐述;最后指出电子电路故障检测时的注意事项,以提高电子电路故障检测效率,保护电子电路运行和维护安全.     

浅谈仿真技术在电子产品设计中的应用

本文重点梳理了目前国内技术应用水平相对成熟的电子电路仿真技术在电子产品集成电路设计过程中的应用模式,从如何发挥电子电路仿真技术优势入手,探讨了电子电路仿真技术在电子产品集成电路设计中的具体应用策略。     

焊接随谈

从开始生产电子产品到今天，焊接就一直是连接电子电路的基本手段，无论是电子爱好者还是专业电子工厂，只要动手制作(或维修)或批量生产电子产品，就离不开焊接。在焊接工程中，其焊点的质量在很大程度上影响整机的工作状态，任何一个焊点出现故障，将会使机器产生故障而不能正常工作。找寻失效的焊点，需花费一定的时间和精力，因而在学习焊接技术时要注意焊点的质量，乃是提高产品质量和可靠性的重要环节。     

电子电路仿真技术在电子应用开发中的作用分析

现代科技的发展使得各类电子设备频繁出现在人们的日常生活中,为人们的日常生活提供了很大的便利,也从一定意义上提升了现代技术发展的水平。随着电子产品创新的速度加快,电子电路的专业研发人员也将不断创新电子产品的应用,以便根据时代的发展需要提供更好的服务。应用新技术开发是实现技术创新的关键措施。电子电路仿真技术在电子产品技术研发中的运用,能够减少开发周期,提升研发效能,在电子产品工业研发中起到关键性作用。文中首先对电子电路仿真技术的特性进行研究,然后进一步阐述电子应用开发中的电子电路仿真技术的作用,最后提出电子应用开发中电子电路仿真技术的策略。     

电子电路的故障检测技术

在科技不断发展的大背景下,电子设备渐渐的进入到人们视野中。不论是在日常的生活中,还是在工作中,电子设备都随处可见。电子设备经长时间使用,或多或少会出现故障。若这些故障不排除,将严重阻碍电子设备的使用。排除电子电路故障的前提就是要检测出故障。通过分析和研究电子电路故障检测技术,以期确保电子设备能正常使用。     

Design of self-testing and on-line fault detection combinational circuits with weakly independent outputs

In this article we propose a structure dependent method for the systematic design of combinational selftesting fault detection circuits that is well adapted to the arbitrarily chosen technical fault model. According to the fault model considered the outputs of the circuit are partitioned into different generally nondisjoint groups of weakly independent outputs. The parities of these groups of weakly independent outputs are compared in test mode as well as in normal operation mode with the corresponding predicted parities by use of a self-checking checker. For on-line detection, the hardware is in normal operation mode, and for testing, it is in test mode. In the test mode, these fault detection circuits guarantee a 100% fault coverage for single stuck-at-0/1 faults and a high fault coverage for arbitrary faults. In normal operation mode all technical faults considered will be detected possibly, with some degree of latency.Partially presented at the VLSI Test Symposium, Atlantic City, 1992.     

Fault Diagnosis of Analog Circuits Using Systematic Tests Based on Data Fusion

An analog fault diagnosis approach using a systematic step-by-step test is proposed for fault detection and location in analog circuits with component tolerance and limited accessible nodes. First, by considering soft faults and component tolerance, statistics-based fault detection criteria are established to determine whether a circuit is faulty by measuring accessible node voltages. For a faulty circuit, fuzzy fault verification is performed using the accessible node voltages. Furthermore, using an approximation technique, the most likely faulty elements are identified with a limited number of circuit gain measurements at selected frequencies. Finally, employing the D-S evidence theory, synthetic decision is made to locate faults according to the results of fault verification and estimation. Unlike other methods which use a single diagnosis method or a particular type of measurement information, the proposed approach makes use of the redundancy of different types of measurement information and the combined use of different diagnosis methods so as to improve diagnosis accuracy.     

BP网络改进及在电路故障诊断中的应用

本文根据ＢＰ神经网络的特点和性能以及电路故障诊断的要求，提出了一种利用ＢＰ神经网络对电路进行故障诊断的方法。该方法应用自行改进的ＢＰ抑经网络，建立了故障识别系统，并对模拟电路故障诊断进行了实例实现，计算机仿真结果良好。     

基于FPGA的功能域隔离电路设计

静态随机存储器(Static Random Access Memory, SRAM)型现场可编程门阵列（Field Programmable Gate Array, FPGA）广泛应用于航空航天系统中,但是高空中FPGA易受高能粒子影响造成配置出错,互联资源上发生的单点错误可能导致跨域故障,使芯片内多个模块同时失效。跨域故障可能导致电路中的工作模块与检错模块同时故障,使设备中存在不能被检测到的隐蔽故障。针对上述问题,提出在芯片上将不同功能的模块相互隔离,并通过约束实现模块间可信通信的故障隔离方法,将故障限定在单一模块内,防止多个模块同时失效,提高电路的容错能力。通过故障注入评估隔离设计前后的航空电子全双工交换式以太网（Avionics Full Duplex Switched Ethernet, AFDX）电路的各类故障发生率。实验结果证明隔离设计可以与电路原有的检错容错机制结合,将隐蔽故障的发生率降为原来的3%。     

A Binary Decision Diagram based on-line testing of digital VLSI circuits for feedback bridging faults

Classical manufacturing test verifies that a circuit is fault free during fabrication, however, cannot detect any fault that occurs after deployment or during operation. As complexity of integration rises, frequency of such failures is increasing for which on-line testing (OLT) is becoming an essential part in design for testability. In majority of the works on OLT, single stuck at fault model is considered. However in modern integration technology, single stuck at fault model can capture only a small fraction of real defects and as a remedy, advanced fault models such as bridging faults, transition faults, delay faults, etc. are now being considered. In this paper we concentrate on bridging faults for OLT. The reported works on OLT using bridging fault model have considered non-feedback faults only. The basic idea is, as feedback bridging faults may cause oscillations, detecting them on-line using logic testing is difficult. However, not all feedback bridging faults create oscillations and even if some does, there are test patterns for which the fault effect is manifested logically. In this paper it is shown that the number of such cases is not insignificant and discarding them impacts OLT in terms of fault coverage and detection latency. The present work aims at developing an OLT scheme for bridging faults including the feedback bridging faults also, that can be detected using logic test patterns. The proposed scheme is based on Binary Decision Diagrams, which enables it to handle fairly large circuits. Results on ISCAS 89 benchmarks illustrate that consideration of feedback bridging faults along with non-feedback ones improves fault coverage, however, increase in area overhead is marginal, compared to schemes only involving non-feedback faults.     

基于冗余有限域算术的AES S盒高效故障检测方案

为使AES S盒的多奇偶校验故障检测方案具备预期故障检测能力,提出了由预期故障覆盖率确定预测奇偶总数的参数计算模型.根据模型确定的预测奇偶总数,为基于冗余有限域算术的S盒定制了两种多分块多奇偶校验的故障检测方案.推导优化了各分块预测奇偶计算公式,并通过穷举搜索找到了使整个电路结构最优的多项式系数与映射矩阵.仿真结果表明两种方案的随机多故障覆盖率均约为97%,验证了参数计算模型的有效性,突发故障覆盖率分别约为61.8%、76.3%,优于已有文献中大部分故障检测方案.综合结果表明,对比于已有文献中具有相似故障检测能力的故障检测S盒电路,所设计电路的面积-延时积最小.     

Improving the Transition Fault Coverage of Functional Broadside Tests by Observation Point Insertion

Functional broadside tests were defined to address overtesting that may occur due to high peak current demands when tests for delay faults take the circuit through states that it cannot visit during functional operation (unreachable states). The fault coverage achievable by functional broadside tests is typically lower than the fault coverage achievable by (unrestricted) broadside tests. A solution to this loss in fault coverage in the form of observation point insertion is described. Observation points do not affect the state of the circuit. Thus, functional broadside tests retain their property of testing the circuit using only reachable states to avoid overtesting due to high peak current demands. However, the extra observability allows additional faults to be detected. A procedure for observation point insertion to improve the coverage of transition faults is described. Experimental results are presented to demonstrate that significant improvements in transition fault coverage by functional broadside tests is obtained.     

Hazard-Based Detection Conditions for Improved Transition Fault Coverage of Scan-Based Tests

We define a new type of detection conditions for delay faults, referred to as hazard-based detection conditions, to enhance the coverage of delay faults using the standard scan test application methods. Some delay faults, including irredundant faults, may be undetectable under the conventional detection conditions. These faults may be detectable under the hazard-based detection conditions. The use of hazard-based detection conditions thus improves the delay fault coverage achievable for a circuit. We consider transition faults under standard scan for the study in this paper.      

利用BIT技术提高雷达维修性

在现代复杂电子系统中,机内测试(BIT)技术作为提高系统可维修性和可测试性的重要手段,日益得到普遍重视和广泛应用。根据设计原则,BIT系统采用多机分布式结构,故障检测电路和故障检测软件采用通用化设计,故障定位采用基于故障传播有向图的故障定位方法。本文对雷达设备的维修性及状态监测方面进行了探索,主要阐述了机内测试系统的实现结构及其基于故障树算法实现故障定位的原理,介绍了通用故障检测电路的工作原理,总结了设计过程中应注意的问题及相应的解决方法。