A thermally robust Ni-FUSI process using in 65 nm CMOS technology

The interest in the low resistivity fully silicided (FUSI) gate increased significantly because of promising in use as contact to the source, drain, and gate for sub−65 nm/45 nm CMOS devices. NiSi is potentially an attractive material due to its capability to maintain low resistivity even for channel length down to 100 nm. The Formation of thermally stable silicide gates is important for improving the devices fabrication processes. In order to obtain a thermally stable Ni-FUSI gate electrode, we introduced a two-step annealing process associated with properly tuned thickness of the initial Ni film and additional of implantation of BF₂ during the poly-gate formation to push the transformation of NiSi₂ to higher temperatures at about 900°C and retard agglomeration. A mixed-phase of nickel silicide layer was commonly observed during phase transformation. For the first time, we established an effective way to identify the phase transformations by some nondestructive techniques such as X-ray diffraction, sheet resistance measurement and AFM analysis. The correlations between its electrical and morphological changes during Ni–Si phase transformation were presented. Furthermore, the effect with addition amount of BF₂ impurities into NiSi was investigated. F-incorporation demonstrated some improvements in both morphology and phase stability of the NiSi films at high processing temperatures.     

Dopant enhanced in nickel silicide formation for high-<Emphasis Type="Italic">k</Emphasis> dielectric applications

The thermal stability of fully silicided NiSi with arsenic doping on silicon was investigated. The combination of full nickel silicidation gate electrodes and hafnium based high-k gate dielectrics is one of the most promising gate stacks to replace poly-Si/SiO₂/Si gate stacks in the future complementary metal–oxide–semiconductor (CMOS) sub-45 nm technology node. The aims of the work were to investigate the Ni silicide phase-related issues associated with arsenic dopant and thermal annealing on Ni–FUSI/HfO₂/Si and Ni–FUSI/HfSiO/Si gate stacks. It was found that arsenic-incorporation demonstrated some improvement in both morphology and phase stability of nickel silicided films at high processing temperatures regardless underlying gate dielectrics. The correlations of Ni–Si phase transformation and arsenic doapnt with their electrical and physical changes were established by sheet resistance measurements, X-ray diffraction (XRD), atomic force microscopy (AFM), and X-ray photoelectron spectroscopy (XPS) analysis. Furthermore, the modulation of the work function (WF) of Ni fully silicided gates by arsenic impurity is presented, comparing the effects of dopant (As) on the WF and silicide phases (NiSi and NiSi₂). It confirmed that the work function of NiSi can be tuned by implanting arsenic dopant, but it ineffective for NiSi₂ phase.     

Growth of nickel silicides in Si and Si/SiOx core/shell nanowires

We exploited the oxide shell structure to explore the structure confinement effect on the nickel silicide growth in one-dimensional nanowire template. The oxide confinement structure is similar to the contact structure (via hole) in the thin film system or nanodevices passivated by oxide or nitride film. Silicon nanowires in direct contact with nickel pads transform into two phases of nickel silicides, Ni31Si12 and NiSi2, after one-step annealing at 550 °C. In a bare Si nanowire during the annealing process, NiSi2 grows initially through the nanowire, followed by the transformation of NiSi2 into the nickel-rich phase, Ni31Si12 starting from near the nickel pad. Ni31Si12 is also observed under the nickel pads. Although the same phase transformations of Si to nickel silicides are observed in nanowires with oxide confinement structure, the growth rate of nickel silicides, Ni31Si12 and NiSi2, is retarded dramatically. With increasing oxide thickness from 5 to 50 nm, the retarding effect of the Ni31Si12 growth and the annihilation of Ni2Si into the oxide confined-Si is clearly observed. Ni31Si12 and Ni2Si phases are limited to grow into the Si/SiOx core-shell nanowire as the shell thickness reaches 50 nm. It is experimental evidence that phase transformation is influenced by the stressed structure at nanoscale.     

Extremely scaled 3-dimensional multiple-gate technologies for terabit era

In order to make possible silicon-based, room-temperature operable devices having a feature size in the sub-5 nm range, an all-around gate FinFET having an extremely narrow gate-surrounded silicon fin with a floating body was proposed and fabricated. Sub-10 nm device issues such as short channel effects, punchthrough, source/drain series resistance, gate misalignment, and hot-carrier injection were intensively studied and optimized for the sub-5 nm structure. The sub-5 nm all-around gate FinFET with 3 nm fin width and 1.2 nm EOT was demonstrated for the first time.     

Addressing materials and integration issues for NiSi silicide contact metallization in nano-scale CMOS devices

As the industry approaches sub-100 nm technology nodes, the trend is to replace cobalt silicide with nickel monosilicide (NiSi) since the use of NiSi for contact metallization shows a number of technological advantages, including its line-width independent low resistivity, less Si consumption and low thermal budget for its formation, and compatibility with Si_1 − xGe_x substrate technology. However, NiSi has not been considered as a serious candidate until recently mainly due to its poor morphological/thermal stability. Recent studies have shown that the morphological/thermal stability of NiSi can be enhanced substantially through the addition of a small amount of impurities, resulting in much improved silicided shallow junction integrity. Moreover, it has also been demonstrated that the addition of certain impurities, such as Ti, effectively reduces the sensitivity of NiSi formation to surface contaminants (e.g., residual interfacial oxide). This paper will present and discuss the details of these experimental results.     

In situ control of atomic-scale Si layer with huge strain in the nanoheterostructure NiSi/Si/NiSi through point contact reaction

Nanoheterostructures of NiSi/Si/NiSi in which the length of the Si region can be controlled down to 2 nm have been produced using in situ point contact reaction between Si and Ni nanowires in an ultrahigh vacuum transmission electron microscope. The Si region was found to be highly strained (more than 12%). The strain increases with the decreasing Si layer thickness and can be controlled by varying the heating temperature. It was observed that the Si nanowire is transformed into a bamboo-type grain of single-crystal NiSi from both ends following the path with low-activation energy. We propose the reaction is assisted by interstitial diffusion of Ni atoms within the Si nanowire and is limited by the rate of dissolution of Ni into Si at the point contact interface. The rate of incorporation of Ni atoms to support the growth of NiSi has been measured to be 7 x 10(-4) s per Ni atom. The nanoscale epitaxial growth rate of single-crystal NiSi has been measured using high-resolution lattice-imaging videos. On the basis of the rate, we can control the consumption of Si and, in turn, the dimensions of the nanoheterostructure down to less than 2 nm, thereby far exceeding the limit of conventional patterning process. The controlled huge strain in the controlled atomic scale Si region, potential gate of Si nanowire-based transistors, is expected to significantly impact the performance of electronic devices.     

Compositional characterization of nickel silicides by HAADF-STEM imaging

A methodology for the quantitative compositional characterization of nickel silicides by high angle annular dark field scanning transmission electron microscopy (HAADF-STEM) imaging is presented. HAADF-STEM images of a set of nickel silicide reference samples Ni₃Si, Ni₃₁Si₁₂, Ni₂Si, NiSi and NiSi₂ are taken at identical experimental conditions. The correlation between sample thickness and HAADF-STEM intensity is discussed. In order to quantify the relationship between the experimental Z-contrast intensities and the composition of the analysed layers, the ratio of the HAADF-STEM intensity to the sample thickness or to the intensity of the silicon substrate is determined for each nickel silicide reference sample. Diffraction contrast is still detected on the HAADF-STEM images, even though the detector is set at the largest possible detection angle. The influence on the quantification results of intensity fluctuations caused by diffraction contrast and channelling is examined. The methodology is applied to FUSI gate devices and to horizontal TFET devices with different nickel silicides formed on source, gate and drain. It is shown that, if the elements which are present are known, this methodology allows a fast quantitative 2-dimensional compositional analysis.     

An ordered Si nanowire with NiSi2 tip arrays as excellent field emitters

A method was developed to grow ordered silicon nanowire with NiSi(2) tip arrays by reacting nickel thin films on silica-coated ordered Si nanowire (NW) arrays. The coating of thin silica shell on Si NW arrays has the effect of limiting the diffusion of nickel during the silicidation process to achieve the single crystalline NiSi(2) NWs. In the meantime, it relieves the distortion of the NWs caused by the strain associated with formation of NiSi(2) to maintain the straightness of the nanowire and the ordering of the arrays. Other nickel silicide phases such as Ni(2)Si and NiSi were obtained if the silicidation processes were conducted on the ordered Si NWs without a thin silica shell. Excellent field emission properties were found for NiSi(2)/Si NW arrays with a turn on field of 0.82 V μm(-1) and a threshold field of 1.39 V μm(-1). The field enhancement factor was calculated to be about 2440. The stability test showed a fluctuation of about 7% with an applied field of 2.6 V μm(-1) for a period of 24 h. The excellent field emission characteristics are attributed to the well-aligned and highly ordered arrangement of the single crystalline NiSi(2)/Si heterostructure field emitters. In contrast to other growth methods, the present growth of ordered nickel silicide/Si NWs on silicon is compatible with silicon nanoelectronics device processes, and also provides a facile route to grow other well-aligned metal silicide NW arrays. The advantages will facilitate its applications as field emission devices.     

Effect of initial composition on phase selection in Ni–Si powder blends processed by mechanical alloying

The effect of initial powder blend composition on the synthesis and formation mechanism of nickel silicide phases was investigated by mechanical alloying in Ni-60 and Ni-66.7?at.% Si powder blends. It was noted that the equilibrium NiSi phase started to form in the early stages of milling and that the amount of the NiSi phase in the milled powder increased with increasing milling time. Even though, under equilibrium conditions, a mixture of both the NiSi and NiSi₂ phases was expected to be present in the Ni-60?at.% Si composition and the stoichiometric NiSi₂ phase in the Ni-66.7?at.% Si composition, the NiSi phase was present in both the compositions investigated. However, while only the NiSi phase was present homogeneously in the Ni-60?at.% Si powder blend, both the NiSi phase and a very small amount of unreacted Si were present in the powder blend of Ni-66.7?at.% Si composition. This unexpected phase constitution in the milled powders was attributed to a partial loss of Si during mechanical alloying of the powder blends, confirmed by energy dispersive X-ray spectrometer analyses, and explained on a thermodynamic basis.     

Direct electrical measurement of the self-assembled nickel silicide nanowire

We present results from the direct electrical measurement of an as-grown nanowire. The nickel silicide (NiSi) nanowire was spontaneously grown across a trench between two electrodes used for measurement. The NiSi nanowire, 58 nm in diameter and 2.9 microm in length, showed a low resistance characteristic of 147.9 Omega. This unique method is straightforward and does not require removal of a grown nanowire to be moved into a measurement environment.     

Sub-100 nanometer channel length Ge/Si nanowire transistors with potential for 2 THz switching speed

Ge/Si core/shell nanowires (NWs) are attractive and flexible building blocks for nanoelectronics ranging from field-effect transistors (FETs) to low-temperature quantum devices. Here we report the first studies of the size-dependent performance limits of Ge/Si NWFETs in the sub-100 nm channel length regime. Metallic nanoscale electrical contacts were made and used to define sub-100 nm Ge/Si channels by controlled solid-state conversion of Ge/Si NWs to NiSixGe y alloys. Electrical transport measurements and modeling studies demonstrate that the nanoscale metallic contacts overcome deleterious short-channel effects present in lithographically defined sub-100 nm channels. Data acquired on 70 and 40 nm channel length Ge/Si NWFETs with a drain-source bias of 0.5 V yield transconductance values of 78 and 91 microS, respectively, and maximum on-currents of 121 and 152 microA. The scaled transconductance and on-current values for a gate and bias voltage window of 0.5 V were 6.2 mS/microm and 2.1 mA/microm, respectively, for the 40 nm device and exceed the best reported values for planar Si and NW p-type FETs. In addition, analysis of the intrinsic switching delay shows that terahertz intrinsic operation speed is possible when channel length is reduced to 70 nm and that an intrinsic delay of 0.5 ps is achievable in our 40 nm device. Comparison of the experimental data with simulations based on a semiclassical, ballistic transport model suggests that these sub-100 nm Ge/Si NWFETs with integrated high-kappa gate dielectric operate near the ballistic limit.     

DC and AC characteristics of sub-50-nm MOSFETs with source/drain-to-gate nonoverlapped structure

A MOSFET structure with a nonoverlapped source/drain (S/D) to gate region was proposed to overcome the challenges in sub-50-nm CMOS devices. Key device characteristics were investigated by extensive simulation study. Fringing gate electric field through the spacer induces an inversion layer in the nonoverlap region to act as an extended S/D region. An oxide spacer is used to reduce parasitic gate overlap capacitance. A reasonable amount of inversion electrons were induced under the spacers. Internal physics, speed characteristics, short channel effects, and RF characteristics were studied with the nonoverlap distance at a fixed metallurgical channel length of 40 nm. The proposed structure had good drain-induced barrier lowering and V/sub T/ rolloff characteristics and showed reasonable intrinsic gate delay and cutoff frequency compared to those of an overlapped structure.     

Toward sub-20 nm hybrid nanofabrication by combining the molecular ruler method and electron beam lithography

It is of great interest and importance to develop new nanofabrication processes to fabricate sub-20 nm structures with sub-2 nm resolution for next-generation nanoelectronic devices. A combination of electron beam lithography (EBL) and a molecular ruler is one of the promising methods to make these fine structures. Here we successfully develop a hybrid method to fabricate sub-20 nm nanogap devices at the desired positions with a complex structure by developing a post-EBL process, which enabled us to avoid damaging the molecular ruler with the high-energy electron beam, and to fully utilize the EBL resolution. It was found that slight etching of the Ti adhesion layer of the parent metal (Pt) by ACT935J solution assisted the removal of molecular rulers, resulting in improved enhancement in the product yield (over 70%) of nanogap devices.     

Quantum behavior of graphene transistors near the scaling limit

The superior intrinsic properties of graphene have been a key research focus for the past few years. However, external components, such as metallic contacts, serve not only as essential probing elements, but also give rise to an effective electron cavity, which can form the basis for new quantum devices. In previous studies, quantum interference effects were demonstrated in graphene heterojunctions formed by a top gate. Here phase coherent transport behavior is demonstrated in a simple two terminal graphene structure with clearly resolved Fabry-Perot oscillations in sub-100 nm devices. By aggressively scaling the channel length down to 50 nm, we study the evolution of the graphene transistor from the channel-dominated diffusive regime to the contact-dominated ballistic regime. Key issues such as the current asymmetry, the question of Fermi level pinning by the contacts, the graphene screening determining the heterojunction barrier width, the scaling of minimum conductivity, and of the on/off current ratio are investigated.     

Fast growth of branched nickel monosilicide nanowires by laser-assisted chemical vapor deposition

Branched nickel monosilicide (NiSi) nanowires (NWs), for the first time, have been synthesized on Ni foams by laser-assisted chemical vapor deposition using disilane precursor molecules. Studies indicate that 600?°C is the threshold temperature for the growth of a large number of branched NiSi NWs with 100-500 nm long branches extending from the main stems. Below the threshold temperature, unbranched NiSi NWs were obtained. The density of the branched NiSi NWs is relatively higher in comparison to that of the unbranched ones. The growth rate of the branched NiSi NWs at 700?°C is estimated up to 10 μm min(-1). High-resolution transmission electron microscopy and energy-dispersive x-ray spectroscopy of the branched NiSi NWs suggest that the formation of these branched nanostructures is ascribed to the Ni-dominant diffusion process. These NiSi NWs with branched nanostructures could bring them new opportunities in nanodevices.     

3-D Monte Carlo Simulation of the Impact of Quantum Confinement Scattering on the Magnitude of Current Fluctuations in Double Gate MOSFETs

For the scaling of ultrathin body double gate (UTB DG) MOSFETs to channel lengths below 10 nm, a silicon body thickness of less than 5 nm is required. At these dimensions the influence of atomic scale roughness at the interface between the silicon body and the gate dielectric becomes significant, producing appreciable body thickness fluctuations. These fluctuations result in a scattering potential related to the quantum confinement variation within the channel which, similarly to the interface roughness scattering, influences the mobility, the drive current and the intrinsic parameter variations. In this paper we have developed an ensemble Monte Carlo simulation approach to study the impact of quantum confinement scattering on the transport in sub-10 nm UTB DG MOSFETs, and the corresponding intrinsic parameter variations. By comparing the Monte Carlo simulations with drift-diffusion simulations we quantify the important contribution of the quantum confinement related scattering to the current fluctuations in such devices     

Au/Ni bilayers on n-type silicon: Metallurgical and electrical behaviour

Diffusion effects during the formation of silicides in the Ni-Au-Si system were investigated by means of ⁴He⁺ MeV Rutherford backscattering spectrometry, Auger electron spectroscopy coupled with Ar⁺ ion sputtering and X-ray diffraction as a function of the heat treatment temperature (280–350°C) and time (10–1000 min). Schottky barrier heights were used to identify the type of metal present at the silicon surface. Au/Ni/Si and Ni/Au/Si structures were prepared by electron gun deposition of thin gold and nickel films onto n-type Si〈111〉 single crystals. After thermal treatment only Ni₂Si and NiSi compounds were observed and their formation follows the phase order confirmed by previous investigations on the Ni/Si system, with a growth controlled by a lattice diffusion process. In the Ni/Au/Si〈111〉 structure the diffusion of the silicon through the gold film was detected during the formation of nickel silicide and the kinetics of growth of Ni₂Si and NiSi were similar to those studied in the Ni/Si〈100〉 system. A diffusion of gold towards the Si-NiSi interface was observed during the growth of NiSi in the Au/Ni/Si〈111〉 structure. The Schottky barrier height measurements confirm these findings.     

Sub-30 nm gate template fabrication for nanoimprint lithography using spacer patterning technology

In this study, we present a spacer patterning technology for sub-30 nm gate template which is used for nano-scale MOSFETs fabrication. A spacer patterning technology using a poly-silicon micro-feature and a chemical vapor deposition (CVD) SiO2 spacer has been developed, and the sub-30 nm structures by conventional dry etching and chemical mechanical polishing are demonstrated. The minimum-sized features are defined not by the photolithography but by the CVD film thickness. Therefore, this technology yields a large-area template with critical dimension of minimum-sized features much smaller than that achieved by optical lithography.     

50-nm fully depleted SOI CMOS technology with HfO/sub 2/ gate dielectric and TiN gate

In this paper, we demonstrate for the first time CMOS thin-film metal gate FDSOI devices using HfO/sub 2/ gate dielectric at the 50-nm physical gate length. Symmetric V/sub T/ is achieved for long-channel nMOS and pMOS devices using midgap TiN single metal gate with undoped channel and high-k dielectric. The devices show excellent performance with a I/sub on/=500 /spl mu/A//spl mu/m and I/sub off/=10 nA//spl mu/m at V/sub DD/=1.2 V for nMOSFET and I/sub on/=212 /spl mu/A//spl mu/m and I/sub off/=44 pA//spl mu/m at V/sub DD/=-1.2 V for pMOSFET, with a CET=30 /spl Aring/ and a gate length of 50 nm. DIBL and SS values as low as 70 mV/V nand 77 mV/dec, respectively, are obtained with a silicon film thickness of 14 nm. Ring oscillators with 15 ps stage delay at V/sub DD/=1.2 V are also realized.