Attenuation mechanisms of aluminum millimeter-wave coplanar waveguides on silicon

The loss mechanisms of silicon coplanar waveguides (CPW) with aluminum metallization are investigated up to 40 GHz. Three main parts contribute to the attenuation of coplanar waveguides (CPWs): the frequency-dependent conductor losses of the metallization, frequency-independent substrate losses, and the specifically investigated bias-dependent interface losses caused by free charges at the Si-SiO/sub 2/ interface. The minimum losses found in 50-/spl Omega/ CPWs with 45-/spl mu/m signal line width were 0.19 db/mm at 10 GHz and 0.33 dB/mm at 40 GHz. High-purity silicon from a float zone (FZ) process was used as substrate. Substrates with lower purity from a Czochralski (CZ) process (resistivity 50-100 /spl Omega/cm) resulted in somewhat higher (0.2-0.3 dB/mm) losses for the same CPW geometry.     

Fabrication and Characterization of Coplanar Waveguides on Silicon Using a Combination of SiO $_{2}$ and SRO $_{20}$

In this work, the use of silicon rich oxide (SRO) and chemical vapor deposition SiO$_{2}$ double layers as passivation films of coplanar waveguides (CPW) on high resistivity silicon (HR-Si) with an ${hbox{N}}^{+}$ backside is studied. The microwave performance of the fabricated CPWs is evaluated by computing the attenuation loss of the devices in the 0.045–50 GHz frequency range. Experimental results show that the ${hbox{N}}^{+}$ layer can be used without affecting CPW performance. Also, using a combined dielectric layer (SRO$_{20}$ /SiO$_{2}$ ), the attenuation losses are reduced compared to single dielectric layers.      

High frequency electrical circuits on a planar lightwave circuitplatform

We investigated the propagation losses and the characteristic impedances Z_L of coplanar waveguides (CPWs) and microstrip lines (MSLs) on a planar lightwave circuit (PLC)-platform formed on a silica/silicon substrate. The loss of the CPWs was 2.7 dB/cm at 10 GHz on the PLC-platform with 30 μm thick silica layer. Thus, a cm-order circuit of this CPW is difficult to fabricate in the 10 Gb/s module. This is because the silicon substrate has a large loss tangent (tan δ). On the other hand, the loss of the MSLs, where a ground plane shielded the high loss silicon substrate, could be improved to 0.9 dB/cm at 10 GHz with 30 μm thick polyimide. These lower loss MSLs on a PLC-platform can be applied to module operation at 10 Gb/s. Furthermore they have the advantage that they are suitable for application to array device circuits or circuits in a module where several devices are integrated because unlike CPWs the ground planes are not divided by signal lines or DC bias lines. The structure of CPWs and MSLs on a PLC-platform with a Z_L of 50 Ω was also studied in detail     

Low-loss coplanar waveguides interconnects on low-resistivity silicon substrate

This paper describes fabrication, characterization and simulation of low-loss coplanar waveguide (CPW) interconnects on low-resistivity silicon substrate. The fabrication of CPWs is low-temperature (below 250/spl deg/C) and incorporates a spin-on low-k dielectric benzocyclobutene (BCB) and self-aligned electroplating of copper. The performance of CPWs is evaluated by high-frequency characterization and EM simulation. CPWs with different line width (W) and line spacing (S) are investigated and compared. Using a BCB layer as thick as 20 /spl mu/m, CPW fabricated on a low-resistivity silicon substrate exhibits an insertion loss of 3 dB/cm at 30 GHz.     

Surface property of passivation layer on integrated circuit chip and solder mask layer on printed circuit board

Adhesion of underfill to passivation layer on integrated circuit chip and solder mask layer on printed circuit board is critical to the reliability of an underfilled flip chip package. In this study, the surface properties of solder mask and four passivation materials: benzocyclobutene (BCB), polyimide (PI), silicon dioxide (SiO/sub 2/), and silicon nitride (SiN) were investigated. A combination of both wet and dry cleaning processes was very effective to remove contaminants from the surface. The element oxygen, introduced during O/sub 2/ plasma treatment or UV/O/sub 3/ treatment, led to the increase of the base component of surface tension. X-ray photoelectron spectroscopy (XPS) experiments confirmed the increase of oxygen concentration at the surface after UV/O/sub 3/ treatment. Wetting of underfill on passivation and solder mask was slightly improved at higher temperatures. Although UV/O/sub 3/ cleaning and O/sub 2/ plasma treatment significantly improved the wetting of underfill on passivation materials, they did not improve adhesion strength of epoxy underfill to passivation. Therefore, the wetting was not the controlling factor in adhesion of the system studied.     

在高阻硅衬底上制备低微波损耗的共面波导

分别在普通的低阻硅衬底、带有3μm厚氧化硅介质层的低阻硅衬底和高阻硅衬底上设计并制备了微波传输共面波导.结果表明,低阻硅衬底导致过高的微波损耗从而不能使用,通过加氧化硅介质层,微波损耗可以大大减少,但是需要较厚的氧化硅厚度.直接制备在高阻硅衬底上的共面波导在所测试的26GHz的频率范围内获得低于2dB/cm的微波损耗,而且工艺十分简单.     

Impact of light illumination and passivation layer on siliconfinite-ground coplanar-waveguide transmission-line properties

The modeling of silicon finite-ground coplanar-waveguide (FGCPW) transmission lines is presented in this paper. It is shown that the effective substrate conductivity increases in the presence of illumination and in the presence of a passivation layer in the slot regions independently. As a result, the losses of trenched FGCPW are lower than conventional FGCPW transmission lines. The strong dependence of the substrate conductivity on illumination suggests that optically controlled attenuators can be implemented with FGCPW transmission lines exhibiting practically no phase change between the different attenuation states. A new contrast ratio for optically controlled transmission lines is derived     

A long-refresh dynamic/quasi-nonvolatile memory device with 2-nmtunneling oxide

A memory device using silicon rich oxide (SRO) as the charge trapping layer for dynamic or quasi-nonvolatile memory application is proposed. The device achieved write and erase speed at low voltage comparable to that of a dynamic-random-access memory (DRAM) cell with a much longer data retention time. This device has a SRO charge trapping layer on top of a very thin tunneling oxide (<2 nm). Using the traps in the SRO layer for charge storage, a symmetrical write/erase characteristics were achieved. This new SRO cell has an erase time much shorter than values of similar devices reported in the literature     

Impact of neutron irradiation on the RF properties of oxidized high-resistivity silicon substrates with and without a trap-rich passivation layer

This work investigates the influence of high-energy neutrons on oxidized high-resistivity silicon substrates (HR-Si). Two oxide thicknesses as well as the presence of a trap-rich passivation layer are considered. The impact of neutron irradiation is directly related to the competition between the generation of interface traps added to the mobility and carrier lifetime degradation, which are beneficial to reduce parasitic surface conduction (PCS) into the Si substrate similarly to the passivation layer, and accumulation of radiation-induced positive charges in oxide, which would unfortunately increase PSC. It is shown that under neutron irradiation, RF losses are strongly reduced in the case of thin oxide (t_ox = 50 nm), while substrates with a polysilicon passivation layer are almost insensitive to the neutron irradiation.     

Textured silicon surface passivation by high‐rate expanding thermal plasma deposited SiN and thermal SiO2/SiN stacks for crystalline silicon solar cells

Expanding thermal plasma (ETP) deposited silicon nitride (SiN) with optical properties suited for the use as antireflection coating (ARC) on silicon solar cells has been used as passivation layer on textured monocrystalline silicon wafers. The surface passivation behavior of these high‐rate (>5 nm/s) deposited SiN films has been investigated for single layer passivation schemes and for thermal SiO₂/SiN stack systems before and after a thermal treatment that is normally used for contact‐firing. It is shown that as‐deposited ETP SiN used as a single passivation layer almost matches the performance of a thermal oxide. Furthermore, the SiN passivation behavior improves after a contact‐firing step, while the thermal oxide passivation degrades which makes ETP SiN a better alternative for single passivation layer schemes in combination with a contact‐firing step. Moreover, using the ETP SiN as a part of a thermal SiO₂/SiN stack proves to be the best alternative by realizing very low dark saturation current densities of <20 fA/cm² on textured solar‐grade FZ silicon wafers and this is further improved to <10 fA/cm² after the anneal step. Optical and electrical film characterizations have also been carried out on these SiN layers in order to study the behavior of the SiN before and after the thermal treatment. Copyright © 2008 John Wiley & Sons, Ltd.     

Characterization and attenuation mechanism of CMOS-compatible micromachined edge-suspended coplanar waveguides on low-resistivity silicon substrate

This paper presents detailed characterization of a category of edge-suspended coplanar waveguides that were fabricated on low-resistivity silicon substrates using improved CMOS-compatible micromachining techniques. The edge-suspended structure is proposed to provide reduced substrate loss and strong mechanical support at the same time. It is revealed that, at radio or microwave frequencies, the electromagnetic waves are highly concentrated along the edges of the signal line. Removing the silicon underneath the edges of the signal line, along with the silicon between the signal and ground lines, can effectively reduce the substrate coupling and loss. The edge-suspended structure has been implemented by a combination of deep reactive ion etching and anisotropic wet etching. Compared to the conventional silicon-based coplanar waveguides, which show an insertion loss of 2.5dB/mm, the loss of edge-suspended coplanar waveguides with the same dimensions is reduced to as low as 0.5 dB/mm and a much reduced attenuation per wavelength (dB//spl lambda//sub g/) at 39 GHz. Most importantly, the edge-suspended coplanar waveguides feature strong mechanical support provided by the silicon remaining underneath the center of the signal line. The performance of the coplanar waveguides is evaluated by high-frequency measurement and full-wave electromagnetic (EM) simulation. In addition, the resistance, inductance, conductance, capacitance (RLGC) line parameters and the propagation constant of the coplanar waveguides (CPWs) were extracted and analyzed.     

Surface-passivated high-resistivity silicon substrates for RFICs

Surface passivation of high-resistivity silicon (HRS) by amorphous silicon thin-film deposition is demonstrated as a novel technique for establishing HRS as a microwave substrate. Metal-oxide-silicon (MOS) capacitor measurements are used to characterize the silicon surface properties. An increase of the quality factor (Q) of a 10-nH spiral inductor by 40% to Q=15 and a 6.5-dB lower attenuation of a coplanar waveguide (CPW) at 17 GHz indicate the beneficial effect of the surface passivation for radio frequency (RF) and microwave applications. Regarding CPW attenuation, a nonpassivated 3000-/spl Omega//spl middot/cm substrate is equivalent to a 70-/spl Omega//spl middot/cm passivated substrate. Surface-passivated HRS, having minimum losses, a high permittivity, and a high thermal conductivity, qualifies as a close-to-ideal radio frequency and microwave substrate.     

Propagation characteristics of MIS transmission lines withinhomogeneous doping profile

The authors present a hybrid-mode analysis of slow-wave MIS (metal-insulator-semiconductor) transmission lines with a gradually inhomogeneous doping profile. In general it was found that, in comparison with homogeneously doped semiconductor layers, a Gaussian-type doping distribution results in lower losses for the slow-wave mode in both thin- and thick-film MIS CPWs. While the effect of the doping profile is more pronounced in thin-film structures which support a slow-wave mode only up to 3 GHz, it is less significant in thick-film structures. On the other hand, numerical analysis indicates that thick-film structures can support a slow-wave mode at moderate loss up to 40 GHz. The behavior of MIS microstrip lines is similar to that of MIS CPWs, except that for thick-film transmission lines an increase in losses can be observed when the doping profile becomes inhomogeneous. The numerical investigation was carried out using the method of lines. Several transmission lines have been investigated, and results are presented for microstrip, coupled microstrips, and coplanar lines     

Wafer-level packaging technology for high-Q on-chip inductors and transmission lines

In the current trend toward portable applications, high-Q integrated inductors have gained considerable importance. Hence, much effort has been spent to increase the performance of on-chip Si inductors. In this paper, wafer-level packaging (WLP) techniques have been used to integrate state-of-the-art high-Q on-chip inductors on top of a five-levels-of-metal Cu damascene back-end of line (BEOL) silicon process using 20-/spl Omega//spl middot/cm Si wafers. The inductors are realized above passivation using thick post-processed low-K dielectric benzocyclobutene (BCB) and Cu layers. For a BCB-Cu thickness of 16 /spl mu/m/10 /spl mu/m, a peak single-ended Q factor of 38 at 4.7 GHz has been measured for a 1-nH inductor with a resonance frequency of 28 GHz. Removing substrate contacts slightly increases the performance, though a more significant improvement has been obtained by combining post-processed passives with patterned ground shields: for a 2.3-nH above integrated-circuit (above-IC) inductor, a 115% increase in Q/sub BW//sup max/ (37.5 versus 17.5) and a 192% increase in resonance frequency (F/sub res/: 12 GHz versus 5 GHz) have been obtained as compared to the equivalent BEOL realization with a patterned ground shield. Next to inductors, high-quality on-chip transmission lines may be realized in the WLP layers. Losses below -0.2 dB/mm at 25 GHz have been measured for 50-/spl Omega/ post-processed coplanar-waveguide lines, above-IC thin-film microstrip lines have measured losses below -0.12 dB/mm at 25 GHz.     

Influence of temperature and humidity on adhesion of underfills for flip chip packaging

This paper systematically discusses the influence of temperature and humidity on the adhesion performance of underfill material (epoxy cured with acid anhydride), which was evaluated by die shear test after exposure to various conditions. The inherent adhesion strength between the underfill and passivation is not affected significantly by thermal cycling between -55/spl deg/C and 125/spl deg/C for 1000 cycles. The adhesion strength of underfill material decreases with the increase of test temperature in the investigated range, due to the decrease of modulus of the underfill with the increase of temperature. A sharp decrease in adhesion strength occurs as temperature increases toward the glass transition temperature of the underfill material. Adhesion strength of underfill with different passivation materials decreases after aging in a high temperature and high humidity environment. The extent of the decrease depends on underfill formulation and the hydrophilicity of the passivation material. Hydrophilic passivation such silicon oxide (SiO/sub 2/) and silicon nitride (Si/sub 3/N/sub 4/) shows much more severe adhesion degradation than hydrophobic passivation such as benzocyclobutene (BCB) and polyimide (PI). Adhesion degradation is slower than moisture diffusion. The adhesion stability for hydrophilic passivation can be successfully improved by use of a coupling agent such as silane that introduces stable chemical bonds at interface.     

Si/SiO_2系统电荷对高阻硅基CPW传输损耗的影响

通过高频C-V测试得到实验制备的共平面波导(CPW)下方的Si/SiO2系统电荷主要表现为正电荷,其密度约为4.8×1010/cm2。三种不同衬底上50Ω共平面波导分别为直接制备于高阻硅上、高阻硅氧化层上、去除信号线与地线间的高阻硅氧化层上。20GHz时,测得上述三种CPW的微波传输损耗分别为-0.88dB、-2.50dB及-1.06dB,因此去除线间氧化层使得传输线损耗降低了1.44dB。此外还测试了高阻硅氧化层和除去线间氧化层的高阻硅氧化层上的两种CPW的传输损耗随外加偏压的变化。     

色散效应对钝化硅太阳电池减反射膜系设计的影响

在考虑折射率色散效应基础上,以加权平均反射率作为评价函数,通过智能优化算法对空间硅太阳电池减反射膜进行优化设计,得到了最佳的膜厚参数,并与不考虑色散下设计的减反射膜进行了比较。对MgF2/TiO2,SiO2/TiO2双层减反射膜,与不考虑色散情形相比,考虑色散下优化后的最小加权平均反射率分别减小了36.6%和37.6%;对具有厚度为15 nm的SiO2钝化层的硅太阳电池的MgF2/TiO2,SiO2/TiO2减反射膜重新优化设计,与不考虑色散情形相比,考虑色散下优化后的最小加权平均反射率分别减小了43.9%和33.7%;对具有不同厚度钝化层的空间硅太阳电池,在考虑色散下进行了减反射膜的优化设计。结果发现,随着钝化层厚度的增加,所得减反射膜的最小加权平均反射率也随之增大,减反射效果越来越弱。最后,在考虑与未考虑色散情形下,将钝化层膜厚也作为反演参量后重新设计。结果表明:在色散情形下所设计的减反射膜更佳,对于MgF2/TiO2/SiO2（钝化层）膜系,最佳膜厚参量为d1（MgF2）=97.6 nm,d2（TiO2）=40.2 nm,d3（SiO2）=4.9 nm;对于SiO2/TiO2/SiO2（钝化层）,最佳膜厚参量为d1（SiO2）=85.1 nm,d2（TiO2）=43.4 nm,d3（SiO2）=1.8 nm。     

Stability of sulfur-passivated facets of InGaAs-AlGaAs laser diodes

The facets of GaAs-AlGaAs ridge waveguide (RW) laser diodes were passivated using (NH/sub 4/)/sub 2/S/sub x/. The effectiveness of this procedure was checked by electroluminescence power-voltage-current (P-V-I) measurements that provide information on the changes in the density of surface states. Using this nondestructive method, the degradation of the passivation under ambient atmosphere has been studied. Capping with silicon nitride is found to stabilize the sulfur passivation and avoid degradation.     

Characteristics of smooth and periodic HTS coplanar resonators on ferroelectric/dielectric substrates

Characteristics of smooth and periodic (consisting of sections with different dimensions) high temperature superconducting (HTS) thin film coplanar waveguide (CPW) resonators with a ferroelectric component were calculated. Frequency tunability and microwave (MW) losses of the structure were analyzed using the obtained formulas. It was shown that for the ferroelectric layer thickness less than 100 nm, the MW losses are determined by the losses of HTS electrodes, while for thicker layers, the MW losses are completely determined by the loss tangent of the ferroelectric. Experimental aspects of the problem were investigated in the example of a YBCO/Ba/sub x/Sr/sub 1-x/TiO/sub 3/ smooth CPW resonator at 77 K and information about the permittivity and the loss tangent of the ferroelectric was obtained.     

Flexible AM OLED panel driven by bottom-contact OTFTs

Active matrix organic-light-emitting-diode (AM OLED) panels, driven by organic thin-film transistors (OTFT), have been successfully fabricated on a flexible plastic substrate. The pixel circuit consists of two bottom-contact pentacene OTFTs working as switching and driving transistors. The panel has 16 /spl times/ 16 pixels, each of which have an OLED using a phosphorescent material with an emission efficiency of 30 cd/A. A tantalum oxide (Ta/sub 2/O/sub 5/) film with a dielectric constant of 24, prepared by the anodization of Tantalum (Ta), was used as the gate insulator of the OTFTs. The passivation layer on the OTFTs was formed by a layer of silicon dioxide (SiO/sub 2/) and two layers of polyvinyl alcohol. Using OTFTs with a Ta/sub 2/O/sub 5/ gate insulator, the authors have realized a flexible active matrix OLED panel driven with a low voltage of -12 V.