热处理对钽芯及钽电容器电性能的影响北大核心CSCD

在实际使用过程中,钽电容器常因电容量、损耗和漏电流发生漂移而失效。为了改善钽电容器的电性能稳定性,系统研究了在空气环境中热处理对形成后的钽芯及钽电容器电性能的影响。采用阳极氧化法在烧结后的钽块表面形成Ta_(2)O_(5)介质氧化膜,然后对阳极钽芯进行热处理。研究结果表明:热处理对钽芯的击穿电压和漏电流传导机理无明显影响;热处理后的钽芯表面Ta_(2)O_(5)介质氧化膜的微观形貌未发生明显变化;经过适当热处理且补形成后的阳极钽芯的漏电流及所制备的钽电容器电容量稳定性、损耗和漏电流均得到了明显改善;合适的热处理工艺为300℃/45~60 min。     

氧化膜强化技术在钽电容器生产中的应用

采用氧化膜强化技术在钽阳极体外表面形成抗机械应力的强化氧化膜,并模拟钽电容器回流焊过程,研究回流焊前后钽电容器漏电流变化以及对击穿电压(BDV)的影响。试验结果显示:在回流焊安装前后,应用氧化膜强化技术的电容器漏电流增幅小于普通产品14%;耐BDV比普通产品高6 V。     

合理利用钽粉制造系列钽电容器

国内电容器生产厂家在制造钽电容器时，通常是根据钽电容器的工作电压来选择对应电压的国产钽粉的。本文以九○五厂生产的ＦＴＷ１２０钽粉为例，通过改变烧结条件的实验，生产出不同工作电压系列的产品，来论述使用同一种规格的钽粉制造不同工作电压的电容器。这样既方便于电容器的生产组织和管理，同对，也利于钽粉制造厂稳定工艺，提高技术。文中给出了电容量－烧结温度曲线。     

钽阳极氧化膜(Ta-Ta_2O_5)的热处理

<正> 近年来,国内对固体电解质烧结钽电容器的工艺研究开展得很活跃。对二氧化锰被覆工艺的探讨,有了新的突破;高比容钽粉正在推广使用,在研究降低漏电流方面也取得了一定进展。本文将分析钽阳极氧化膜的热处理对漏电流的影响。 可靠性实验已经证阴,固体钽电解电容器的主要失效模式是漏电流增大。其表现形式有两种:一是漏电流增大,在极短的时间     

钽电解电容器的耐久性试验

钽电解电容器具有阻抗低、漏电流小、高频特性好、可靠性高等特点，而耐久性试验是对电容器产品综合性能最严峻的考验。介绍了钽电解电容器耐久性试验的方法、注意事项和失效分析技术。     

有机电解质片式钽电容器稳定性的提高

新一代信息技术的发展不仅要求有机固体电解质片式钽电容器的等效串联电阻(ESR)小,更需要在严酷环境中使用时电容量、ESR和漏电流保持稳定。影响钽电容器稳定性的影响因素很多,其中界面稳定性是关键因素之一。为此,在此类电容器生产中引入一种新的界面预处理方法,即在介质氧化膜表面涂敷硅烷偶联剂预涂层,抑制介质氧化膜-聚合物界面的劣化。经过高低温、浪涌电压和125℃-2000 h寿命测试,静电容量、漏电流和ESR的稳定性有明显改善。试验结果表明,该界面预处理技术是制造高稳定性高压有机钽电容器非常有效的方法。     

钽粉氧含量对其钽阳极漏电流的影响

在多年实践经验基础上，用氧含量Ｘ１（质量分数）０．２０％～０．３８％的四种钽粉，控制钽阳极中残余氧含量Ｘ２（质量分数）在０．０８％～０．２０％间，采用正交设计实验研究了对其漏电流的影响，并建立了漏电流峰值ＩＬ和Ｘ１、Ｘ２间的预示方程，描述了漏电流和钽粉氧含量（Ｘ１）、残余氧含量（Ｘ２）间的关系。随后，用预示方程讨论了钽中氧和钽阳极中残余氧对其漏电流的影响。     

正确使用钽电容器

使用钽电容器时应注意电气、气候、组装和机械、存储等方面的条件。任何一方面的条件不合适，都可能造成短路、漏电流增大等问题。 1 工作电压 电压降额幅度应尽可能大。在常规条件下，工作电压（含纹波电压）Vo应降至额定电压Vr的50%以下，建议降至30%，尤其是用于低阻抗电路时。 用于开关电路、充-放电电路或其他瞬间电流电路时，建议降至30%以下，串联一只电阻器，将电流限制在300 mA 以下。 当环境温度t超过85℃时，建议工作电压不要超过图1所示的范围。 2 纹波电流与纹波电压 2.1 纹波电流 若施加在钽电容器上的纹波电流Im…     

提高高压MnO2钽电容器漏电流稳定性的试验研究

高压MnO₂钽电容器漏电流在高温和高压应用环境中的稳定性对电路的安全性和可靠性有重要影响。通过正反向偏置V-I特性测试可知，高压MnO₂钽电容器漏电流主要为氧空位缺陷和介质表面的微晶诱发的Poole-Frenkel电流和隧穿电流。在Ta₂O₅介质表面通过浸渍的方法涂覆一层绝缘树脂阻挡层，以提高界面的势垒和Poole-Frenkel电阻，屏蔽介质表面的晶化点，且抑制氧空位缺陷和晶化点在高温和高场环境应用过程中的互作用。浪涌电流/电压冲击、高低温稳定性、加速121℃-85%RH-63 h和125℃-2000 h寿命测试表明，漏电流在高温和高压环境中的稳定性明显改善，电容器的可靠性和稳定性显著提高。该研究对电子装备系统在严酷环境中的安全可靠运行具有重要的支撑作用。     

CA型固体钽电容器的老化筛选方法

ＣＡ型固体钽电容器是重要的电子元件，为淘汰早期失效产品，确保高的可靠性水平，采用合适的筛选方法十分必要。介绍了：１．敲击漏电流闪变筛选；２．电参数性能测量筛选；３．温度循环筛选；４．高温电负荷老化筛选；５．高温浪涌电压老化筛选；６．高温漏电流老化筛选；７．密封检验筛选。筛选效果最明显的是４、６两项     

Reliability studies of MOCVD TiSiN and EnCoRe Ta(N)/Ta

Passivated single damascene copper SiO₂ damascene lines were evaluated in combination with TiSiN and Ta(N)/Ta diffusion barriers. Leakage current, breakdown and time-dependent dielectric breakdown properties were investigated on a wafer level basis for temperatures ranging between room temperature and 150 °C. It is found that the leakage performance of the wafers with a TiSiN barrier is better at room temperature, but at 150 °C the performance levels out with Ta(N)/Ta. Time-dependent dielectric breakdown measurements at 150 °C show that the lifetime of the interconnect is higher with the selected Ta(N)/Ta barrier than for TiSiN.     

A new gate current extraction technique for measurement of on-statebreakdown voltage in HEMTs

We present a new simple three-terminal technique for measuring the on-state breakdown voltage in HEMTs. The gate current extraction technique involves grounding the source, and extracting a constant current from the gate. The drain current is then ramped from the off-state to the on-state, and the locus of drain voltage is measured. This locus of drain current versus drain voltage provides a simple, unambiguous definition of the on-state breakdown voltage which is consistent with the accepted definition of off-state breakdown. The technique is relatively safe and repeatable so that temperature dependent measurements of on-state breakdown can be carried out. This helps illuminate the physics of both off-state and on-state breakdown     

Improvement of breakdown voltage in SOI n-MOSFETs using thegate-recessed (GR) structure

A gate-recessed structure is introduced to SOI MOSFETs in order to increase the source-to-drain breakdown voltage. A significant increase in the breakdown voltage can be seen compared with that of a planar single source/drain SOI MOSFET without inducing the appreciable reduction of the current drivability. We have analyzed the origin of the breakdown voltage improvement by the substrate current measurements and 2-D device simulations, and shown that the breakdown voltage improvement is caused by the reductions in the impact ionization rate and the parasitic bipolar current gain     

基于双极载流子导电的新型恒流器件

提出了一种基于双极载流子导电、具有低开启电压VK和高反向击穿电压BVR的恒流器件,并进行了初步的试验验证。利用Tsuprem4和Medici仿真工具对器件的恒定电流IS、开启电压VK、正向击穿电压BVF和反向击穿电压BVR等电学参数进行了仿真,优化了外延层电阻率ρepi、外延层厚度Tepi、JFET注入剂量DJFET、P-well注入窗口间距WJFET等参数。试验结果显示,该器件工作于正向时,开启电压VK约为1.6 V,恒定电流IS约为31 mA,正向击穿电压BVF为55 V;该器件工作在反向时,反向击穿电压BVR约为200 V。     

Breakdown behavior of GaAs/AlGaAs HBTs

Avalanche breakdown behavior at the collector junction of the GaAs/AlGaAs HBT (heterojunction bipolar transistor) has been studied. Junction breakdown characteristics displaying hard breakdown, soft breakdown, and negative resistance breakdown behavior were observed and are interpreted by analysis of localized microplasma effects, uniform microplasma-free behavior, and associated current gain measurements. Light emission from the collector-base junction of the GaAs/AlGaAs HBT was observed and used to investigate breakdown uniformity. Using a simple punchthrough breakdown model, the theoretical breakdown curves at different collector doping concentrations and thicknesses were computed and found to be in agreement with maximum breakdown voltages measured from devices displaying the most uniform junction breakdown. The serious current gain degradation of GaAs/AlGaAs HBTs at low current densities was analyzed in connection with the measurement of a large collector-emitter breakdown voltage. The unexpected functional relationship between the collector-emitter breakdown voltage and collector-base breakdown voltage is explained by the absence of a hole-feedback effect for devices not exhibiting transistor action     

Ultrahigh-power picosecond current switching by a silicon sharpener based on successive breakdown of structures

Ultrafast current switching by a silicon sharpener based on successive breakdown of structures has been experimentally implemented and theoretically studied. A voltage pulse with an amplitude of 180 kV and a rise time of 400 ps was applied to a semiconductor device containing 44 series-connected diode structures positioned in a 50-Ω transmission line. After device switching, pulses with an amplitude of 150 kV and a rise time of 100 ps were obtained in the transmission line. Numerical simulation showed that the electric field near the p-n junction reaches the Zener breakdown threshold (∼10⁶ V/cm) at an input voltage rise rate of more than 4 × 10¹³ V/s per structure achieved in the experiment, even when the diode structure contains technological impurities with deep ionization levels and a concentration of 10¹¹ cm⁻³.     

SIPOS钝化功率晶体管“双线击穿”曲线现象的分析

测试半绝缘掺氧多晶硅(SIPOS)层钝化的功率晶体管管芯反向击穿电压曲线时,出现异常击穿曲线--"双线击穿"曲线现象.通过对SIPOS钝化的功率晶体管管芯进行逐层腐蚀,再进行反向击穿曲线测试,以及扫描电镜对SIPOS层结构进行能谱分析,结果显示SIPOS层中氧含量过大,从而产生界面效应造成击穿电压回移,并解释了在应用特定测试仪器测试时显示出"双线击穿曲线"的现象.同时提出解决双线击穿曲线现象的方法.     

A physically-based MOS transistor avalanche breakdown model

A physically based breakdown model for MOSFET's is presented to rectify the unexplained experimental breakdown behaviors. The drain avalanche breakdown in the MOS transistor can be caused by either infinite multiplication (MI) or finite multiplication with positive feedback of the substrate current (MF) due to the impact ionization in the pinch-off region. The breakdown voltages of these two modes of breakdown have different dependencies on the biasing conditions and device parameters. For MI mode of breakdown, the breakdown voltage increases slowly with the gate voltage and can be approximated by the drain saturation voltage plus a constant offset. For MF mode of breakdown, the breakdown voltage decreases as the drain saturation current becomes larger. The calculated breakdown characteristics agree well with the measured ones for devices with effective channel length in the range of 0.44~10 μm     

Off-state breakdown and leakage current transport analysis of AlGaN/GaN high electron mobility transistors

Off-state breakdown characteristics of AlGaN/GaN high-electron-mobility transistors have been studied based on drain current injection method. It is found that at low drain current injection level, the observed premature breakdown is caused by excess gate-to-drain leakage current. Nevertheless, at high drain injection current level, buffer-leakage-dominated breakdown proceeds gate-leakage-dominated breakdown as the gate bias increases from pinch-off voltage to deep-depletion voltage. In both breakdown regions, the breakdown voltages show negative temperature coefficients. The buffer-leakage-induced breakdown should be defect-related, which is confirmed by temperature-dependent buffer leakage measurements.     

氟掺杂对非晶硅薄膜特性的影响

采用电容结构研究了氟(F,Flourine)掺杂非晶薄膜漏电、击穿以及温度特性。结果表明,氟掺杂钝化了非晶膜中的缺陷和悬挂键,使非晶薄膜漏电降低两个数量级,同时使击穿电压升高。掺杂非晶薄膜的漏电与温度呈指数增长,增长系数为0.0375 K^-1,击穿电压随温度线性减小,系数为0.012 V·K^-1。