锗硅异质结双极器件单粒子效应与加固技术研究进展

锗硅异质结双极晶体管(Silicon-Germanium Heterojunction Bipolar Transistors, SiGe HBT)具有高速、高增益、低噪声、易集成等多种优势,广泛应用于高性能模拟与混合信号集成电路。同时,基区能带工程带来的优异低温特性以及良好的抗总剂量、抗位移损伤能力使其拥有巨大的空间极端环境应用潜力。然而,SiGe HBT固有的器件结构使其对单粒子效应极为敏感,并严重制约了SiGe电路综合抗辐射能力的提升。针对上述问题,综述了SiGe HBT单粒子效应及加固技术的研究进展,详细阐述了SiGe HBT单粒子效应的基本原理,分析了影响单粒子效应敏感性的关键因素,并对比了典型加固方法取得的效果,从而为抗辐射SiGe工艺开发和电路设计提供参考。     

抗辐射电子学研究综述

抗辐射电子学是一门交叉性、综合性的学科,其研究的辐射效应规律、损伤作用机制、加固设计方法、试验测试方法、建模仿真方法等对极端恶劣环境中的电子系统的可靠工作至关重要。对核爆炸中子、γ和X射线,空间和大气高能粒子产生的各种损伤效应(如瞬时剂量率效应、总剂量效应、单粒子效应、位移效应等)的研究现状进行了系统梳理。对辐射之间、辐射和环境应力之间的协同损伤效应(如长期原子迁移对瞬时剂量率感生光电流的影响,中子和γ射线同时辐照与序贯辐照、单因素辐照的损伤差异,质子和X射线、中子辐照的损伤差异,γ射线辐照与环境氢气的协同损伤效应等)的研究进展进行了详细介绍。阐述了国内外在核爆、空间和大气辐射加固研究方面的最新技术进展。总结了国内外在地面实验室对空间、大气或核爆辐射各种效应进行试验模拟和建模仿真的相关能力。最后对21世纪20年代以后抗辐射电子学研究领域潜在的挑战和关键技术进行了展望。     

功率VDMOSFET单粒子效应研究

阐述了空间辐射环境下n沟功率VDMOSFET发生单粒子栅穿(SEGR)和单粒子烧毁(SEB)的物理机理。研究了多层缓冲局部屏蔽抗单粒子辐射的功率VDMOSFET新结构及相应硅栅制作新工艺。通过对所研制的漏源击穿电压分别为65V和112V两种n沟功率VDMOS-FET器件样品进行锎源252Cf单粒子模拟辐射实验,研究了新技术VDMOSFET的单粒子辐射敏感性。实验结果表明,两种器件样品在锎源单粒子模拟辐射实验中的漏源安全电压分别达到61V和110V,验证了新结构和新工艺在提高功率VDMOSFET抗单粒子效应方面的有效性。     

DSP处理器单粒子翻转率测试系统的研制

航天器及其内部元器件在太空中会受到单粒子效应(SEE)带来的威胁,因此航天用电子器件在装备前必须进行抗SEE能力的测试评估。针对传统测试方法存在的测试系统程序容易在辐照过程崩溃、统计翻转数不准确、单粒子闩锁(SEL)辨别不清晰和忽略内核翻转统计等问题,设计了一种测试系统,通过片外加载与运行程序从而减少因辐照导致片内程序异常的现象;通过片外主控电路统计被测电路翻转数使统计翻转结果准确;通过主控电路控制被测电路时钟供给排除因频率增加导致电流过大而误判发生SEL的情况;通过内核指令集统计内核翻转数。实验结果表明,该测试系统可以实时全面地监测数字信号处理器(DSP)的SEE,并有效防止辐照实验器件(DUT)因SEL而失效。     

星载环境下可重构技术分析

针对卫星在宇宙空间运行易受到各种高能粒子辐射,产生的单粒子现象会影响卫星正常工作的问题,通过总结传统的抗单粒子效应的几种方法、可重构技术的发展与分类,分析研究了星载可重构系统设计方法用来抗空间环境辐射效应。通过硬件平台的动态重构可以有效克服单粒子效应的影响,实现远程故障维修、硬件可升级、可靠性提高和成本降低等目标。     

辐照加固SRAM型FPGA总剂量辐射效应研究

在航天辐射环境中,电离辐射产生的辐射效应会对电子元器件性能产生影响。文章对自主研发的SRAM型FPGA芯片在60Co-γ源辐照下的总剂量辐射效应进行了研究。实验表明:(1)总剂量累积到一定程度后功耗电流线性增大,但只要功耗电流在极限范围内,FPGA仍能正常工作;(2)SRAM型FPGA在配置过程中需要瞬间大电流,故辐照后不能立即配置;(3)总剂量辐照实验时,功耗电流能直观反映器件随总剂量的变化关系,可作为判断器件失效的一个敏感参数。该研究为FPGA的设计提供了基础。     

Methods for the Prediction of Total-Dose Effects on Modern Integrated Semiconductor Devices in Space: A Review

Ionizing-radiation effects on space microelectronics are addressed. Major approaches to the radiation-hardness evaluation of IC components in terms of total-dose effects at low dose rates are reviewed. The main mechanisms and kinetic models of radiation degradation are discussed from the standpoint of the prediction of IC radiation response.     

自由空间用半导体激光器抗辐射的研究

为了提高半导体激光器的抗辐射性能,满足空间应用的需要,在介绍了空间辐射环境的基础上,对空间辐射在半导体激光器中产生的总剂量效应、单粒子翻转效应和位移效应进行了分析,并探讨了半导体激光器在空间辐射环境中相应的抗辐射防护技术。对980 nm单模半导体激光器采用了端面镀膜、Al2O3绝缘介质层、真空封装等抗辐射的改进措施,有效地提高了半导体激光器的抗辐射能力。     

一种高温单粒子效应测试系统的设计与实现

航天器件在空间环境中存在着单粒子效应,根据研究可知高温会提升单粒子效应的敏感性,因此为了更好地评估器件的抗辐射性能,有必要建立一套高温单粒子效应测试系统.通过建立高温单粒子效应测试系统,选择ASIC和SRAM进行高温测试实验,完成了电路高温下的单粒子效应检测,证明了温度提升单粒子效应敏感性的事实.     

Radiation effects on microelectronics in space

The basic mechanisms of space radiation effects on microelectronics are reviewed. Topics discussed include the effects of displacement damage and ionizing radiation on devices and circuits, single-event phenomena, dose enhancement, radiation effects on optoelectronic devices and passive components, hardening approaches, and simulation of the space radiation environment. A summary of damage mechanisms that can cause temporary or permanent failure of devices and circuits operating in space is presented     

Radiation testing of semiconductor devices for space electronics

Radiation effects testing, part selection, and hardness assurance for application to electronic components in the natural space environment are discussed. The emphasis is on semiconductor devices, primarily silicon microcircuits, which are used in the greatest quantity and which, in most cases, are the most sensitive. After a summary of the natural space radiation environment and the effects of radiation on semiconductor devices, laboratory simulation of space radiation and extrapolation to space are covered. Radiation testing is performed to understand failure mechanisms, to characterize the radiation response of specific devices, and to provide data for lot acceptance. Part selection and hardness assurance are discussed by contrasting the traditional approach with the unique aspects of space systems. Some recommendations are made for treating the more complex aspects of space system microcircuit hardness assurance     

Reliability for nanomagnetic logic (NML) readout circuit under single event effect

In the application for the space radiation environment, NML circuits face a reliability challenge mainly from their CMOS peripheral circuits, suffering from single event effects (SEE). An on-chip readout interface circuit (RIC) for NML circuit is designed based on dual-barrier magnetic tunnel junction (DB-MTJ). The sensitive nodes to SEE in RIC are analyzed. The SEU required critical charge in RIC is described. The impacts of energetic particle hitting time and technology node on the critical charge are studied. As the technology node scales down, the critical charge will significantly decrease. Two efficient hardening technologies for RIC are presented: local transistors׳ size and symmetrical load capacitances. By increasing local transistors׳ size or decreasing the load capacitance, the critical charge will be improved, which enhances the immunity to SEE.     

CMOS有源像素图像传感器的辐照损伤效应

互补金属氧化物半导体(CMOS)有源像素(APS)图像传感器作为光电成像系统的核心器件,被广泛应用在空间辐射或核辐射环境中,辐照损伤是导致其性能退化,甚至功能失效的主要原因之一。阐述了不同辐射粒子或射线辐照损伤诱发CMOS APS图像传感器产生位移效应、总剂量效应和单粒子效应的损伤物理机制。综述和分析了辐照损伤诱发CMOS APS图像传感器暗信号增大、量子效率减小、饱和输出电压减小、噪声增大以及暗信号尖峰和随机电码信号(RTS)产生的实验规律和损伤机理。归纳并提出了CMOS APS图像传感器辐照损伤效应研究亟待解决的问题。     

Effects of radiation and charge trapping on the reliability of high-κ gate dielectrics

The radiation response and long term reliability of alternative gate dielectrics will play a critical role in determining the viability of these materials for use in future space applications. The total dose radiation responses of several near and long term alternative gate dielectrics to SiO₂ are discussed. Radiation results are presented for nitrided oxides, which show no change in interface trap density with dose and oxide trapped charge densities comparable to ultra thin thermal oxides. For aluminum oxide and hafnium oxide gate dielectric stacks, the density of oxide trapped charge is shown to depend strongly on the film thickness and processing conditions. The alternative gate dielectrics discussed here are shown to have effective trapping efficiencies that are up to 15 to 20 times larger than thermal SiO₂ of equivalent electrical thickness. A discussion of single event effects in devices and ICs is also provided. It is shown that some alternative gate dielectrics exhibit excellent tolerance to heavy ion induced gate dielectric breakdown. However, it is not yet known how irradiation with energetic particles will affect the long term reliability of MOS devices with high-κ gate dielectrics in a space environment.     

SOI材料与器件的辐照效应

目前，ＳＯＩ（ＳｉｌｉｃｏｎＯｎＩｎｓｕｌａｔｏｒ）材料的一个主要用途是用来制作抗辐照电路，本文以ＳＩＭＯＸ（ＳｅｐｅｒａｔｉｏｎｂｙＩＭｐｌａｎｔａｔｉｏｎｏｆＯＸｙｇｅｎ）技术为主，详细论述了ＳＯＩ材料和器件（ＭＯＳＦＥＴ）的辐照特性及其机理，包括总剂量、瞬时和单粒子效应，并以总剂量效应为主。经过恰当的加固工艺和优化设计，可以制造出优良的抗辐照集成电路。     

Design of high performance and radiation hardened SPARC-V8 processor

Design of a highly reliable SPARC-V8 processor for space applications requires consideration single-event effects including single event upsets, single event transients, single event latch-up, as well as cumulative effects such as the total ionizing dose (TID). In this paper, the fault tolerance of the SPARC-V8 processor to radiation effects is discussed in detail. The SPARC-V8 processor, fabricated in the 65 nm CMOS process, achieves a frequency of 300 MHz with a core area of 9.78×9.78 mm², and it is demonstrated that its radiation hardened performance is suitable for operating in a space environment through the key elements' experiments, which show TID resistance to 300 krad(Si), SEL immunity to greater than 92.5 MeV·cm²/mg, and an SEU error rate of 2.51×10^-4 per day.     

Considerations for the development of radiation resistant devices and VLSI circuits

The impact of radiation on Very Large Scale Integration (VLSI) silicon technology is discussed with a focus on Complimentary Metal-Oxide Semiconductor (CMOS). Effects of total dose, transient radiation, single event phenomena, and neutron fluence on devices and circuits are presented. General approaches to mitigating radiation effects are put forth. With proper considerations, VLSI CMOS can be enhanced to achieve several orders-of-magnitude increase in radiation tolerance.     

应变Si NMOS器件总剂量辐射对单粒子效应的影响

针对应变Si NMOS器件总剂量辐射对单粒子效应的影响机制,采用计算机TCAD仿真进行研究。通过对比实验结果,构建50 nm应变Si NMOS器件的TCAD仿真模型,并使用该模型研究处于截至态(V_ds=1 V)的NMOS器件在总剂量条件下的单粒子效应。实验结果表明,总剂量辐照引入的氧化层陷阱正电荷使得体区电势升高,加剧了NMOS器件的单粒子效应。在2 kGy总剂量辐照下,漏极瞬态电流增加4.88%,而漏极收集电荷增量高达29.15%,表明总剂量辐射对单粒子效应的影响主要体现在漏极收集电荷的大幅增加方面。     

辐照加固的500MHz锁相环设计

设计了一款与CSMC 0.5μm CMOS工艺兼容的频率为500 MHz的辐照加固整数型锁相环电路,研究了总剂量辐照以及单粒子事件对锁相环电路主要模块及整个系统性能的影响。此外,通过修正BSIM3V3模型的参数以及施加脉冲电流源来模拟总剂量辐照效应和单粒子事件,对锁相环整体电路进行了电路模拟仿真以及版图寄生参数提取后仿真。模拟结果表明,辐照总剂量为1Mrad(Si)时锁相环电路仍能正常工作,产生270.58~451.64 MHz的时钟输出,峰峰值抖动小于100 ps,锁定时间小于4μs;同时在对单粒子事件敏感的数字电路的主要节点处施加脉冲电流源后,锁相环电路均能在短时间内产生稳定的输出。     

Total ionizing dose radiation effects on NMOS parasitic transistors in advanced bulk CMOS technology devices

In this paper, total ionizing dose effect of NMOS transistors in advanced CMOS technology are examined. The radiation tests are performed at ⁶⁰Co sources at the dose rate of 50 rad (Si)/s. The investigation''s results show that the radiation-induced charge buildup in the gate oxide can be ignored, and the field oxide isolation structure is the main total dose problem. The total ionizing dose (TID) radiation effects of field oxide parasitic transistors are studied in detail. An analytical model of radiation defect charge induced by TID damage in field oxide is established. The I-V characteristics of the NMOS parasitic transistors at different doses are modeled by using a surface potential method. The modeling method is verified by the experimental I-V characteristics of 180 nm commercial NMOS device induced by TID radiation at different doses. The model results are in good agreement with the radiation experimental results, which shows the analytical model can accurately predict the radiation response characteristics of advanced bulk CMOS technology device.