Compact charge and capacitance modeling of undoped ultra-thin body (UTB) SOI MOSFETs

We present an analytic, explicit and continuous charge model for a long-channel UTB (ultra-thin body) SOI (silicon-on-insulator) MOSFET, from which analytical expressions of the total capacitances are obtained. Our model is valid from below to well above threshold, without suffering from discontinuities between the regimes. It is based on a unified charge control model derived from Poisson’s equation. The drain-current, charge and capacitances expressions result in continuous explicit functions of the applied bias.The calculated capacitance characteristics are validated by 2D numerical simulations showing a very good agreement for different silicon film thicknesses.     

Analytical Charge and Capacitance Models of Undoped Cylindrical Surrounding-Gate MOSFETs

We present an analytical and continuous charge model for cylindrical undoped surrounding-gate MOSFETs, from which analytical expressions of all total capacitances are obtained. The model is based on a unified charge control model derived from Poisson equation. The drain current, charge, and capacitances are written as continuous explicit functions of the applied voltages. The calculated capacitance characteristics show excellent agreement with three-dimensional numerical device simulations     

Modeling of cylindrical surrounding gate MOSFETs including the fringing field effects

A physically based analytical model for surface potential and threshold voltage including the fringing gate capacitances in cylindrical surround gate(CSG) MOSFETs has been developed.Based on this a subthreshold drain current model has also been derived.This model first computes the charge induced in the drain/source region due to the fringing capacitances and considers an effective charge distribution in the cylindrically extended source/drain region for the development of a simple and compact model.The fringing gate capacitances taken into account are outer fringe capacitance,inner fringe capacitance,overlap capacitance,and sidewall capacitance.The model has been verified with the data extracted from 3D TCAD simulations of CSG MOSFETs and was found to be working satisfactorily.     

A new empirical nonlinear model for sub-250 nm channel MOSFET

An empirical nonlinear model for sub-250 nm channel length MOSFET is presented which is useful for large signal RF circuit simulation. Our model is made of both analytical drain current and gate charge formulations. The drain current expression is continuous and infinitely derivable, and charge conservation is taken into account, as the capacitances derive from a single charge expression. The model's parameters are first extracted, prior the model's implementation into a circuit simulator. It is validated through dc, ac, and RF large signal measurements compared to the simulation.     

A Compact Model of Silicon-Based Nanowire MOSFETs for Circuit Simulation and Design

A silicon-based nanowire FET (SNWT) compact model is developed for circuit simulation. Starting from the solution of Poisson's equation, an accurate inversion charge expression is derived for SNWTs with arbitrary body doping concentration. The drain current, transconductance, output conductance, terminal charges, and capacitances are then calculated based on fundamental device physics. Short-channel and quantum effects have been included in the model in a self-consistent way. Comparison between the numerical simulation and analytical calculation shows that the proposed model is valid for all operation regions of SNWTs with different dimensions and channel doping. The model has been implemented in circuit simulators by Verilog-A, and its application in circuit simulation is also demonstrated.      

A charge sheet model for MOSFETs with an abrupt retrograde channel: Part II. Charges and intrinsic capacitances

The 16 intrinsic capacitance components related to the gate, source, drain and depletion charges are examined for MOSFETs with an ideally abrupt retrograde doping profile in the channel, based on the analytical solutions for the drain current and body charge in the preceding paper. Though lengthy and complex in their final mathematical expressions, analytical solutions for the capacitances can be obtained. The validity of the analytical solutions is confirmed by comparing the modeling results with simulation data obtained using numerical calculations. The inclusion of an intrinsic surface layer in the channel merely causes a simple voltage shift for the capacitances that are not associated with the depletion charge or body bias, similarly to the variation of the drain current shown in the preceding paper. For the capacitances that are related to the depletion charge or body bias, there is not only a parallel voltage shift with an amount commensurate to the shift in drain current as well as in the other capacitances, but also a decrease in their values. This decrease depends on the thickness of the intrinsic surface layer and it amounts to 25% for a surface layer of 30 nm thickness.     

An explicit analytical charge-based model of undoped independent double gate MOSFET

This paper describes an explicit analytical charge-based model of an undoped independent double gate (DG) MOSFET. This model is based on Poisson equation resolution and field continuity equations. Without any fitting parameter or charge sheet approximation, it provides explicit analytical expressions of both inversion charge and drain current considering long undoped transistor. Consequently, this is a fully analytical and predictive model allowing describing planar DG MOSFET as well as FinFET structures. The validity of this model is demonstrated by comparison with Atlas simulations.     

A capacitance model for GaAs MESFETs

A capacitance model for a GaAs MESFET suitable for implementation in the circuit analysis program SPICE is presented. The model consists of nonlinear capacitances that are a function of two voltages. Such a model gives rise to ordinary nonlinear capacitances and transcapacitances. The placement of these elements in the Y matrix is shown. The empirical equations for the gate charge of a GaAs MESFET given provide an accurate SPICE model for the gate charge and capacitances of a MESFET. A comparison of measured capacitance values with the modeled values gives close enough agreement for circuit simulation purposes     

Coupling capacitances in the planar conductive path system of the hybrid circuit with dielectric layer

This paper presents the analytical method of capacitance calculation for the hybrid circuit. The analyzed example of planar conductive paths, being a system of typical spatial configuration, is a part of research that is to develop a general, universal mathematic model to calculate parasite capacitances in hybrid structures. In general, this leads to solve the 3D boundary problem. The Fourier’s integral transformation has been used in order to determine the potential satisfying the Laplace equation.

Resulting from here the equation system of electric charge distribution is being solved numerically by using the collocation method. On this basis the capacitance between conducting paths is calculated and experimentally verified.     

Quasistatic compact modelling of organic thin-film transistors

A compact model for the quasistatic charge and capacitances in organic thin-film transistor (OTFT) is derived and implemented for the simulation of organic circuits. A model for organic ring oscillator circuits is also developed. Comparing the models to experimental data, the simulation qualitatively reproduces the experimental data for frequency, amplitudes and waveforms. The simulation results indicate that the quasistatic model underestimates the capacitances in organic circuits, and it is shown that the geometrical capacitances originating from layout and gate overlap dominate in organic ring oscillators.     

The Effect of Signal Activity on Propagation Delay of CMOS Logic Gates Driving Coupled On-Chip Interconnections

The effect of interconnect coupling capacitances on neighboring CMOS logic gates driving coupled interconnections strongly depends upon signal activity. A transient analysis of two capacitively coupled CMOS logic gates is presented in this paper for different combinations of signal activity. The uncertainty of the effective load capacitance and propagation delay due to signal activity is addressed. Analytical expressions characterizing the output voltage and propagation delay are also presented for different signal activity conditions. The propagation delay based on these analytical expressions is within 3% as compared to SPICE, while the estimated delay neglecting the difference between the load capacitances can exceed 45%. The logic gates should be properly sized to balance the load capacitances in order to minimize any uncertainty in the delay and load. The peak noise voltage on a quiet interconnection determined from the analytical expressions is within 4% of SPICE. The peak noise voltage on a quiet interconnection can be minimized if the effective output conductance of the quiet logic gate driving the interconnect is increased.     

SiGe HBT大信号扩散电容模型研究

基于SiGe HBT（异质结双极晶体管）大信号等效电路模型,建立了SiGe HBT大信号发射结扩散电容模型和集电结扩散电容模型．该模型从SiGe HBT正反向传输电流出发,研究晶体管内可动载流子所引起的存储电荷（包括正向存储电荷和反向存储电荷）的基础上,同时考虑了厄利效应对载流子输运的影响,其物理意义清晰,拓扑结构简单。将基于大信号扩散电容模型的SiGe HBT模型嵌入PSPICE软件中,实现对SiGe HBT器件与电路的模拟分析。对该模型进行了直流特性模拟分析,直流模拟分析结果与文献报道的结果符合得较好,瞬态特性分析结果表明响应度好。     

Interperiod capacitance calculations for three-dimensionalmulticonductor systems

An approach is proposed to facilitate the capacitance calculations for periodic three-dimensional multiconductor systems. Based on the Fourier transform technique, the approach requires only the conductors inside one period and solves the charge distribution in the spectral domain by the integral equation method. The resultant spectral capacitances are then inverse transformed to give the capacitances between any two conductors, which may even be inside different periods. The approach is applied to the capacitance analysis for connector pins in a packaging board design     

A capacitance model for GaAs MESFET's

We present a new analytical model for small signal capacitances of GaAs MESFET's. This model may be used for epitaxially grown as well as ion-implanted FET's because the effects related to the nonuniform doping profile are included. We also take into account backgating, capping, velocity saturation in the conducting channel, and possible Gunn domain formation in the channel at the drain side of the gate. The model explains complicated voltage dependences of the gate-source and gate-drain capacitances of GaAs microwave FET's and is in fair agreement with the experimental results. This analytical model is quite suitable for the computer-aided design of GaAs microwave FET's and integrated circuits.     

Double-layer microstrip structures—lumped capacitances and open-circuit end correction

The analysis is reported of the lumped capacitance and open-circuit end effects of finite-length strip conductors in double-layer microstrip structures. Two specific configurations, namely double-layer microstrip and microstrip-with-overlay configurations, are considered. The analytical approach uses the variational technique in the Fourier transform domain in conjunction with the transverse transmission line technique. It is identified that the only parameter needed to analyse the lumped capacitances and open-circuit end effects of these microstrip structures is the admittance at the charge plane. This parameter can easily be determined from the two-wire transmission line equivalent circuit. Extensive numerical data are generated for the lumped capacitances and open-circuit end effects of the finite-length strip conductor in double-layer microstrip and microstrip-with-overlay configurations. The data presented should be useful in designing lumped elements and filters in these configurations.     

A simple analytical model to accurately predict self-resonance frequencies of on-silicon-chip inductors in TEM mode and eddy current mode

For the first time, a simple analytical model in the form of explicit formulas was derived for on-silicon-chip inductors. This analytical model can accurately calculate self-resonance frequencies (f_SR) in TEM mode and eddy current mode corresponding to very high and very low substrate resistivities (ρ_Si). Furthermore, this derived model can predict and explain the interesting result that f_SR keeps nearly a constant independent of ρ_Si in TEM and eddy current modes but is critically determined by the inductance and parasitic capacitances. The simple model is useful in on-silicon-chip inductor design for increasing f_SR under specified inductance target for broadband RF circuit design and applications.     

Consistent modeling of capacitances and transit times of GaAs-based HBTs

This paper investigates how time delays and capacitances observed under small-signal conditions can be consistently accounted for in heterojunction bipolar transistor (HBT) large-signal models. The approach starts at the circuit level by mapping the large-signal equivalent circuit (which consists of charge and current sources) to the well-known small-signal circuit (which consists of capacitances, transit-time, and resistances). It is shown that and how bias dependent charge sources at either pn-junction impact transit-time, base-collector capacitance, and their mutual dependence. It is demonstrated for the example of a GaAs-based HBT that the interrelation of the elements is observed in measurements as predicted. The results of the investigation enhance understanding of HBT model characteristics and provide a criterion to check model consistency.