一种快捕获宽调节范围的锁相环

提出了一种快捕获,低抖动,宽调节范围的增益自适应锁相环的设计.在这个方案中,采用了双边触发的鉴频鉴相器(dual-edge-triggered phase frequency detector)和自调节压控振荡器(self-regulated voltage controlled oscillator)并进行了详细的分析.芯片的加工工艺是0.5μm 1P3M CMOS标准数字逻辑工艺.测试结果表明输入频率变化在捕获范围的37%时,捕获时间为150ns;输出频率为640MHz时,均方根抖动为39ps.     

Frequency Detectors for PLL Acquisition in Timing and Carrier Recovery

A significant problem in phase-locked loop (PLL) timing and carrier extraction is the initial acquisition. Very narrow loop bandwidths are generally required to control phase jitter, and acquisition may depend on an extremely accurate initial VCO frequency (VCXO) or sweeping. We describe two simply implemented frequency detectors which, when added to the traditional phase detector, can effect acquisition even with very small loop bandwidths and large initial frequency offsets. The first is the quadricorrelator, previously applied to timing recovery by Bellisio, while the second is new, and called a rotational frequency detector. The latter, while limited to lower frequencies and higher signal-to-noise ratios, is suitable for many applications and can be implemented with simpler circuitry.     

Digital-only PLL with adaptive search step

In this paper, an all-digital phase-locked loop (PLL) with adaptively controlled up/down counter serves as the loop filter is presented, and it is implemented on a field-programmable gate array. The detailed circuit of the adaptive up/down counter implementing the adaptive search algorithm is also given, in which the search step for frequency acquisition is adaptively scaled down in half until it is reduced to zero. The phase jitter of the proposed PLL can be lowered, yet keeping with fast lock-in time. Thus, the dilemma between the low phase jitter and fast lock-in time of the traditional PLL can be resolved. Simulation results and circuit implementation show that the locked count, phase jitter and lock-in time of the proposed PLL are consistent with the theoretical predictions.     

A VCDL-based 60-760-MHz dual-loop DLL with infinite phase-shift capability and adaptive-bandwidth scheme

A dual-loop delay-locked loop (DLL) was implemented by using an analog voltage-controlled delay line (VCDL) for low jitter. An infinite phase-shift capability with seamless phase change was achieved by adding a look-ahead VCDL. A low jitter was achieved for the entire input frequency lock range from 60 to 760 MHz by using the adaptive bandwidth scheme in both reference and fine loops. A wide input-frequency lock range was achieved due to the combined effects of the dual-loop architecture and the extra phase detector of the reference DLL. The extra phase detector eliminated the constraint on the initial VCDL delay for DLL to be locked. Measurements on the fabricated chip by using a 0.18-/spl mu/m CMOS process showed a power consumption of 63 mW at 700 MHz, an active chip area of 370/spl times/510 /spl mu/m/sup 2/, and peak-to-peak jitters of 28 and 39 ps at the 700-MHz synchronous and plesiochronous operations, respectively.     

A new pattern jitter free frequency error detector

One method to enable fast acquisition of a phase-locked loop (PLL) in spite of large frequency offsets and small PLL bandwidths is to use an additional AFC (automatic frequency control) loop. A suitable frequency error detector (FED) for large frequency offsets is the well-known balanced quadricorrelator. This FED is shown to produce great pattern jitter if it is to work with digital modulated MQAM and MPSK signals (M>2) and random data. The authors describe how this pattern jitter for MQAM and MPSK signals can be overcome completely. Another understanding of the balance quadricorrelator is also given     

A 250-622 MHz deskew and jitter-suppressed clock buffer usingtwo-loop architecture

A 250-622 MHz clock buffer has been developed, using a two-loop architecture: a delay-locked loop (DLL) for deskew, and a frequency-locked loop (FLL) for reference frequency supply to the DLL. The DLL incorporates a current-mode phase detector which utilizes a flip-flop metastability to detect a phase difference in the order of 20 ps. A measured jitter is suppressed to less than 40 ps RMS over the operating frequency range. A DLL acquisition time of 150 ns typical is simulated at 400 MHz. A 0.4-μm CMOS technology is used to fabricate the chip     

一个简单鉴频鉴相器结构实现的快速锁定低抖动锁相环

用简单的鉴频鉴相器结构实现了一个快锁定低抖动的锁相环.鉴频鉴相器仅仅由两个异或门组成,它可以同时获得低抖动和快锁定的性能.锁相环中的电压控制振荡器由四级环形振荡器来实现,每级单元电路工作在相同的频率,并提供45°的相移.芯片用0.18μm CMOS工艺来实现.PLL输出的中心频率为5GHz,在偏离中心频率500kHz处,测量的相位噪声为-102.6dBc/Hz.锁相环的捕获范围为280MHz,RMS抖动为2.06ps.电源电压为1.8V时,功耗仅为21.6mW(不包括输出缓冲).     

A simple precharged CMOS phase frequency detector

We propose a simple precharged CMOS phase frequency detector (PFD). The circuit uses 18 transistors and has a simple topology. Therefore, the detector, in a 0.8-μm CMOS process, works up to clock frequencies of 800 MHz according to SPICE simulations on extracted layout. Further, the detector has no dead-zone in the phase characteristic which is important in low jitter applications. The phase and frequency characteristics are presented and comparisons are made to other PFDs. The phase offset of the detector is sensitive to differences of the duty-cycle between the inputs. Mixed-mode simulations are presented of the lock-in procedure for a phase-locked loop (PLL) where the detector is used. Measurements on the detector are presented for a test-chip with a delay-locked loop (DLL) where the phase detection ability of the detector has been verified     

Fast locking scheme for PLL frequency synthesiser

A phase-locked loop (PLL) with a fast-locked nonlinear phase frequency detector (PFD) is presented. Compared with the conventional discriminator-aided phase detector, the proposed fast-locked PFD can further reduce the PLL acquisition time while the loop stability remains unchanged. Moreover, the new architecture can decrease the capacitance value and the charge-pump current to 1/k of a conventional one as the loop bandwidth increases k times, thus saving substantial area and power.     

Properties of Optical Phase-Locked Loop Based on Four Wave Mixing in Semiconductor Laser Amplifiers

In this paper, the properties of the optical phase-locked loop(PLL) based on the four-wave mixing in the semiconductor laser amplifiers (SLAs) are discussed. The components that achieve the function of detecting the bit phase of the input optical signal are concerned and discussed in detail together as a function module named as the optical bit phase detector referred to the general electronic PLL. Therefore, most of the properties of the optical PLL can be analyzed by applying the general phase-locked theory. Here the stability of the optical PLL is discussed. It's shown that the variance of input signal power in the practical application will cause optical PLL system unstable because of its long loop delay. The influence on the output phase jitter of the optical PLL is also investigated.     

A low-jitter 1.9-V CMOS PLL for UltraSPARC microprocessorapplications

A phase-locked loop (PLL) for CMOS UltraSPARC microprocessor applications uses a loop filter referenced to a quiet power supply and achieves measured clock period jitter of ±25 ps at 360 MHz. The fully integrated CMOS PLL uses a charge-pump phase/frequency detector, a single-capacitor loop filter, and a feedforward error correction architecture. Loop characteristics are analyzed and verified by measurements. The measured sensitivity of clock period jitter to supply voltage is 2.6 ps/100 mv over an analog supply-voltage range of 1.6-2.1 V; the measured output operating frequency range is 8.5-660 MHz. Fabricated in an area of 310×280 μm² in a 0.25-μm CMOS process, the PLL dissipates 25 mW from a 1.9-V supply     

Short locking time and low jitter phase-locked loop based on slope charge pump control

A novel structure of a phase-locked loop(PLL) characterized by a short locking time and low jitter is presented,which is realized by generating a linear slope charge pump current dependent on monitoring the output of the phase frequency detector(PFD) to implement adaptive bandwidth control.This improved PLL is created by utilizing a fast start-up circuit and a slope current control on a conventional charge pump PLL.First,the fast start-up circuit is enabled to achieve fast pre-charging to the loop filter...     

A per-survivor phase acquisition and tracking algorithm fordetection of TCM signals with phase jitter and frequency error

In this letter we investigate the performance of a per-survivor phase estimation algorithm for detection of trellis-coded modulation (TCM) signals in the presence of phase jitter and frequency error. Phase and frequency estimates are derived based on a second-order phase-locked loop (PLL)-like algorithm. A simplified transient and steady-state analysis of the algorithm recursive equations is derived. A heuristic blind phase acquisition scheme is proposed and shown to achieve good results. Computer simulations are used to compare the algorithm's performance to other methods described in the literature     

一种快速捕获、带宽可调的锁相环电路

设计实现了一个快速捕获,带宽可调的电荷泵型锁相环电路。采用了一种利用状态机拓展鉴频鉴相器检测范围的方法,加快了环路的锁定;通过SPI总线实现电荷泵电流配置和调整VCO延时单元的延迟时间,优化了电路性能。芯片采用中芯国际0.18μmCMOS工艺,测试结果表明,锁相环锁定在100MHz时的抖动均方值为24ps,偏离中心频率1MHz处的相位噪声为-98.62dBc/Hz。     

SiGe clock and data recovery IC with linear-type PLL for 10-Gb/sSONET application

An integrated 10 Gb/s clock and data recovery (CDR) circuit is fabricated using SiGe technology, It consists of a linear-type phase-locked loop (PLL) based on a single-edge version of the Hogge phase detector, a LC-tank voltage-controlled oscillator (VCO) and a tri-state charge pump. A PLL equivalent model and design method to meet SONET jitter requirements are presented. The CDR was tested at 9.529 GB/s in full operation and up to 13.25 Gb/s in data recovery mode. Sensitivity is 14 mV_pp at a bit error rate (BER)=10^-9 . The measured recovered clock jitter is less than 1 ps RMS. The IC dissipates 1.5 W with a -5 V power supply     

A 155-MHz clock recovery delay- and phase-locked loop

The authors describe a completely monolithic delay-locked loop (DLL) that may be used either by itself as a deskewing element, or in conjunction with an external voltage-controlled crystal oscillator (VCXO) to form a delay- and phase-locked loop (D/PLL). By phase shifting the input data rather than the clock, the DLL and D/PLL provide jitter-peaking-free clock recovery. Additionally, the jitter transfer function of the D/PLL has a low bandwidth for good jitter filtering without compromising acquisition speed. The D/PLL described here exhibits less than 1° r.m.s. jitter on the recovered clock, independent of the input data density. No jitter peaking is observed over the 40-kHz jitter bandwidth     

基于半速率锁相环的5Gb/s CMOS单片时钟恢复电路

利用TSMC的O．18μm CMOS工艺,设计实现了单片集成的5 Gb/s锁相环型时钟恢复电路。该电路采用由半速率鉴相器、四相位环形电流控制振荡器、电荷泵以及环路滤波器组成的半速率锁相环结构。测试表明：在输入速率为5 Gb/s、长度为211-1伪随机序列的情况下,恢复出时钟的均方根抖动为4．7 ps。在偏离中心频率6MHz频率处的单边带相位噪声为-112．3 dBe/Hz。芯片面积仅为0．6mm×O．6 mm,采用1.8 V电源供电,功耗低于90 mW。     

A low spur, low jitter 10-GHz phase-locked loop in 0.13-μm CMOS technology

This paper presents a 10-GHz low spur and low jitter phase-locked loop (PLL).An improved low phase noise VCO and a dynamic phase frequency detector with a short delay reset time are employed to reduce the noise of the PLL.We also discuss the methodology to optimize the high frequency prescaler's noise and the charge pump's current mismatch.The chip was fabricated in a SMIC 0.13-μm RF CMOS process with a 1.2-V power supply.The measured integrated RMS jitter is 757 fs (1 kHz to 10 MHz); the phase noise is -89 and-118.1 dBc/Hz at 10 kHz and 1 MHz frequency offset,respectively; and the reference frequency spur is below -77 dBc.The chip size is 0.32 mm2 and the power consumption is 30.6 mW.     

一种基于55nmCMOS工艺，输出频率0.1G-1.5G Hz的低抖动锁相环

本文设计了一种0.1G-1.5GHz,3.07pS RMS 抖动的多相位输出锁相环。通过引入双路径电荷泵,极大的减小了锁相环中的低通滤波器的尺寸。基于指定的功耗约束,提出了一种新颖的压控振荡器、电荷泵与鉴频鉴相器的尺寸优化方法,使用该方法,每个模块输出相位噪声减小了约3-6dBc/Hz。该锁相环在55nm的工艺下流片,集成了16pF的MOM电容,占用面积仅为0.05平方毫米。输出1.5GHz信号时,功耗2.8mW,相位噪声为-102dBc/Hz@1MHz。     

A 4224 MHz low jitter phase-locked loop in 0.13-μm CMOS technology

A 4224 MHz phase-locked loop (PLL) is implemented in 0.13 μm CMOS technology. A dynamic phase frequency detector is employed to shorten the delay reset time so as to minimize the noise introduced by the charge pump. Dynamic mismatch of charge pump is considered. By balancing the switch signals of the charge pump, a good dynamic matching characteristic is achieved. A high-speed digital frequency divider with balanced input load is also designed to improve in-band phase noise performance. The 4224 MHz PLL achieves phase noises of-94 dBc/Hz and -114.4 dBc/Hz at frequency offsets of 10 kHz and 1 MHz, respectively. The integrated RMS jitter of the PLL is 0.57 ps (100 Hz to 100 MHz) and the PLL has a reference spur of-63 dB with the second order passive low pass filter.