Extended One-Dimensional Analysis to Effectively Derive Quantum Efficiency of Various CMOS Photodiodes

This paper proposes an extended 1-D analysis to derive quantum efficiency of various commonly used CMOS photodiodes. The theoretical model of the CMOS photodiode with the n-/p-epitaxial/p + substrate (n-/p-epi/p + sub) structure is established from steady-state continuity equations, where most existing boundary conditions are applied. In particular, the minority carrier and current densities are continuous across the interface between two layers with the same dopant type. Models of the other commonly used CMOS photodiodes are also examined. Three CMOS photodiodes with n-/p-substrate (n-/p-sub), p⁺/n-/p-substrate (p⁺/n-/p-sub), and n-/p-epi/p + sub structures are fabricated and characterized to validate the proposed model. Additionally, the surface recombination velocity is adequately determined by fitting the simulated quantum efficiency to the measured value. The simulated quantum efficiency of the proposed model for these three photodiodes is quite consistent with the measured values, revealing the feasibility and effectiveness of the proposed model in characterizing various CMOS photodiodes.     

薄膜SOI／CMOS的SPICE电路模拟

鉴于ＳＰＩＣＥ是目前世界上广泛采用的通用电路模拟程序，具具有可扩展模型的灵活性，我们通过修改ＳＰＩＣＥ源程序把新器件模型－－ＳＯＩＭＯＳＦＥＴ模型移植入ＳＰＩＣＥ中，通过我们的模拟工作，证实了我们模型的正确性和电路实用性，分析了器件参数对ＳＯＩ／ＣＭＯＳ电路速率的影响，这些结论可以很好地指导电路设计和工艺实践。     

CMOS device noise considerations for terabit lightwave systems

An improved model to predict sensitivity of p-i-n lightwave receivers using CMOS technology is proposed. This model incorporates the latest understanding of excess channel noise observed in nanoscale MOSFETs. For the case of an ideal channel filter, the results are presented in an analytical closed form. For nonideal channels, the concept of higher order Personick integrals is introduced. Up to 10 Gb/s, the results predicted by the above model closely mimic the existing CMOS data published over the last 20 years. Above 10 Gb/s, due to lack of CMOS data, projections are evaluated against the nonsilicon technologies. The predictions compare very favorably with the measured system performance using high electron mobility transistors and heterojunction bipolar transistors. The findings thus indicate that CMOS should claim its status as the low-cost high-performance highly integrated technology of choice for lightwave applications beyond 10 Gb/s.     

Prediction of CMOS APS design enabling maximum photoresponse for scalable CMOS technologies

This brief represents the CMOS active pixel sensor (APS) photoresponse model use for maximum pixel photosignal prediction in scalable CMOS technologies. We have proposed a simple approximation determining the technology-scaling effect on the overall device photoresponse. Based on the above approximation and the data obtained from the CMOS 0.5 /spl mu/m process thorough investigation we have theoretically predicted, designed, measured and compared the optimal (in the output photosignal sense) pixel in a more advanced, CMOS 0.35 /spl mu/m technology. Comparison of both, our theoretically predicted and modeled results and the results obtained from the measurements of an actual pixel array gives excellent agreement. It verifies the presented scaling-effect approximation and validates the usefulness of our model for design optimization in scalable CMOS technologies.     

Waveform analysis and delay prediction for a CMOS gate driving RLC interconnect load

This paper deals with the problem of estimating the performance of a CMOS gate driving RLC interconnect load. The widely accepted model for CMOS gate and interconnect line is used for the representation. The CMOS gate is modeled by an Alpha Power law model, whereas the distributed RLC interconnect is represented by an equivalent π-model. The output waveform and the propagation delay of the inverter are analytically calculated and compared with SPICE simulations. The analytical driver-interconnect load model gives sufficiently close results to SPICE simulations for two different cases of slow and fast input ramps. For each case of stimulation, the model gives an insight to four regions of operation of the CMOS gate. The voltage waveform at the end of an interconnect line is obtained for each region of operation. The SPICE and analytical results for the output voltage waveform and propagation delay match very closely.     

一种新型的高性能CMOS电流比较器电路

分析了目前几种高性能连续时间CMOS电流比较器的优缺点,提出了一种新型CMOS电流比较器电路．它包含一组具有负反馈电阻的CMOS互补放大器、两组电阻负载放大器和两组CMOS反相器．由于CMOS互补放大器的负反馈电阻降低了它的输入、输出阻抗,从而使电压的变化幅度减小,所以该电流比较器具有较短的瞬态响应时间和较快的速度．电阻负载放大器的使用减小了电路的功耗．利用1.2μm CMOS工艺HSPICE模型参数对该电流比较器的性能进行了模拟,结果表明该电路的瞬态响应时间达到目前最快的CMOS电流比较器的水平,而功耗则低于这些比较器,具有最大的速度/功耗比．此外,该CMOS电流比较器结构简单,性能受工艺偏差的影响小,适合应用于高速/低功耗电流型集成电路中．     

Photoresponse analysis and pixel shape optimization for CMOS active pixel sensors

In this work, a semi-analytical model, based on a thorough analysis of experimental data, is developed for photoresponse estimation of a photodiode-based CMOS active pixel sensor (APS). The model covers the substrate diffusion effect together with the influence of the photodiode active-area geometrical shape and size. It describes the pixel response dependence on integration photocarriers and conversion gain and demonstrates that the tradeoff between these two conflicting factors gives an optimum geometry enabling extraction of maximum photoresponse. The parameter dependence on the process and design data and the degree of accuracy for the photoresponse modeling are discussed. Comparison of the derived expression with the measurement results obtained from a 256/spl times/256 CMOS APS image sensor fabricated via HP in a standard 0.5-/spl mu/m CMOS process exhibits excellent agreement. The simplicity and the accuracy of the model make it a suitable candidate for implementation in photoresponse simulation of CMOS photodiode arrays.     

An improved model for ground-shielded CMOS test fixtures

An improved model for ground-shielded (GS) test fixtures is proposed. The proposed model provides more accurate device-under-test gap behavioral model than previous test-fixture models and takes into account the impedance of the ground return path. The new model is validated up to 25 GHz by comparing the model simulations with experimental measurements. The proposed model is applied to bulk-silicon- and sapphire-based GS test fixtures with different layouts. Furthermore, a large phase shift in the shield-based test-fixture forward transmission is reported in this study. Based on the results achieved, suggestions for deembedding method selection are given. Test fixtures were fabricated using a 0.35-/spl mu/m CMOS process and 0.5-/spl mu/m silicon-on-sapphire CMOS process.     

Modified Model for Settling Behavior of Operational Amplifiers in Nanoscale CMOS

An accurate time-domain model for the settling behavior of folded-cascode operational amplifiers is presented. Using a velocity–saturation model for MOS transistors makes the proposed model suitable for nanoscale CMOS technologies. Both linear and nonlinear settling regimes and their combination are considered. Transistor-level HSPICE simulation results of a fully differential single-stage folded-cascode amplifier using BSIM4v3 models of a standard 90-nm CMOS process are presented to verify the accuracy of the proposed models.      

Analysis of the switching speed of a submicrometer-gate CMOS/SOS inverter

The speed of a short-channel CMOS/SOS inverter circuit can be predicted with the use of a simple analytical model. Transistor switching times and stage charging times are assumed to contribute independently to the total propagation delay. The analysis is shown to represent accurately the behavior of 1.5- and 0.9-µm-gate CMOS/SOS ring oscillators.     

双等比CMOS缓冲器的设计

双比CMOS缓冲器可分为双等比和双变比CMOS缓冲器，文章对双等比CMOS缓冲器进行了设计研究，提出了它的一种次优实验方法，双等比CMOS缓冲器容易取得对称的传播延迟，可以在较小的面积与功耗下取得和等比CMOS缓冲器相等的传播延迟，使用0．35um工艺参数的HSPICE模拟结果证实了双等比CMOS缓冲器的性能。     

Radiation-Induced Fault Simulation of SOI/SOS CMOS LSI’s Using Universal Rad-SPICE MOSFET Model

The methodology of modeling and simulation of environmentally induced faults in radiation hardened SOI/SOS CMOS IC’s is presented. It is realized at three levels: CMOS devices – typical analog or digital circuit fragments – complete IC’s. For this purpose, a universal compact SOI/SOS MOSFET model for SPICE simulation software with account for TID, dose rate and single event effects is developed. The model parameters extraction procedure is described in great depth taking into consideration radiation effects and peculiarities of novel radiation-hardened (RH) SOI/SOS MOS structures. Examples of radiation-induced fault simulation in analog and digital SOI/SOS CMOS LSI’s are presented for different types of radiation influence. The simulation results show the difference with experimental data not larger than 10–20% for all types of radiation.     

Circuit Design of a High Speed and Low Power CMOS Continuous-time Current Comparator

Current comparator is a fundamental component of current-mode analog integrated circuits. A novel high-performance continuous-time CMOS current comparator is proposed in this paper, which comprises one CMOS complementary amplifier, two resistive-load amplifiers and two CMOS inverters. A MOS resistor is used as the CMOS complementary amplifier's negative feedback. Because the voltage swings of the CMOS complementary amplifier are reduced by low input and output resistances, the delay time of the current comparator is shortened. Its power consumption can be reduced rapidly with the increase of input current. Simulation results based on 1.2 m CMOS process model show the speed of the novel current comparator is comparable with those of the existing fastest CMOS current comparators, and its power consumption is the lowest, so it has the smallest power-delay product. Furthermore, the new current comparator occupies small area and is process-robust, so it is very suitable to high-speed and low-power applications.     

环栅结构CMOS/SOI器件SPICE模型研究

建立了环栅结构的CMOS/SOI器件的SPICE模型,可以对抗辐照设计中环栅结构的CMOS/SOI器件计算其等效宽长比,将环栅器件转换为等效宽度和长度的条栅器件;以及对体接触电阻等其他受影响的SPICE模型参数做出调整,使其电学特性模拟达到最准确精度.模拟数据和试验数据具有很好的一致性,证明所建立的模型具有较高的精度.     

Performance and Vdd scaling in deep submicrometer CMOS

Analytical models on metal-oxide-semiconductor field-effect transistor (MOSFET) scaling and complementary (CMOS) ring oscillator performance developed recently are applied to revisit CMOS design guidelines because those based on the basic long channel model are obsolete. Handy and empirical equations for deep submicrometer MOSFET drain saturation current are developed. The differences between the basic long channel model and the accurate deep submicrometer MOSFET current model are highlighted. Design guidelines on V_th and V _dd scaling as well as interconnect loading effects based on the accurate models are presented     

New Delay-Time Measurements on a 64-kb Josephson–CMOS Hybrid Memory With a 600-ps Access Time

A 64-kb subnanosecond Josephson–CMOS hybrid random-access memory (RAM) has been developed with ultrafast hybrid interface circuits. The hybrid memory is designed and fabricated using a commercial 0.18- $muhbox{m}$ CMOS process and NEC-SRL's 2.5- $hbox{kA/cm}^{2}$ Nb process for Josephson circuits. The millivolt-level Josephson signals are amplified to volt-level CMOS digital signals by a hybrid interface amplifier, which is the most challenging part of the memory system. The performance of this amplifier is optimized by minimizing its parasitic capacitance loading. The 4-K operation of short-channel CMOS devices and circuits is reviewed, and a complete 4-K CMOS BSIM3 model, which has been verified by experiments, is discussed. The memory bit-line output currents are detected by ultralow-power high-speed Josephson devices. Here, we report the first high-frequency access-time measurements on the full critical path showing 600 ps for a single bit. We discuss future designs made to reduce the crosstalk and improve margins, as well as plans to reduce power dissipation and latency.      

Delay and Power Expressions for a CMOS Inverter Driving a Resistive-Capacitive Load

A delay and power model of a CMOS inverter driving aresistive-capacitive load is presented. The model is derivedfrom Sakurais alpha-power law and exhibits good accuracy. Themodel can be used to design and analyze those CMOS invertersthat drive a large RC load when considering bothspeed and power. Expressions are provided for estimating thepropagation delay and transition time which exhibit less than27% discrepancy from SPICE for a wide variety of RCloads. Expressions are also provided for modeling the short-circuitpower dissipation of a CMOS inverter driving a resistive-capacitiveinterconnect line which are accurate to within 15% of SPICEfor most practical loads.     

Wide-band CMOS cascode low-noise amplifier design based on source degeneration topology

A design methodology for a wide-band CMOS low noise amplifier (LNA) with source degeneration is presented. By allowing an arbitrary source degeneration and employing a general input matching network, the proposed wide-band CMOS LNA can be shown for any choice of transistor width to achieve the minimum noise figure at all frequencies of interest. The transistor width simply affects the gain of the LNA at the cost of power dissipation. These results apply uniquely to CMOS LNAs, as they are derived from a quasi-static MOSFET model. To validate these design concepts, a wide-band LNA was realized in 0.25-/spl mu/m CMOS technology. The measured noise figure ranges from 2.7 to 3.7 dB over 3.2-4.8 GHz with power consumption of 20 mW. A close agreement with the theoretical results is observed.     

Switching characteristics of scaled CMOS circuits at 77 K

Performance enhancement of CMOS inverters at room and liquid-nitrogen temperatures are studied. The extent of delay improvement at low temperature is limited by the velocity saturation effect, as the channel lengths are decreased and/or the supply voltage increased. An analytical delay model taking into account velocity saturation is developed that accurately predicts the measured delay of CMOS inverter chains with drawn channel lengths down to 0.5 µm, Compared are the relative merits of CMOS devices operating at 77 K and those scaled for room-temperature operations.     

Modelling of hot-carrier degradation and its application for analog design for reliability

An analytical CMOS transistor ageing model is presented and a new procedure that allows the extraction of its parameters are presented in this paper. Then, we show how this model can be used to forecast and understand the drifts of the main characteristics of a CMOS circuit. Further, we demonstrate that this model can also be used to help the analog designer to choose and/or modify a circuit in order to minimise the hot-carrier induced degradations. Finally, we use an ageing simulation tool realised in VHDL-AMS to validate the analytical study, and we present our first experimental results.