3D IC-TSV技术与可靠性研究

对三维(3 Dimension,3D)堆叠集成电路的硅通孔(Through Silicon Via,TSV)互连技术进行了详细的介绍,阐述了TSV的关键技术与工艺,比如对准、键合、晶圆减薄、通孔刻蚀、铜大马士革工艺等。着重对TSV可靠性分析的重要性、研究现状和热应力分析方面进行了介绍。以传热分析为例,实现简单TSV模型的热仿真分析和理论计算。最后介绍了TSV技术市场化动态和未来展望。     

应用于MOEMS集成的TSV技术研究

硅通孔(TSV)通过缩短互连长度可实现低延迟、低功耗等目的。对应用于微光机电系统(MOEMS)集成的TSV工艺进行了研究,通过ICP-DRIE参数优化获得了陡直TSV通孔;通过金-金键合及bottom-up法,实现了TSV的无缺陷填充;对填充后的TSV进行电学表征,测试结果表明,单个TSV的电阻平均值为0.199Ω、相邻两个TSV的电容在无偏压时为170.45 fF、TSV的漏电流在100 V时为9.43 pA,具有良好的电学特性。     

TSV可靠性综述

对硅通孔(Through Silicon Via,TSV)技术的可靠性进行了综述,主要分为三个方面:热应力,工艺和压阻效应。TSV热应力可靠性问题体现在不同材料之间的热膨胀系数差异较大,过大的热应力可能导致界面分层和裂纹;TSV工艺可靠性体现在侧壁的连续性以及填充铜的质量;有源区中载流子的迁移率会受到TSV热应力的影响。在TSV周围规定一个保持区域(Keep-Out Zone, KOZ)。KOZ设置为载流子迁移率不超过5%的区域。当载流子迁移率超过5%,可能会导致电路的时序被破坏,使集成电路失效。     

红外焦平面硅基通孔加工及电极互连技术

通过硅通孔技术实现红外焦平面电极垂直互连,提高像元占空比,缩短了互连引线长度,降低了信号延迟。用单晶硅湿法刻蚀方法形成通孔,利用直写技术将耐高温Ag-Pd导体浆料填充通孔,实现红外焦平面阵列底电极与硅基片背面倒装焊凸点互连。     

用于微惯性器件的ICP刻蚀工艺技术

在微惯性器件加工中,ICP深硅刻蚀技术主要用于梳齿结构的释放.工艺试验中的梳齿结构的最细线条尺寸为2μm,刻蚀深度为40μm,刻蚀的深宽比为20∶1,接近刻蚀设备A601E的加工极限.为了提高刻蚀精度,减小根切和底切效应,本文介绍了一种实现微结构刻蚀的ICP分步工艺的新方法,采用不同的刻蚀工艺条件,初始阶段减小底切效应,减小线条损失,刻蚀的中间阶段保证刻蚀速度,刻蚀的最终阶段减小侧向刻蚀,提高结构释放的一致性.同时通过在刻蚀结构的背面生长200 nm厚Al膜对等离子体的吸附作用减小了根切效应,提高了刻蚀的精度和结构释放的一致性.     

应用于激光雷达的二维静电微镜设计

设计了一种应用于激光雷达的二维静电驱动谐振式微机电系统(MEMS)扫描微镜.基于MEMS技术对微镜加工工艺进行设计,简化了电隔离槽制备工艺,利用在绝缘体上硅(SOI)晶圆顶层硅刻蚀微镜结构的同时刻蚀电隔离槽,无需填充绝缘材料,实现动静梳齿的电绝缘;利用SOI晶圆底层硅的背面刻蚀结构,实现机械结构的连接,保证二维微镜结构...     

硅基材料的各向异性刻蚀工艺研究

穿透硅通孔技术是实现3-D集成封装的关键技术之一,而交替复合深刻蚀技术是实现穿透硅通孔的重要方式。本文分别采用SF6和CF4、SF6和C4F8、SF6和O2三组不同组合气体,对硅基材料进行交替复合深刻蚀,获得了不同组合气体对硅的横向刻蚀速率和纵向刻蚀速率,实现了对硅的各项异性刻蚀,为硅深刻蚀技术的实现奠定了基础。     

以密度为导向的3D芯片的布局设计

3D芯片通过垂直集成提高了芯片的集成度,成为当前半导体产业发展最快的技术之一,被认为是一种延续摩尔定律增长趋势的新方法。硅通孔（TSV）设计是3D芯片设计的关键技术,其可靠性是影响3D芯片良率的主要因素。针对3D芯片的TSV结构进行研究,为多个垂直堆叠裸晶设计密度为导向的TSV布局结构,为后续TSV容错设计提供基础。     

一种多链式结构的3D-SIC过硅通孔（TSV）容错方案

三维（3-Dimensional,3D）电路由于其更高的密度、更高的传输速率及低功耗的优点逐渐受到人们的重视和研究,而硅通孔（Through Silicon Via,TSV）技术是三维电路中互联上下层不同模块的主要方法之一。然而由于制造工艺水平的限制,在芯片制作完成后会出现一些失效TSV,这些失效TSV会导致由其互联的模块失效甚至整个芯片的失效。提出了一种多链式的硅通孔容错方案,通过将多个TSV划分为一个TSV链,多个TSV链复用冗余TSV的方法修复失效TSV。通过相关实验显示,该方案在整体修复率达到90%以上的情况下可以较大地减少冗余TSV增加的个数和面积开销。     

硅通孔键合硅片预对准边缘信息采集与处理

研究硅通孔即TSV(through-silicon vias)键合硅片的预对准边缘信息采集与处理方法。TSV硅片与标准硅片相比,有减薄、键合不同心、边缘毛刺多、存在崩边;缺口被填充、内有鼓胶、镀铜等工艺特点,使得传统基于线阵CCD一维图像采集与处理预对准方法失败。针对TSV硅片的特点,把线阵CCD配合扫描运动采集的一维原始图像集拼接获得二维图像,应用二维图像处理技术提取边缘信息,硅片整周边缘数据用最小二乘圆拟合算法识别出圆心位置,缺口边缘数据用Hough直线变换识别出缺口两条斜边,其交点定位为缺口位置,从而实现TSV硅片的自动预对准。实际测量表明,该方法预对准重复性定位精度<20um、预对准时间<40s,满足指标需求,为光刻机能够曝光TSV硅片提供有力支持。     

A low-cost through via interconnection for ISM WLP

Wafer level packaging (WLP) for image sensor device has the advantage of small size, high performance and low cost. In WLP technology, in order to form electrical interconnection from image sensor contact pad to the backside of the wafer, several structures have been developed, such as T-contact and through silicon via (TSV). In this paper, a wafer level package of image sensor with new type TSV electrical interconnection for image sensor pad is presented. The target of this development is to reduce process cost and difficulty, and increase yield of image sensor packaging. Key fabrication processes includes glass protecting wafer bonding, device wafer thinning, backside through via etching, via passivation layer deposition, pad oxide opening, via filling and backside re-routing layer formation, etc. Compared to large opening area of tapered via on the backside of CMOS image sensor wafer, only small opening area is need for making via interconnection with vertical sidewall presented in this paper. A fillet structure at bottom corner of via holes can help to reduce sequent process difficulty, so that low-cost and simplified unit processes are successfully adopted in the fabrication process for through via formation. The through via interconnection shows good electrical connection performance, and high-quality photo images are obtained by packaged image sensor device.     

三维芯片中TSV链式冗余修复电路的设计与实现

由于具有高集成度、高性能及低功耗等优点,三维芯片结构逐渐成为超大规模集成电路技术中的热门研究方向之一。TSV是三维芯片进行垂直互连的关键技术,然而在TSV的制作或晶圆的减薄和绑定过程中都可能产生TSV故障,这将导致与TSV互联的模块失效,甚至整个三维芯片失效。提出了一种基于TSV链式结构的单冗余/双冗余修复电路,利用芯片测试后产生的信号来控制该修复电路,将通过故障TSV的信号转移到相邻无故障的TSV中进行传输,以达到修复失效TSV的目的。实验结果表明,该电路结构功能正确,在面积开销较低的情况下,三维芯片的整体修复率可达91.97%以上。     

Process development of a novel wafer level packaging with TSV applied in high-frequency range transmission

The process development of a novel wafer level packaging with TSV applied in high-frequency range transmission is presented. A specially designed TSV structure (a core TSV and six shielding TSVs) is adopted to connect the components on different sides of the high-resistivity silicon wafer. And the microstrip line in the microwave monolithic integrated circuit is used to transmit high-frequency signal in packaging structure together with the low permittivity intermediate dielectric polymer, benzocyclobutene. The TSV fabrication process and the multi-layer interconnection is illustrated in details. The electrical measurement result of the microstrip lines connected by TSVs reveals the resistances within 0.719 Ω, a return loss better than 23.8 dB and an insertion loss better than 2.60 dB from 14 to 40 GHz.     

一种用于硅通孔的阻挡层和种子层一体化制备工艺研究

介绍了一种硅通孔中阻挡层和种子层制备的新型工艺方法。利用磁控溅射的方法在SiO2上沉积1μm的Ti膜。表层的Ti膜湿法氧化后作为种子层,底层Ti膜作为阻挡层。填充材料选择Cu,利用电镀的方法填充。利用热退火的方法来测试Cu的扩散性能,即Ti膜的阻挡特性,热退火试验选择350,400,450℃三种不同的温度。XPS结果表明:在400℃及以下温度阻挡层成功阻挡了Cu的扩散。目前已在硅通孔中初步实现此种结构并完成通孔中Cu的填充。     

Evaluation of Si liquid cooling structure with microchannel and TSV for 3D application

The development of 3D integration has caused a major technology paradigm shift to all integrated circuit (IC) devices, interconnects, and packages. Despite the benefits of 3D integration, this process faces the key challenge of thermal management, especially for high power and high density IC devices. Due to the limitations of conventional thermal solutions, liquid cooling technology has become a field of great interest for IC thermal management. In this study, an on-chip liquid cooling module with three different through Si vias (TSVs) and a fixed microchannel structure has been fabricated on an Si wafer using deep reactive ion etching and anodic bonding, followed by a grinding and dicing process. Pressure drop, coolant flow, and temperature difference before and after liquid flow were experimentally measured. TSV depth and diameter have been shown to have little effect on the change of pressure drop; however, shallower TSV depth and larger TSV diameter led to improved liquid cooling performance. The trapezoidal TSV showed slightly more effective cooling than did the scalloped TSV or the straight TSV.

     

3D System-on-Chip technologies for More than Moore systems

3D integration is a key solution to the predicted performance problems of future ICs as well as it offers extreme miniaturization and cost-effective fabrication of More than Moore products. Through silicon via (TSV) technologies enable high interconnect performance compared to 3D packaging. At present TSVs are associated with a relatively high fabrication cost, but research world wide strive to bring the cost down to an acceptable level. An example of a 3D System-on-Chip (3D-SOC) technology is to introduce a post backend-of-line TSV process as an optimized technology for heterogeneous system integration. The introduced ICV-SLID process, that combines both TSVs and bonding, enables 3D integration of fabricated devices. Reliability issues related to thermo-mechanical stress caused by the TSV formation and the bonding are considered. 3D-SOC technology choices made to realize a heterogeneous ultra-small IC stack for a wireless tire pressure monitoring system (TPMS) as an automotive application are described.     

Through-silicon via technologies for interconnects in RF MEMS

In this paper, we describe the application of through-silicon via (TSV) interconnects in Radio Frequency Micro-electro-mechanical systems (RF MEMS). Using TSV technologies as grounding connections, a Ku band miniature bandpass filter is designed and fabricated. Measured results show an insertion loss of 1.9 dB and a bandwidth of 20%. The chip size is 9.6 × 4 × 0.4 mm³. Using TSV as interconnections for 3 dimensional millimeter-wave integrated circuits, a silicon micromachined vertical transition with three layers is presented. TSV, alignment, bonding and wafer thinning technologies are used to fabricate the sample. This transition has an insertion loss of less than 6.7 dB from 26 to 34 GHz and its amplitude variation is less than 2 dB. The total size of the chip is 6.3 × 3.2 mm².     

基于链式的信号转移冗余TSV方案

三维集成电路（3D IC）带来了诸多的益处,譬如高带宽,低功耗,外形尺寸小。基于硅通孔的三维集成得到了行业的广泛采用。然而,硅通孔的制造过程引入了新的缺陷机制。一个失效的硅通孔会使整个芯片失效,会极大地增加成本。增加冗余硅通孔修复失效硅通孔可能是最有效的提高良率的方法,但是却带来了面积成本。提出了一种基于链式的信号转移冗余方案,输入端从下一分组选择信号硅通孔传输信号。在基于概率模型下,提出的冗余结构良率可以达到99%,同时可以减少冗余TSV的数目。     

基于LabVIEW的过电压在线检测仪

过电压在线检测仪主要用于变电站过电压在线检测,能自动追踪、并以较高的采样速率和采样深度记录内外过电压的波形、幅值及相关信息,并可查询已保存的过电压历史数据,同时实现对波形的多种操作;过电压在线检测仪采用电容分压器和NI公司的图形化编程软件LabVIEW等组成;经过运行证明该装置运行正常、稳定、可靠,能在过电压发生时完整、准确地同时记录下六路瞬态过电压信号,为更好的绝缘配合、修订绝缘水平提供有力参考。     

多路数字绝缘电阻测试仪的设计

为了准确可靠地实现电气设备绝缘电阻多路巡回检测,提出了基于PC/104总线的数字绝缘电阻测试仪的结构和系统硬件、软件设计方案;系统选择反激式单片开关电源设计方案,产生250V直流测试电压;采用光电微电子继电器开关电路,检测24路绝缘电阻;采用线性隔离放大电路,提高系统安全性;实现了多路绝缘电阻的巡回检测和自动量程转换功能,绝缘故障时准确报警;实验结果表明,该仪表满足测量多路绝缘电阻的要求,缩短了测试时间,提高了测试效率,运行性能良好.