A low-power 72.8-GHz static frequency divider in AlInAs/InGaAs HBTtechnology

We report a 72.8-GHz fully static frequency divider in AlInAs/InGaAs HBT IC technology. The CML divider operates with a 350-mV logic swing at less than 0-dBm input power up to a maximum clock rate of 63 GHz and requires 8.6 dBm of input power at the maximum clock rate of 72.8 GHz. Power dissipation per flip-flop is 55 mW with a 3.1-V power supply. To our knowledge, this is the highest frequency of operation for a static divider in any technology. The power-delay product of 94 fJ/gate is the lowest power-delay product for a circuit operating above 50 GHz in any technology. A low-power divider on the same substrate operates at 36 GHz with 6.9 mW of dissipated power per flip-flop with a 3.1-V supply. The power delay of 24 fJ/gate is, to our knowledge, the lowest power-delay product for a static divider operating above 30 GHz in any technology. We briefly review the requirements for benchmarking a logic family and examine the historical trend of maximum clock rate in high-speed circuit technology     

Fully ECL-compatible GaAs standard-cell library

A standard cell library for MSI circuits is described. It is based on buffered FET logic (BFL) with 1-μm gate-length MESFET transistors. It contains gates, buffers, master-slave flip-flops, and ECL interfaces and it has been optimized to operate over the military temperature range. It is fully compatible with ECL circuits (signal level and power supply). Typical propagation delay is 80 ps for an inverter (FI=FO=1) and power dissipation is 5 mW per BFL cell. A realistic printed circuit board for test and demonstration is proposed     

Diode-HBT-logic circuits monolithically integrable with ECl/CMLcircuits

A novel logic approach, diode-HBT logic (DHL), that is implemented with GaAlAs/GaAs HBTs and Schottky diodes to provide high-density and low-power digital circuit operation is described. This logic family was realized with the same technology used to produce emitter-coupled-logic/current-mode-logic (ECL/CML) circuits. The logic operation was demonstrated with a 19-stage ring oscillator and a frequency divider. A gate delay of 160 ps was measured with 1.1 mW of power per gate. The divider worked properly up to 6 GHz. Layouts of a DHL flip-flop and divider showed that circuit area and transistor count can be reduced by about a factor of 3, relative to ECL/CML circuits. The new logic approach allows monolithic integration of high-speed ECL/CML circuits with high-density DHL circuits with high-density DHL circuits     

GaAs DCFL超高速集成电路研究

直接耦合场效应逻辑（ＤＣＦＬ）具有简单的结构、良好的速度／功耗性能，是ＧａＡｓＦＥＴＬＳＩ电路中一种重要的逻辑形式。传统Ｅ／Ｄ型ＤＣＦＬ电路具有较低的成品率和较差的温度特性，本文研究了改进的Ｅ／Ｅ型ＤＣＦＬ电路。对Ｅ／Ｄ、Ｅ／Ｅ型ＤＣＦＬ电路的直流、瞬态及温度特性进行了分析、模拟和比较，Ｅ／Ｅ逻辑具有良好的高温性能。经优化设计，最后制作出单门延迟约１００ｐｓ、单门功耗约１ｍＷ的Ｅ／Ｄ和Ｅ／Ｅ型ＤＣＦＬ电路，且Ｅ／Ｅ型电路较Ｅ／Ｄ型电路具有更高的成品率。     

A high-speed, low-power divide-by-4 frequency divider implementedwith AlInAs/GaInAs HBT's

The authors describe the first frequency divider demonstrated using AlInAs/GaInAs heterojunction bipolar transistors (HBTs). The divider (a static 1/4 divider circuit) operates up to a maximum frequency of 17.1 GHz, corresponding to a gate delay of 29 ps for a bilevel current-mode logic (CML) gate with a fan-out of 2, and a total power consumption of 67 mW (about 4.5 mW per equivalent NOR gate). These results demonstrate the potential of AlInAs/GaInAs HBTs for implementing low-power, high-speed integrated circuits     

39.5-GHz static frequency divider implemented in AlInAs/GaInAs HBTtechnology

A static divide-by-4 frequency divider operating at 39.5 GHz with a corresponding gate delay of 12.6 ps was implemented using InP-based HBT technology. The AlInAs/GaInAs HBT devices utilized in the divider incorporated a graded emitter-base (E-B) junction and had a unity gain cutoff frequency, maximum frequency of oscillation, and current gain β of 130 GHz, 91 GHz, and 39, respectively. The divider was operated with a 3-V power supply and consumed a total power of 425 mW (77 mW per flip-flop). The divider functional yield was over 90%. The operating frequency of this circuit is the highest ever reported for a static divider     

Complementary AlGaAs/GaAs HBT I2L (CHI2L)technology

The monolithic integration of non-self-aligned AlGaAs/GaAs N-p-n and P-n-p HBTs with selective organometallic vapor-phase epitaxy (OMVPE) has been utilized to demonstrate a low-power high-speed integrated injection logic (I²L) technology. Seventeen-stage ring oscillators with a logic swing of 0.7 V exhibited a delay of 65 ps per gate with power dissipation of 13 mW per gate for a speed-power product of 850 fJ. This value was in excellent agreement with SPICE simulations based on extracted device parameters which predicted a speed-power product of 840 fJ. Additional simulations predicated a 28-fJ speed-power product and more than a factor of 2 reduction in gate delay with improved epitaxial design and use of submicrometer emitters and self-aligned processing     

A high-speed high-density silicon 8/spl times/8-bit parallel multiplier

An 8/spl times/8-bit parallel multiplier with submicrometer gate lengths has been fabricated using silicon NMOS technology. The multiplication time is 9.5 ns. This corresponds to an average loaded gate delay in the multiplier circuit of 244 ps/gate, which the authors believe is the shortest gate delay for MOS multiplier circuits demonstrated to date. The power dissipation is 600 mW at a supply voltage of 5 V. The multiplier circuit has a total of 1427 transistors in an active area of 0.61/spl times/0.58 mm/SUP 2/, corresponding to a gate density of 1125 gates/mm/SUP 2/.     

Advantages of metallic-amorphous-Silicon-gate FET's in GaAs LSI applications

A Schottky barrier as high as 1 V is obtained for contact between a ternary amorphous film, a-Si-Ge-B, and an n-type GaAs crystal. A metallic-amorphous-silicon-gate FET (MASFET) was made using the amorphous film as a gate contact. GaAs MASFET characteristics are superior to GaAs MESFET characteristics in application to LSI's with a DCFL configuration because the DCFL circuits with the GaAs MASFET's provide a logic level as high as 0.94 V and widen the circuit operation margin. Full operation is obtained from a 1 Kword × 2 bit SRAM with GaAs MASFET's, which is considered to be mainly due to the wide operation margin. The measured propagation delay time of the DCFL inverter is 34 ps at supply voltageV_{DD} = 1.5V and power consumption of 1.9 mW/gate.     

InP HBT integrated circuit technology with selectively implanted subcollector and regrown device layers

We describe a quasi-planar HBT process using a patterned implanted subcollector with a regrown MBE device layer. Using this process, we have demonstrated discrete SHBT with f/sub t/>250 GHz and DHBT with f/sub t/>230 GHz. The process eliminates the need to trade base resistance for extrinsic base/collector capacitance. Base/collector capacitance was reduced by a factor of 2 over the standard mesa device with a full overlap between the heavily doped base and subcollector regions. The low proportion of extrinsic base/collector capacitance enables further vertical scaling of the collector even in deep submicrometer emitters, thus allowing for higher current density operation. Demonstration ring oscillators fabricated with this process had excellent uniformity and yield with gate delay as low as 7 ps and power dissipation of 6 mW/CML gate. At lower bias current, the power delay product was as low as 20 fJ. To our knowledge, this is the first demonstration of high-performance HBTs and integrated circuits using a patterned implant on InP.     

High-speed bipolar logic circuits with low power consumption for LSI-a comparison

Various high-speed bipolar logic circuits (CML, FECL, NTL, TTL, STL) are investigated and compared which exhibit gate delays far below 1 ns, even at a very low power dissipation per gate (e.g. 0.1 mW). Therefore, these circuits are best suited for LSI. It is shown that, by tailoring the circuit components (transistors, Schottky diodes) to the power dissipation P, the expected increase of the gate delay t/SUB D/ according to t/SUB D/~1/P can be shifted to surprisingly low values of P. Further, the simulations show that the Schottky clamp technique has considerable advantages concerning the switching speed at very low power dissipations, compared with the current-mode logic known to be fast. The results are explained by simple calculations.     

低耗高速互补型CML电路

本文给出一种互补型ＣＭＬ电路，该电路可以工作在很低的功耗下，具有很高的开关速度。ｍｗＳＰＩＣＥ仿真结果表明，单门功耗为０．５ｍＷ和０．２ｍＷ时，平均门延时可分别低达１８ｐｓ和３０．５ｐｓ。     

A GaAs low-power normally-on 4-bit ripple carry adder

The realization and performance of a low-power buffered FET logic (1p-BFL) 4 bit ripple carry adder is reported. Performance measurements indicate a critical path average propagation delay of 1.9 ns at a total power dissipation of 45 mW, output buffers included (27 mW without). This corresponds to an average propagation delay of 380 ps/gate (FI/FO=/SUP 5///SUB 3/), an average power consumption of 1.56 mW/gate, and a power-delay product of 0.6 pJ. Best speed performance biasing conditions yield a 1.25 ns critical path average propagation delay at a total power dissipation of 180 mW (180 mW excluding buffers), which corresponds to an average gate delay, power consumption and power-delay product of 250 ps, 6 mW, and 1.5 pJ, respectively. Standard cell layout techniques yield an average gate density of 200 gates/mm/SUP 2/, interconnection wiring included.     

Ultra-high-speed digital circuit performance in 0.2-μmgate-length AlInAs/GaInAs HEMT technology

The fabrication of fifteen-stage ring oscillators and static flip-flop frequency dividers with 0.2-μm gate-length AlInAs/GaInAs HEMT technology is described. The fabricated HEMT devices within the circuits demonstrated a g_m transconductance of 750 mS/mm and a full-channel current of 850 mA/mm. The measured cutoff frequency of the device is 120 GHz. The shortest gate delay measured for buffered-FET-logic (BFL) ring oscillators at 300 K was 9.3 ps at 66.7 mW/gate (fan-out=1); fan-out sensitivity was 1.5 ps per fanout. The shortest gate delay measured for capacitively enhanced logic (CEL) ring oscillators at 300 K was 6.0 ps at 23.8 mW/gate (fan-out=1) with a fan-out sensitivity of 2.7 ps per fan-out. The CEL gate delay reduced to less than 5.0 ps with 11.35-mW power dissipation when measured at 77 K. The highest operating frequency for the static dividers was 26.7 GHz at 73.1 mW and 300 K     

Gate-length dependence of the speed of SSI circuits using submicrometer selectively doped heterostructure transistor technology

Frequency dividers and ring oscillators have been fabricated with submicrometer gates on selectively doped AIGaAs/GaAs heterostructure wafers. A divide-by-two frequency divider operated up to 9.15 GHz at room temperature, dissipating 25 mW for the whole circuit at a bias voltage of 1.6 V, with gate length ∼ 0.35 µm. A record propagation delay of 5.8 ps/gate was measured for a 0.35-µm gate 19- stage ring oscillator at 77 K, with a power of 1.76 mW/gate, and a bias voltage of 0.88 V. The maximum switching speed at room temperature was 10.2 ps/gate at 1.03 mW/gate and 0.8 V bias, for a ring oscillator with the same gate length. With a range of gate lengths on the same wafer fabricated by electron-beam lithography, a clear demonstration of gate-length dependence on the propagation delay was observed for both dividers and ring oscillators.     

Process integration and device performance of a submicrometerBiCMOS with 16-GHz ft double poly-bipolar devices

Submicrometer-channel CMOS devices have been integrated with self-aligned double-polysilicon bipolar devices showing a cutoff frequency of 16 GHz. n-p-n bipolar transistors and p-channel MOSFETs were built in an n-type epitaxial layer on an n⁺ buried layer, and n-channel MOSFETs were built in a p-well on a p⁺ buried layer. Deep trenches with depths of 4 μm and widths of 1 μm isolated the n-p-n bipolar transistors and the n- and p-channel MOSFETs from each other. CMOS, BiCMOS, and bipolar ECL circuits were characterized and compared with each other in terms of circuit speed as a function of loading capacitance, power dissipation, and power supply voltage. The BiCMOS circuit showed a significant speed degradation and became slower than the CMOS circuit when the power supply voltage was reduced below 3.3 V. The bipolar ECL circuit maintained the highest speed, with a propagation delay time of 65 ps for C_L=0 pF and 300 ps for C_L=1.0 pF with a power dissipation of 8 mW per gate. The circuit speed improvements in the CMOS circuits as the effective channel lengths of the MOS devices were scaled from 0.8 to 0.4 μm were maintained at almost the same ratio     

A 6 K-gate GaAs gate array with a new large-noise-margin SLCF circuit

A 6 K-gate GaAs gate array has been successfully designed and fabricated using a novel large-noise-margin Schottky-diode level-shifter capacitor-coupled FET logic (SLCF) circuitry and a WN/SUB x/ gate selfaligned lightly doped drain (LDD) structure GaAs MESFET process. Chip size was 8.0/spl times/8.0 mm/SUP 2/. A basic cell can be programmed as an SLCF inverter, a two-input NOR, or a two-input NAND gate. The unloaded propagation delay time was 76 ps/gate a 1.2-mW/gate power dissipation. The increases in delay time due to various loading capacitances were 10 ps/fan-in, 45 ps/fan-out, and 0.64 ps/IF. A 16-b serial-to-parallel-to-serial (S/P/S) data-conversion circuit was constructed on the gate array as an application example. A maximum operation frequency of 852 MHz was achieved at a 952-mW power dissipation, including I/O buffers.     

Dual material gate silicon on insulator junctionless MOSFET for low power mixed signal circuits

In this research paper, demonstrates, the logic performance of n and p channel complementary metal oxide semiconductor (CMOS) circuits implemented with dual material gate silicon on insulator junctionless transistor (DMG SOI JLT). The logic performance of a CMOS circuit is evaluated in terms of static power dissipation, voltage transfer characteristic, propagation delay and noise margin. The gate capacitance is less as compared to gate capacitance of DMG SOI transistor in saturation. The power dissipation for CMOS inverter of DMG SOI JLT is improved by 25% as compared to DMG SOI transistor. The DMG SOI JLT common source amplifier has 1.25 times amplification as that of DMG SOI transistor. The noise margin of DMG SOI JLT CMOS inverter is improved by 23% as compared to the DMG SOI transistor CMOS inverter. The NAND gate static power dissipation of DMG SOI JLT is found improved imperically as compared to DMG SOI transistor for various channel length. The improvement obtained is 53% for 20nm, 46% for 30nm and 34% for 40nm respectively. Static power dissipation of DMG SOI JLT inverter is reduced by 3% as compared to junction transistor inverter at channel length of 30nm.     

A 30-ps Josephson current injection logic (CIL)

A family of novel Josephson logic circuits called current injection logic (CIL) is presented. In contrast to previous approaches, it combines magnetically coupled interferometers with novel nonlinear injection gates to obtain ultra-fast logic speeds, wide margins, and greater fan-in and fan-out capabilities. Fastest logic delay of 30 ps/gate is measured averaged over two- and four-input OR and AND gates (average fan-in=4.5, average fan-out=2.5) fabricated using 2.5 /spl mu/m nominal design rules. The average power dissipation of these experimental circuits is 6 /spl mu/W/gate. An unprecedented logic delay of 13 ps/stage is measured on a chain of two-input OR gates, and the logic delay for a circuit consisting of two two-input OR gates, the outputs of which are `AND'ed, is measured at 26 ps. The experimental results are found to be in excellent agreement with delay estimates based upon computer simulations.     

Analysis of heterojunction bipolar transistor/resonant tunnelingdiode logic for low-power and high-speed digital applications

A high-speed digital logic family based on heterojunction bipolar transistors (HBTs) and resonant tunneling diodes (RTDs) is proposed. The negative differential resistance of RTDs is used to significantly decrease the static power dissipation. SPICE simulations indicate that propagation delay time below 150 ps at 0.09-mW static power per gate should be obtainable