Electrostatically actuated dip pen nanolithography probe arrays

Dip pen nanolithography (DPN) is a method of creating nanoscale chemical patterns on surfaces using an atomic force microscope (AFM) probe. Until now, efforts to increase the process throughput have focused on passive multi-probe arrays and active arrays based on thermal bimetallic actuation. This paper describes the first use of electrostatic actuation to create an active DPN probe array. Electrostatic actuation offers the benefit of actuation without the probe heating required for thermal bimetallic actuation. Actuator cross talk between neighboring probes is also reduced, permitting more densely spaced probe arrays. The array presented here consists of 10 cantilever probes, where each is 120 μm long and 20 μm wide. Each cantilever probe is actuated by the electrostatic force between the probe and a built-in counter electrode with a 20–25 μm gap. The tip-to-tip probe spacing, also called the array pitch, is 30 μm. Patterns of 1-octadecanethiol were created on gold surfaces to demonstrate single-probe actuation, simultaneous multi-probe actuation, and overlap of patterns from adjacent probes. The minimum line width was 25 nm with an average line width of 30–40 nm.     

Electrostatically actuated FGM micro-tweezer under the thermal moment

In previous studies, the mechanical behavior of a micro-tweezer with homogenous and the same material has been investigated. In this paper considering the desired characteristics of FGMs, as a good thermal and wear resistance, the mechanical behavior of FGM micro-tweezer under DC voltage and temperature variations is investigated. It is assumed that the two micro-beams of the FGM micro-tweezer are mounted symmetrically against each other and one side of the micro-beams is made of a pure metal the other side is a mixture of metal and ceramic, and the percentage of ceramic varies exponentially through the micro-beams thickness. The nonlinear equations governing the static deflection of micro-beams due to the application of DC voltage and the temperature changes are derived and solved using the step by step linearization method and the Galerkin method. The response and the stability of the system against the variation of DC voltage and temperature are investigated. Also, the effect of geometrical dimensions, ceramic percentage and its variations through the micro-beams thickness on the mechanical behavior and the system stability are studied.     

Fully integrated magnetically actuated micromachined relays

A fully integrated magnetically actuated micromachined relay has been successfully fabricated and tested. This particular device uses a single-layer coil to actuate a movable upper magnetically responsive platform. The minimum current for actuation was 180 mA, resulting in an actuation power of 33 mW. Devices have been tested which can make and break 1.2 A of current through the relay contacts when the relay is electromagnetically switched. Operational lifetimes in excess of 850000 operations have been observed. Contact resistances as low as 22.4 mΩ have been observed under electromagnetic actuation. Magnetic and structural finite-element (FE) simulations have been performed using ANSYS to calculate both the actuation and contact forces     

集成微流体测控芯片的研制

设计、研制了集成有微泵、微沟道、微流量传感器、温度传感器的微流体测控芯片.采用有限元软件ANSYS模拟分析了将其作为冷却芯片时微沟道的散热作用,分析确定了芯片上各元件的结构.该集成芯片为硅-玻璃结构,在硅片上,利用ICP法刻蚀无阀微泵泵体和微沟道;在7740玻璃片上,以溅射、剥离法制作微流量和温度传感器;图形精确对准后硅/玻璃以静电键合方法封接.无阀微泵采用压电元件驱动.测试结果表明:集成芯片具有冷却功能,循环水的流速最大可达25.4mm/s.     

CMOS options for single chip applications

Successfully realizing single-chip solutions often requires adding functions on top of the CMOS logic. This project researched the integration of nonvolatile memory and extra analog-optimized devices in 0.35-micron CMOS processes     

基于CMOS工艺钨微测辐射热计阵列集成芯片的设计与制作

采用0.5μm标准CMOS工艺和微机械加工工艺,设计并制作了低成本4×4钨微测辐射热计阵列集成芯片。阵列中每个钨微测辐射热计均由微悬桥结构和钨热敏电阻组成,CMOS读出电路集成在阵列下方。微悬桥结构由表面牺牲层技术实现,不需要任何的光刻工艺。钨微测辐射热计像元尺寸为100μm×100μm,填充因子为20%。测试结果表明,在真空环境下,钨微测辐射热计等效热导为1.31×10-4W/K,等效热容为1.74×10-7J/K,热时间常数为1.33 ms。当红外光源的斩波频率为10 Hz时,钨微测辐射热计的电压响应率为1.91×103V/W,探测率为1.88×107cm·Hz1/2/W。     

High speed ant colony optimization CMOS chip

Ant colony optimization (ACO) is an optimization computation inspired by the study of the ant colonies’ behavior. This paper presents design and CMOS implementation of the ant colony optimization based algorithm for solving the TSP problem. In order to implement ant colony optimization algorithm in CMOS, we will present a new algorithm. This algorithm is based on the original ant colony optimization but it can be implemented in CMOS. Briefly, pheromone matrix is transformed on the chip area and ants move up-down through the pheromone matrix and they make their decisions. Finally ants select a global path. In previous researches only pheromone values is used, but select the next city in this paper is based on heuristics value and pheromone value. In definition of problem, we use heuristics value as a matrix. Previous researches could not be used for wide type of optimization problem but our chip gives heuristics value initially and we can change initial value of heuristics value according to the optimization problem so this capability increases the flexibility of ACO chip. Simple circuit is used in blocks of our chip to increase the speed of convergence of ACO chip. We use Linear Feedback Shift Register (LSFR) circuit for random number generator in ACO chip. ACO chip has capability of solving the big TSP problem. ACO chip is simulated by HSPICE software and simulation results show the good performance of final chip.     

Implantable CMOS neuro-stimulus chip for visual prosthesis

A prototype chip with 2×2 pixels for implanting in blind patients affected by outer retinal degeneration is presented in this paper.This visual prosthesis chip imitates the degenerated photoreceptor cells,senses the incident light and stimulates the remaining healthy layers of retina or optic nerve.Each pixel integrates photodiode and stimulus pulse generator,converting the illumination on the eyes into 3-bit resolution bi-phasic current pulses.On-chip charge cancellation modules are used to discharge each ...     

一种对嵌入式加密芯片的增强DPA攻击方法*

针对传统DPA攻击方法需要波形数据精确对齐的缺点,提出了一种基于离散傅里叶变换的增强DPA攻击方法,并对目前常用的嵌入式芯片以DES加密算法为例进行了DPA攻击实验。实验结果表明采用这种增强的DPA攻击方法能够克服传统DPA攻击方法的缺点。     

集成毛细管电泳芯片的设计

利用ANSYS软件对集成毛细管电泳芯片微沟道内样品流动情况进行模拟,获得了不同进样模式下微沟道的结构与流体流速之间的关系,并以此为依据对芯片整体结构参数进行设计:毛细管沟道最终尺寸为宽度16μm,深度10μm,有效分离长度为3.5cm的圆角转弯形沟道,从而确定整个芯片设计。     

CMOS fully digital integrated pressure sensors

Most commercially available silicon pressure transducers are based on a Wheatstone bridge configuration and given an analogue output signal. These devices are generally very sensitive to noise and require complicated circuits (by using passive components) for temperature and non-linearity compensation. This limits the transducer accuracy and increases the calibration cost. To overcome these problems, a new generation of pressure transducers with digital output, based on MOSFET ring oscillators, has been developed. A fully digital integrated pressure sensor and data-acquisition procedures will be presented.     

Angular rate sensor and accelerometer combined on the same micromachined CMOS chip

 This paper describes an electroformed micromachining technology capable of producing both angular rate sensors and accelerometers. The sensors fabricated are CMOS integrated for improved signal output. Automotive applications for these devices will also be discussed. Received: 25 August 1997/Accepted: 23 October 1997     

Single core fully integrated CMOS micro-fluxgate magnetometer

A new fully integrated 2D micro-fluxgate magnetometer is presented. This magnetometer is integrated in a standard CMOS process and uses a ferromagnetic core integrated on the chip by a photolithographic post-process compatible with the integrated circuit technology. The cross-shaped ferromagnetic core is placed diagonally above four excitation coils, two for each measurement axis. A novel electronic signal extraction technique is presented. The integrated 2D magnetometer exhibits a sensitivity of 160 V/T and a linear range of ±50 μT. The magnetic equivalent noise spectral density is 70 nT/√Hz at 1 Hz, and the total power consumption is as low as 17 mW for the 5 V power supply.     

M-TEST: A test chip for MEMS material property measurement usingelectrostatically actuated test structures

A set of electrostatically actuated microelectromechanical test structures is presented that meets the emerging need for microelectromechanical systems (MEMS) process monitoring and material property measurement at the wafer level during both process development and manufacturing. When implemented as a test chip or drop-in pattern for MEMS processes, M-Test becomes analogous to the electrical MOSFET test structures (often called E-Test) used for extraction of MOS device parameters. The principle of M-Test is the electrostatic pull-in of three sets of test structures [cantilever beams (CB's), fixed-fixed beams (FB's), and clamped circular diaphragms (CD's)] followed by the extraction of two intermediate quantities (the S and B parameters) that depend on the product of material properties and test structure geometry. The S and B parameters give a direct measure of the process uniformity across an individual wafer and process repeatability between wafers and lots. The extraction of material properties (e.g., Young's modulus, plate modulus, and residual stress) from these S and B parameters is then accomplished using geometric metrology data. Experimental demonstration of M-Test is presented using results from MIT's dielectrically isolated wafer-bonded silicon process. This yielded silicon plate modulus results which agreed with literature values to within ±4%. Guidelines for adapting the method to other MEMS process technologies are presented     

An analog CMOS chip set for neural networks with arbitrarytopologies

An analog CMOS chip set for implementations of artificial neural networks (ANNs) has been fabricated and tested. The chip set consists of two cascadable chips: a neuron chip and a synapse chip. Neurons on the neuron chips can be interconnected at random via synapses on the synapse chips thus implementing an ANN with arbitrary topology. The neuron test chip contains an array of 4 neurons with well defined hyperbolic tangent activation functions which is implemented by using parasitic lateral bipolar transistors. The synapse test chip is a cascadable 4x4 matrix-vector multiplier with variable, 10-b resolution matrix elements. The propagation delay of the test chips was measured to 2.6 mus per layer.     

基于导航基带芯片的UART的设计和仿真

设计了一款带自动波特率检测且误差较小的UART模块,旨在获得良好的通信功能。该模块支持全双工的串行数据传输和红外通信功能,且支持DMA模式以减少CPU的占用时间。UART的发送和接收通道各有一个FIFO模块。最后,利用Verilog语言的硬件实现方法在FPGA平台上进行了验证。     

A disposable,integrated loop-mediated isothermal amplification cassette with thermally actuated valves

An inexpensive, disposable, integrated, polymer-based cassette for loop-mediated isothermal amplification (LAMP) of target nucleic acids was designed, fabricated, and tested. The LAMP chamber was equipped with single-use, thermally actuated valves made with a composite consisting of a mixture of PDMS and expandable microspheres. The effect of the composite composition on its expansion was investigated, and the valve’s performance was evaluated. In its closed state, the valve can hold pressures as high as 200 kPa without any significant leakage. Both the LAMP chamber and the valves were actuated with thin film heaters. The utility of the cassette was demonstrated by carrying out LAMP of Escherichia coli DNA target and reverse transcribed loop meditated isothermal amplification (RT-LAMP) of RNA targets. The amplicons were detected in real time with a portable, compact detector. The system was capable of detecting as few as 10 target molecules per sample in well under 1 h. The portable, integrated cassette system described here is particularly suited for applications at the point of care and in resource-poor countries, where funds and trained personnel are in short supply.     

一种电压输出型CMOS集成电容湿度传感器

设计一种湿度传感器。该传感器选用聚酰亚胺作为湿度传感器的感湿介质,采用叉指电容式结构以增加感湿灵敏度,以电荷转移电路为微电容测量电路,用0.35μm多晶硅栅进行设计,形成单片集成湿度传感器。整个组成电路均与CMOS工艺兼容。仿真结果表明:在测量激励方波激励下,片上湿度传感器在27℃下模拟显示出较好的直流电压输出特性。     

Development of an integrated CMOS DNA detection biochip

This paper presents a CMOS DNA detection biochip using an electrical detection method with self-assembly multilayer gold nanoparticles (AuNPs). Each measuring spot of this biochip consists of three major parts; a pair of electrodes with a nanogap, a current amplifier circuit, and a heater with an embedded temperature sensor. The biochip is first fabricated by a TSMC (Taiwan Semiconductor Manufacturing Company Ltd.) 0.35 μm 2P4M standard CMOS process. Then, post-CMOS micromachining etch processes are used to expose the surface of the nanogap to test samples for the establishment of multilayer AuNPs through hybridization between single strand DNAs in the samples. The gap distance between a pair of electrodes is 350 nm. Before taking DNA detection measurements, self-assembly monolayer AuNPs is established on the nanogap surface between two microelectrodes. Multilayer AuNPs can be observed if hybridization between single strand DNAs occurs. An approximately 1000-fold increase in electric current between the multilayer AuNPs over the monolayer AuNPs serves an indication of the presence of target DNA in test samples. After integrating the electrodes with an embedded current amplifier, the electric current of multilayer AuNPs is amplified to the order of mA that can be easily measured by a commercial Volt-Ohm-Milliammeter. The heating system with a heating element and a temperature sensor can be used to distinguish single base-pair mismatch hybridization from complementary hybridization for the establishment of multilayer AuNPs. The lowest detectable concentration of target DNA on this biochip is 0.1 nM.