Reactive ion etching of trenches in 6H-SiC

In this paper, we report the reactive ion etching (RIE) of trenches in 6H-silicon carbide using SF₆/O₂. The plasma parameters: etchant composition, gas flow rate, chamber pressure, and radio frequency power were optimized to obtain a maximum etch rate of 360Å/min. The etch rate of SiC was found to exhibit a direct correlation with the dc self bias except when the O₂ percentage was varied. Trenches were fabricated using the optimized conditions. It was found that the trench surface was extremely rough due to the aluminum micromasking effect. To overcome this effect, a Teflon^TM sheet was used to cover the cathode during the experiment. The trenches fabricated using this modification were found to have smooth etched surfaces and sidewalls. The angle of anisotropy of these trenches was approximately 80° which is suitable for device applications.     

耗尽型6H-SiC埋沟PMOSFET电流解析模型

在考虑到杂质的不完全离化作用时,建立了S iC埋沟PM O SFET在发生表面多子耗尽时的电流解析模型。实验结果和模拟结果的一致性说明了此模型的准确性。在300~600 K温度范围表面弱电场的条件下,由于杂质不完全离化作用得到充分体现,因此器件的工作状态有不同于常规模型下的特性;当温度升高时离化率的增大使得杂质的不完全离化作用得不到体现,所以文中模型的结果向常规模型的结果靠近,且都与实验结果接近。同时为了充分利用埋沟器件体内沟道的优势,对埋沟掺杂的浓度和深度也进行了合理的设计。     

Al+ and B+ implantations into 6H-SiC epilayers and application to pn junction diodes

Aluminum (Al) and boron (B) ion implantations at room temperature into n-type 6H-SiC epilayers have been investigated. Rutherford backscattering spectroscopy (RBS) channeling measurements revealed larger lattice damage in Al⁺ implantation at a given total implantation dose. A nearly perfect electrical activation ratio (>90%) could be attained by high-temperature annealing at 1600°C for Al⁺ and 1700°C for B⁺ implantations. Mesa pn junction diodes formed by either Al⁺ or B⁺ implantation with a 1×10¹⁴ cm⁻² dose exhibited high blocking voltages of 950∼1070 V, which are 80∼90% of the ideal value predicted for the diode structure. The forward current can clearly be divided into two components of diffusion and recombination currents. B⁺-implanted diodes showed higher breakdown voltage on average but poor forward conduction. Comparison of the performance of Al⁺ and B⁺-implanted diodes is discussed.     

Generation and annealing characteristics of paramagnetic centers in oxidized 3C-SiC and 6H-SiC

Electron paramagnetic resonance studies show that defects are activated in oxidized 3C-SiC and 6H-SiC by heat-treatments at temperatures greater than 800°C in dry (<1 ppm H₂O) N₂ or O₂ ambients. Annealing in forming gas (7% H₂, 93% N₂) at 700°C completely passivates the centers induced by the dry heat-treatment. By contrasting the generation and annealing kinetics for these centers with the well studied Si dangling bond, we suggest that the centers in the oxidized SiC are C dangling bonds created by hydrogen effusion during the dry heat-treatment.     

Effect of high-temperature processing on the creation of boron-related deep levels in 4H-SiC

High-temperature processing was applied to SiC boron-doped epitaxial layers, epitaxial layers grown on boron-rich substrates, and boron-implanted samples in order to establish conditions favorable for the formation of boron-related centers (D-centers) that introduce a deep level in SiC bandgap. Photoluminescence (PL) was used to detect and compare the formation of the D-center after different processing steps. It was confirmed that the presence of lattice defects was required for achieving significant boron diffusion and D-center formation. In addition, epitaxial growth on the top of a boron-implanted sample yielded efficient boron in-diffusion in the growing layer, which resulted in a material compensated with D-centers. The temperature dependence of the D-center formation efficiency was investigated.     

JTE结构4H-SiC肖特基二极管的研究

借助半导体仿真软件Silvaco,仿真一种具有结终端扩展（JTE）结构的碳化硅（SiC）肖特基二极管（SBD）。其机理是通过JTE结构降低肖特基结边缘的电场集中效应,从而优化肖特基二极管的反向耐压能力。研究JTE区深度、宽度及掺杂浓度对碳化硅肖特基二极管的反向耐压的影响。通过优化结终端结构的结构参数使碳化硅肖特基二极管的反向耐压特性达到更好的性能要求。     

Characteristics of Dislocation Half-Loop Arrays in 4H-SiC Homo-Epilayer

Dislocation “half-loop arrays” (HLAs) in 4H-SiC homo-epilayers are studied by molten KOH etching and atomic force microscopy (AFM). It is found that the dislocation half-loops in an array exist at different depths in the epilayer, and they are aligned roughly but not exactly perpendicular to the off-cut direction. These results indicate that the dislocation half-loops in an array are not formed simultaneously, but the array extends by generation of new half-loops during growth. It is also demonstrated that the HLAs can be artificially induced by creating strain in the material, followed by annealing.     

Photoluminescence and Electroluminescence Imaging of Carrot Defect in 4H-SiC Epitaxy

Electroluminescence (EL) and photoluminescence (PL) imaging techniques were successfully used to reveal defect features in 34 carrots in 4H-SiC epilayers. Because EL and PL techniques are nondestructive and require minimal sample preparations, many carrots can be examined over a reasonable time. Our findings showed that some carrots had the basic components consistent with the model proposed by Benamara et al., but also contained additional features beyond the basic components. Eight carrots contained multiple bright line features, and 25 out of 50 bright line features exhibited multiple line characteristics. Eleven carrots were discovered to contain basal plane faults (B’s) and the corresponding small stacking faults (S’s) near the carrot heads. Not all the carrots lie along the off-cut direction; a couple were oriented 5° from the off-cut. Of the seven carrots with shape lengths -200 μm, one had a corresponding bright line length of 370 μm. Based on this line length, the calculated depth of origin was about midway in the epilayer, while all of the other carrots originated from the substrate. In summary, both EL and PL techniques were consistent in showing that carrots exhibit variable defect structures on a microscopic scale.     

Electron microscopic study on residual defects of Al+ or B+ implanted 4H-SiC

The residual defects of Al⁺- or B⁺-implanted 4H-SiC were studied in combination with annealing temperature and implantation temperature using cross-sectional transmission electron microscopy technique. Noticeable defects structure is not observed before post-implantation annealing. But after annealing, a lot of black spots appear in the implanted layer. These black spots are composed of a dislocation loop, parallel to {0001} of 4H-SiC, and strained area at the upper and lower sides of the dislocation loop. This defect structure and its size do not depend on implantation temperature and implanted ion species. The size of defect area depends only on post-implantation annealing temperature. The size grows, when post-annealing temperature is raised.     

Relationship between infrared photoluminescence and resistivity in semi-insulating 6H-SiC

A combination of room-temperature photoluminescence (PL) mapping, low-temperature PL spectroscopy, and resistivity mapping was applied to establish the origin of resistivity variations in different types of semi-insulating (SI) 6H-SiC substrates. Direct correlation between the native-defect PL and resistivity was found in undoped (V-free) SI samples. The regions with high PL intensity also showed high resistivity, indicating that native point defects are associated with the compensation mechanism in those substrates and its nonhomogeneity. A more complex correlation was established for the vanadium-doped samples. In these samples, V-related PL and native point defect-related PL were both present at room temperature. While there was no clear correlation between the resistivity maps and the maps of PL intensity measured at either of the two peaks separately, the resistivity was in good correlation with the total PL signal consisting of both vanadium and intrinsic defect contributions. The resistivity of those wafers was apparently due to the contribution of both V-related and native point defect-related deep levels.     

Micropipe and dislocation density reduction in 6H-SiC and 4H-SiC structures grown by liquid phase epitaxy

We investigated silicon carbide (SiC) epitaxial layers grown by liquid phase epitaxy (LPE). The layers were grown on 6H-SiC and 4H-SiC well-oriented (0001) 35 mm diameter commercial wafers as well as on 6H-SiC Lely crystals. A few experiments were also done on off-axis 6H-SiC and 4H-SiC substrates. Layer thickness and growth rate ranged from 0.5 to 50 microns and 0.5 to 10 μm/h, respectively. Layers were investigated by x-ray diffraction, x-ray topography, and selective chemical etching in molten KOH. It was found that dislocation and micropipe density in LPE grown epitaxial layers were significantly reduced compared with the defect densities in the substrates.     

Identification of a Three-Site Defect in Semi-Insulating 4H-SiC

Using electron paramagnetic resonance (EPR), we observe a defect that increases significantly with annealing temperature. This spin S = 1 defect is characterized by g _x ≈ g _y ≈ g _z = 2.0056 and a fine structure splitting D ∼ 100 G whose principal axis lies in a plane perpendicular to the c-axis. Also resolved are several hyperfine interactions with the low abundance ²⁹Si and ¹³C neighboring nuclei. A careful analysis of the intensity of these hyperfine lines allows a precise determination of the identity and the quantity of interacting nuclei. This center is diamagnetic in the ground state but can be excited into a paramagnetic triplet state by sub-bandgap light. We identify this new defect as a three-site vacancy involving V _C-V _Si-V _C. The angular dependence of the ¹³C hyperfine interaction supports the proposed model. These may be the simplest of a family of more complex and extended defects that play a role in the semi-insulating (SI) character of SiC.     

6H-SiC埋沟NMOSFET耗尽模式的电流特性分析

在考虑杂质不完全离化的作用下,建立了6H—SiC埋沟NMOSFET耗尽模式下的电流解析模型。并通过模型,仿真分析了器件电流随温度的变化情况。在温度达到600k以上时,杂质的不完全离化作用对器件的影响不明显。常温下电流特性模型的仿真结果与实验结果的一致性,说明了本模型的准确性。     

Analysis of nonexponential deep-level current transients in schottky diodes fabricated on [1\bar 100] 6H-SiC00] 6H-SiC

A current deep-level transient spectroscopy (DLTS) system capable of recording an entire set of current transients was developed and used for characterization of deep levels in n-type 6H-SiC wafers grown in the [1 00] direction. The current transients were acquired in the time interval from 10⁻⁴ sec to 10 sec and temperature range from 100 K to 700 K. The current transients exhibited nonexponential behavior, which was related to closely spaced traps in the band gap. The logarithmic plot of the current transient was close to linear at most temperatures. Because the conventional approach based on exponential emission of electrons from discrete levels cannot describe the observed nonexponential behavior of current transients, the transients were fitted assuming continuous distribution of traps in the band gap. Theoretically calculated current transients assuming Gaussian distribution of trap centers in the band gap agree with the experimental data fairly well. The results of electrical measurements and theoretical fitting were explained based on a high density of defects in the investigated wafer that were revealed by chemical etching and related to stacking faults.     

硅熔体中3C-SiC的生长及6H-SiC晶型的抑制

论述了从硅熔体中生长 3C- Si C晶体过程中 6 H- Si C晶型控制的一般原理 .采用将硅置于高纯石墨坩埚中使其在高温条件下熔化 ,坩埚内壁石墨自然熔解于硅熔体中形成碳饱和的硅熔体 ,在石墨表面形成厚约 0 .2 m m的Si C薄层 .X射线衍射 (XRD)、X射线光电子能谱 (XPS)、Ram an散射等分析表明所制备样品为 3C- Si C多晶体 .实验结果进一步证明从硅熔体中生长 3C- Si C晶体过程中 ,通过适当调整工艺参数可以抑制 6 H- Si C晶型的形成 .     

Dopant activation and surface morphology of ion implanted 4H- and 6H-silicon carbide

The activation of ion-implanted B into 4H-SiC, and B, and Al into 6H-SiC is investigated. Complete activation of B implants into 4H-SiC is achieved by annealing at 1750°C for 40 min in an Ar environment. Significant activation (>10%) is not achieved unless the annealing temperature is 1600°C or greater. Sheet resistances of Al-implanted 6H-SiC annealed at 1800°C are 32.2 kΩ/□, indicating high activation of Al at this temperature. Annealing conditions which result in good acceptor activation are shown to be damaging to the surface of either 4H- or 6H-SiC. Atomic force microscopy and Nomarski differential interference contrast optical microscopy are applied to characterize the surfaces of these polytypes. Roughening of the surfaces is observed following annealing in Ar, with measured roughnesses as large as 10.1 nm for B-implanted 4H-SiC annealed at 1700°C for 40 min. Based on data obtained from these techniques, a model is proposed to describe the roughening phenomenon. The premise of the model is that SiC sublimation and mobile molecules enable the surface to reconfigure itself into an equilibrium form.     

6H-SiC MOS场效应晶体管的研制

报道了多晶硅栅 6 H- Si C MOS场效应器件的制造工艺和器件性能。 6 H- Si C氧化层的SIMS分析说明在氧化过程中 ,多余的 C以 CO的形式释放 ,铝元素逸出极少 ,氧化层中因有较多的铝而正电荷密度较大 ,Si C的氧化速率和掺杂类型关系不大。器件漏电流都有很好的饱和特性 ,最大跨导为 0 .36 m S/ mm ,沟道电子迁移率约为 14cm2 / V.s,但串联电阻效应明显。     

N型6H-SiCMOS电容的电学特性

在可商业获得的 N型 6 H- Si C晶片上 ,通过化学气相淀积 ,进行同质外延生长 ,在此结构材料上 ,制备 MOS电容 .详细测量并分析了 6 H- Si C MOS电容的电学特性 ,其有效电荷密度为 4.3× 10 1 0 cm- 2 ;Si C与 Si O2 之间的势垒高度估算为 2 .6 7e V;Si C热生长 Si O2 的本征击穿场强 (用累计失效率 5 0 %时的场强来计算 )为 12 .4MV/ cm ,已达到了制作器件的要求 .     

6H-SiC高压肖特基势垒二极管

在可商业获得的 N型 6 H - Si C晶片上 ,通过化学气相淀积 ,进行同质外延生长 ,在此结构材料上 ,通过热蒸发 ,制作 Ni/6 H- Si C肖特基势垒二极管 .测量并分析了肖特基二极管的电学特性 ,结果表明 ,肖特基二极管具有较好的整流特性 :反向击穿电压约为 45 0 V,室温下 ,反向电压 VR=- 2 0 0 V时 ,反向漏电流 JL=5× 10 - 4 A· cm- 2 ;理想因子为 1.0 9,肖特基势垒高度为 1.2 4— 1.2 6 e V ,开启电压约为 0 .8V     

6H-SiC高反压台面pn结二极管

在可商业获得的单晶 6 H- Si C晶片上 ,通过化学气相淀积 ,进行同质外延生长 ;并在此 6 H - Si C结构材料上 ,利用反应离子刻蚀和接触合金化技术 ,制作台面 pn结二极管 .详细测量并分析了器件的电学特性 ,测量结果表明此 6 H - Si C二极管在室温、空气介质中 ,- 10 V时 ,漏电流密度为 2 .4× 10 - 8A/cm2 ,在反向电压低于 6 0 0 V及接近30 0℃高温下都具有良好的整流特性 .