A Low-Noise Wideband Digital Phase-Locked Loop Based on a Coarse–Fine Time-to-Digital Converter With Subpicosecond Resolution

This paper presents the design of a digital PLL which uses a high-resolution time-to-digital converter (TDC) for wide loop bandwidth. The TDC uses a time amplification technique to reduce the quantization noise down to less than 1 ps root mean square (RMS). Additionally TDC input commutation reduces low-frequency spurs due to inaccurate TDC scaling factor in a counter-assisted digital PLL. The loop bandwidth is set to 400 kHz with a 25 MHz reference. The in-band phase noise contribution from the TDC is -116 dBc/Hz, the phase noise is -117 dBc/Hz at high band (1.8 GHz band) 400 kHz offset, and the RMS phase error is 0.3deg.     

A CMOS Time-to-Digital Converter (TDC) Based On a Cyclic Time Domain Successive Approximation Interpolation Method

This paper describes a time-to-digital converter (TDC) with $sim $1.2 ps resolution and $sim $327 $mu$s dynamic range suitable for laser range-finding application for example. The resolution of $sim $1.2 ps is achieved with interpolation based on a cyclic time domain successive approximation (CTDSA) method that resolves the time difference between two non-repetitive signals using binary search. The method utilizes a pair of digital-to-time converters (DTC), the propagation delay difference between which is implemented by digitally controlling the unit load capacitors of their delay cells, thus enabling sub-gate delay timing resolution. The rms single-shot precision, i.e., standard deviation $sigma $-value of the TDC is 3.2 ps, which is achieved by using an external integral nonlinearity look-up table (INL-LUT) for the interpolators. The power consumption is 33 mW at 100 MHz with a 3.3 V operating voltage. The prototypes were fabricated in a 0.35 $mu{hbox {m}}$ CMOS process.      

A 60–110 GHz Transmission-Line Integrated SPDT Switch in 90 nm CMOS Technology

This letter demonstrates a fully integrated transmit/receive single-pole-double-throw switch in standard bulk 90 nm CMOS process. This switch is based on the transmission-line integrated approach that reduces the effect of parasitic capacitance of transistors in the desired band, and this approach can achieve good isolation and return loss with fewer stages of transistors and broad bandwidth. The switch provides an insertion loss of 3–4 dB and a return loss better than 10 dB in 60–110 GHz. The measured isolation is better than 25 dB. The measured 1 dB compression point of input power is 10.5 dBm at 75 GHz. To the best of our knowledge, this is the first CMOS switch operating beyond 100 GHz.      

A 30–100 GHz Wideband Sub-Harmonic Active Mixer in 90 nm CMOS Technology

This letter presents a 30–100 GHz wideband and compact fully integrated sub-harmonic Gilbert-cell mixer using 90 nm standard CMOS technology. The sub-harmonic pumped scheme with advantages of high port isolation and low local oscillation frequency operation is selected in millimeter-wave mixer design. A distributed transconductance stage and a high impedance compensation line are introduced to achieve the flatness of conversion gain over broad bandwidth. The CMOS sub-harmonic Gilbert-cell mixer exhibits ${-}{hbox{1.5}} pm {hbox{1.5}}$ dB measured conversion gain from 30 to 100 GHz with a compact chip size of 0.35 mm$^{2}$. The OP$_{1 {rm dB}}$ of the mixer is ${-}$ 10.4 dBm and ${-}$9.6 dBm at 77 and 94 GHz, respectively. To the best of our knowledge, the monolithic microwave integrated circuit is the first CMOS Gilbert-cell mixer operating up to 100 GHz.      

A Low-Complexity, Low-Phase-Noise, Low-Voltage Phase-Aligned Ring Oscillator in 90 nm Digital CMOS

An 8-phase phase-aligned ring oscillator in 90 nm digital CMOS is presented that operates up to 2 GHz. The low-complexity circuit consumes 13 mW at 2 GHz and 1.2 mW at 400 MHz, while a flat in-band phase noise below $-$120 dBc$/$Hz is achieved, in close agreement with the presented theory. The circuit occupies an area of 0.008 mm$^{2}$ .      

A 1.9 Gb/s 358 mW 16–256 State Reconfigurable Viterbi Accelerator in 90 nm CMOS

A 16-256 state coarse-grain reconfigurable Viterbi accelerator fabricated in 1.3 V_t 90 nm dual-CMOS technology is described for 3.8 GHz operation, with 1.9 Gb/s data rate in 32-state mode. Radix-4 ripple-carry ACS circuits, reconfigurable path metric read/write control, and tree-bitline traceback memory circuits with programmable ring-buffer decoders enable 358 mW total power, measured at 1.3 V, 50degC, with performance scalable to 2.35 Gb/s at 1.7 V, 50degC.     

A Digital Envelope Modulator for a WLAN OFDM Polar Transmitter in 90 nm CMOS

A digital envelope modulator as part of a polar transmitter architecture for the 802.11a/g WLAN OFDM standards is investigated. The digital envelope modulator is quite similar to a state-of-the-art DAC design, but now it has been optimized to deal with envelope signals. A thermometer-coded envelope DAC has been implemented in a 90 nm digital CMOS process. Measurements of a test chip show the digital envelope modulator to reach an OFDM output power of 5 dBm for 54 Mb/s using 64 QAM at 2.45 GHz and fulfilling EVM specifications and in-band spectral mask requirements using just 12.7 mW from a 1.2 V supply. Combining the digital envelope modulator with an off-chip power amplifier gives an output power of 20.4 dBm, while fulfilling EVM specifications and in-band spectral mask requirements. The output power of the presented envelope DAC can be increased in a re-design by scaling device sizes. The envelope DAC is a key component in a software-defined-radio transmitter.     

A digitally controlled oscillator in a 90 nm digital CMOS process for mobile phones

We propose and demonstrate the first RF digitally controlled oscillator (DCO) for cellular mobile phones. The DCO is part of a single-chip quad-band fully compliant GSM transceiver realized in a 90 nm digital CMOS process. Wide and precise linear frequency tuning is achieved through digital control of a large array of standard n-poly/n-well MOSCAP devices that operate in flat regions of their C- V curves. The varactors are partitioned into binary-weighted and unit-weighted banks that are sequentially activated during frequency locking and tracking. The finest varactor step size is 12 kHz at the 1.6-2.0 GHz high-band output. To attenuate the quantization noise to below the natural oscillator phase noise, the varactors undergo high-speed second-order /spl Sigma//spl Delta/ dithering. We analyze the effect of the /spl Sigma//spl Delta/ dithering on the phase noise and show that it can be made sufficiently small. The measured phase noise at 20 MHz offset in the GSM900 band is -165 dBc/Hz and shows no degradation due to the /spl Sigma//spl Delta/ dithering. The 3.6 GHz DCO core consumes 18.0 mA from a 1.4 V supply and has a very wide tuning range of 900 MHz to support the quad-band operation.     

A 1.25–5 GHz Clock Generator With High-Bandwidth Supply-Rejection Using a Regulated-Replica Regulator in 45-nm CMOS

A clock generator for high-speed chip-to-chip link receivers was implemented in a 45-nm CMOS SOI technology. A low sensitivity to supply voltage noise was achieved by means of a low-dropout voltage regulator using a replica feedback in the regulation loop, where the replica resistance is regulated by a second loop. We show that by adjusting the replica load the necessary matching of the $gm/gds$ ratio of the current sources can be achieved. A power supply rejection of $>,$22 dB was measured up to 1 GHz for a circuit operating from a 1 V supply with 80$~$ pF decoupling capacitance and a load current of 18.5 mA. The maximum supply sensitivity of the clock generation circuit (DLL plus phase rotators) was 4.5 ps/100 mV supply noise over the entire noise frequency range at clock frequencies from 1.25–5 GHz. The phase rotator achieves a wide range of operating frequencies by providing programmable rise/fall times in its selection stage. In addition, low voltage operation of the circuit was demonstrated at supply voltages down to 0.7$~$V and a clock frequency of 1.6 GHz.      

A 1–9 GHz Linear-Wide-Tuning-Range Quadrature Ring Oscillator in 130 nm CMOS for Non-Contact Vital Sign Radar Application

A 1–9 GHz linear-wide-tuning-range quadrature ring oscillator has been designed and fabricated in UMC 0.13 $mu$m CMOS process. The chip was wire-bonded on printed circuit board and tested, showing a liner tuning range from 1 GHz to 9 GHz. Comparative study with other differential ring oscillators demonstrates the advantages of this design in low power consumption and linear-tuning. The oscillator was designed as the voltage controlled oscillator (VCO) for a non-contact vital sign radar sensor. It can also be used for other applications such as ultra-wideband (UWB) impulse radio and clock recovery in broadband optical communications.      

A 9–31-GHz Subharmonic Passive Mixer in 90-nm CMOS Technology

A subharmonic down-conversion passive mixer is designed and fabricated in a 90-nm CMOS technology. It utilizes a single active device and operates in the LO source-pumped mode, i.e., the LO signal is applied to the source and the RF signal to the gate. When driven by an LO signal whose frequency is only half of the fundamental mixer, the mixer exhibits a conversion loss as low as 8–11 dB over a wide RF frequency range of 9–31GHz. This performance is superior to the mixer operating in the gate-pumped mode where the mixer shows a conversion loss of 12–15dB over an RF frequency range of 6.5–20 GHz. Moreover, this mixer can also operate with an LO signal whose frequency is only 1/3 of the fundamental one, and achieves a conversion loss of 12–15dB within an RF frequency range of 12–33 GHz. The IF signal is always extracted from the drain via a low-pass filter which supports an IF frequency range from DC to 2 GHz. These results, for the first time, demonstrate the feasibility of implementation of high-frequency wideband subharmonic passive mixers in a low-cost CMOS technology.     

A 56–65 GHz Injection-Locked Frequency Tripler With Quadrature Outputs in 90-nm CMOS

A sub-harmonic injection-locked tripler multiplies a 20-GHz differential input to 60-GHz quadrature (I/Q) output signals. The tripler consists of a two-stage ring oscillator driven by a single-stage polyphase input filter and 50-$Omega$ I and Q-signal output buffers. Each gain stage incorporates a hard limiter to triple the input frequency for injection locking and a negative resistance cell with two positive feedback loops to increase gain. Regenerative peaking is also used to optimize the gain/bandwidth performance of the 50-$Omega$ output buffers. Fabricated in 90-nm CMOS, the tripler has a free-running frequency of 60.6 GHz. From a 0-dBm RF source, the measured output lock range is 56.5–64.5 GHz, and the measured phase noise penalty is 9.2 $ pm 1~$dB with respect to a 20.2-GHz input. The $0.3times 0.3~ hbox{mm}^{2}$ tripler (including passives) consumes 9.6 mW, while the output buffers consume 14.2 mW, all from a 1-V supply.      

A Fully Integrated Ultra-Low Insertion Loss T/R Switch for 802.11b/g/n Application in 90 nm CMOS Process

A 30 dBm ultra-low insertion loss CMOS transmit-receive switch fully integrated with an 802.11b/g/n transceiver front-end is demonstrated. The switch achieves an insertion loss of 0.4 dB in transmit mode and 0.1 dB in receive mode. The entire receiver chain from antenna to baseband output achieves a measured noise figure of 3.6 dB at 2.4 GHz. The switch has a P_1dB greater than 30 dBm by employing a substrate isolation technique without using deep n-well technology. The switch employs a 1.2 V supply and occupies 0.02 mm² of die area.     

A 1.35 GS/s, 10 b, 175 mW Time-Interleaved AD Converter in 0.13 µm CMOS

A time-interleaved ADC is presented with 16 channels, each consisting of a track-and-hold (T&H) and two successive approximation (SA) ADCs in a pipeline configuration to combine a high sample rate with good power efficiency. The single-sided overrange architecture achieves a 25% higher power efficiency of the SA-ADC compared with the conventional overrange architecture, and look-ahead logic is used to minimize logic delay in the SA-ADC. For the T&H, three techniques are presented enabling a high bandwidth and linearity and good timing alignment. Single channel performance of the ADC is 6.9 ENOB at an input frequency of 4 GHz. Multichannel performance is 7.7 ENOB at 1.35 GS/s with an ERBW of 1 GHz. The FoM of the complete ADC including T&H is 0.6 pJ per conversion step. An improved version is presented as well and achieves an SNDR of 8.6 ENOB for low sample rates, and, with increased supply voltage, it reaches a sample rate of 1.8 GS/s with 7.9 ENOB at low input frequencies and an ERBW of 1 GHz. At fin = 3.6 GHz, the SNDR is still 6.5 ENOB, and total timing error including jitter is 0.4 ps rms.     

A 5.8 GHz 1 V Linear Power Amplifier Using a Novel On-Chip Transformer Power Combiner in Standard 90 nm CMOS

A fully integrated 5.8 GHz Class AB linear power amplifier (PA) in a standard 90 nm CMOS process using thin oxide transistors utilizes a novel on-chip transformer power combining network. The transformer combines the power of four push-pull stages with low insertion loss over the bandwidth of interest and is compatible with standard CMOS process without any additional analog or RF enhancements. With a 1 V power supply, the PA achieves 24.3 dBm maximum output power at a peak drain efficiency of 27% and 20.5 dBm output power at the 1 dB compression point.     

A Low Loss High Isolation DC-60 GHz SPDT Traveling-Wave Switch With a Body Bias Technique in 90 nm CMOS Process

In this letter, a low loss high isolation broadband single-port double-throw (SPDT) traveling-wave switch using 90 nm CMOS technology is presented. A body bias technique is utilized to enhance the circuit performance of the switch, especially for the operation frequency above 30 GHz. The parasitic capacitance between the drain and source of the NMOS transistor can be further reduced using the negative body bias technique. Moreover, the insertion loss, the input 1 dB compression point (${rm P} _{{1}~{rm dB}}$), and the third-order intermodulation (IMD3) of the switch are all improved. With the technique, the switch demonstrates an insertion loss of 3 dB and an isolation of better than 48 dB from dc to 60 GHz. The chip size of the proposed switch is 0.68 $,times,$0.87 ${rm mm}^{2}$ with a core area of only 0.32$,times,$0.21 ${rm mm}^{2}$.      

A resistive-feedback LNA in 65 nm CMOS with a gate inductor for bandwidth extension

In order to get a wideband and flat gain, a resistive-feedback LNA using a gate inductor to extend bandwidth is proposed in this paper. This LNA is based on an improved resistive-feedback topology with a source follower feedback to match input. A relative small inductor is connected in series to transistor׳s gate, which boosts transistor׳s effective transconductance, compensates gain loss and then leads the proposed LNA with a flat gain and wider bandwidth. Moreover, the LNA׳s noise is partially inhibited by the gate inductor, especially at high frequency. Realized in standard 65-nm CMOS process, this LNA dissipates 12 mW from a 1.5-V supply while its core area is 0.076 mm². Across 0.4–10.6 GHz band, the proposed LNA provides 9.5±0.9 dB power gain (S₂₁), better than −11-dB input matching, 3.5-dB minimum noise figure, and higher than −17.2-dBm P_1 dB.     

A 0.65-to-1.4 nJ/Burst 3-to-10 GHz UWB All-Digital TX in 90 nm CMOS for IEEE 802.15.4a

We propose an all-digital UWB transmitter architecture that exploits the low duty cycle of impulse-radio UWB to achieve ultra-low power consumption. The design supports the IEEE 802.15.4a standard and is demonstrated for its mandatory mode. A digitally controlled oscillator produces the RF carrier between 3 and 10 GHz. It is embedded in a phase-aligned frequency-locked loop that starts up in 2 ns and thus exploits the signal duty cycle that can be as low as 3%. A fully dynamic modulator shapes the BPSK symbols in discrete steps at the 499.2 MHz chip rate as required by the standard. The transmitter can operate in any 499.2 MHz band of the standard between 3.1 and 10 GHz, and the generated signal fulfills the emission spectral mask. The jitter accumulation over a burst is below 6 ps_RMS, which is within specifications. The transmitter was realized in a 1 V 90 nm digital CMOS technology, and its power consumption drawn from a 1 V supply is from 0.65 mW at 3.1 GHz to 1.4 mW at 10 GHz for a 1 Mb/s data rate.     

A Compensation Technique for Smooth Transitions in a Noninverting Buck–Boost Converter

With the advent of battery-powered portable devices and mandatory adoption of power factor correction, noninverting buck-boost converters are garnering lots of attention. Conventional two-switch or four-switch noninverting buck-boost converters choose their operation modes by measuring input and output voltage magnitude. The criterion for the selection of the operation mode can cause higher output voltage transients in the neighborhood, where input and output are close to each other. For the mode selection, due to the voltage drops raised by the parasitic components, it is not enough just to compare the magnitude of input and output voltages. In addition, the difference in the minimum and maximum effective duty cycles between controller output and switching device yields discontinuity at the instant of mode change. Moreover, the different properties of output voltage versus a given duty cycle of buck and boost operating modes contribute to the output voltage transients. In this paper, the effect of the discontinuity due to the effective duty cycle derived from the device switching time at the mode change is analyzed. A technique to compensate the output voltage transient due to this discontinuity is proposed. In order to attain additional mitigation of output transients and a linear input/output voltage characteristic in buck and boost modes, the linearization of DC gain of the large-signal model in boost operation is analyzed as well. Analytical, simulation, and experimental results are presented to validate the proposed theory.