On-line compensation of dead-time and inverter nonlinearity with disturbance voltage observer

This paper discusses and analyses a simple on-line compensation scheme for dead-time and inverter nonlinearity in the pulse width modulated (PWM) voltage source inverter (VSI). Dead-time effect and voltage drop in switching devices cause nonlinearity between reference and output voltage. In a conventional three-phase six-switch inverter, this nonideal condition adds extraneous harmonics that badly disturb voltage characteristics. In its turn, voltage disturbance causes distortion of the current waveform and degrades performance. In this paper, an on-line dead-time compensation method based on inverse dynamics control is proposed, and it is much simpler than conventional full/reduced order observation methods adopted in dead-time compensation. Disturbance voltages are observed on-line with no additional circuitry or off-line measurements. The observed disturbance voltages are fed back to the voltage reference for compensation. Stability problem of the proposed observer arisen from inverter delay and parameter mismatch was analysed. The proposed method is applied to a surface-mounted permanent-magnet synchronous motor (SPMSM) drive. The effectiveness of the proposed scheme is validated by the experimental results.     

永磁同步电机矢量控制中死区补偿技术的研究

本文针对永磁同步电机矢量控制系统,分析了死区电压矢量对三相输出电压的影响以及死区电压矢量与定子电流方向的关系,提出了一种基于SVPWM矢量控制的死区补偿方法。定子电流矢量角根据计算得出,避免了传统方法在相电流过零处由于电流方向检测不准而影响补偿效果。该方案无需增加硬件电路,对软件进行修改即可实现。仿真试验结果证实了该方法的有效性。     

Four-wire dynamic voltage restorer based on a three-dimensional voltage space vector PWM algorithm

A modified voltage space vector pulse-width modulated (PWM) algorithm for a four-wire dynamic voltage restorer (DVR) is described. The switching strategy based on a three-dimensional (3-D) /spl alpha//spl beta/O voltage space is applicable to the control of three-phase four-wire inverter systems such as the split-capacitor PWM inverter and the four-leg PWM inverter. In contrast to the conventional voltage space vector PWM method, it controls positive, negative and zero sequence components of the terminal voltages instantaneously. Three 3-D modulation schemes are analyzed with respect to total harmonic distortion (THD), weighted total harmonic distortion (WTHD), neutral line ripple and switching loss over the whole range of the modulation index when the DVR experiences both balanced and unbalanced sags with phase angle jumps. Experimental results from a 9 kW DVR system using a split-capacitor PWM inverter are presented to validate the simulation results.     

Five-Level Diode Clamped Inverter to EliminateCommon Mode Voltage and Reduce $dv/dt$ inMedium Voltage Rating Induction Motor Drives

The High power induction machines are designed at medium voltage (MV) rating for better performance. The multilevel inverters (MLI) are able to provide medium voltage with high quality output at low switching frequency as compared to conventional two-level inverter. In addition to this, MLI reduces $dv/dt$, switching losses and leakage current. In this paper, approaches to reduce and eliminate the common mode voltage (CMV) using five-level diode clamped multilevel inverter (DCMLI) are presented. The CMV spikes are also eliminated by shifting dead-time across the phase pole. A novel technique for the selection of switching states to synthesize the desire vector is proposed. This paper realizes the implementation of five-level diode clamped MLI for three phase induction motor. Experimental results demonstrate the feasibility of the proposed solution.      

On-line dead-time compensation method using disturbance observer

A new on-line dead-time compensation method for a permanent magnet (PM) synchronous motor drive is proposed. Using a simple disturbance observer without any additional circuit and off-line experimental measurement, disturbance voltages in the rotor reference dq frame caused by the dead time and nonideal switching characteristics of power devices are estimated in an on-line manner and fed to voltage references in order to compensate the dead-time effects. The proposed method is applied to a PM synchronous motor drive system and implemented by using software of a digital signal processor (DSP) TMS320C31. Simulations and experiments are carried out for this system and the results well demonstrate the effectiveness of the proposed method.     

Dead-Time Elimination of PWM-Controlled Inverter/Converter Without Separate Power Sources for Current Polarity Detection Circuit

This paper will present a dead-time elimination scheme for a pulsewidth-modulation (PWM)-controlled inverter/converter. The presented dead-time elimination scheme does not require separated power supplies for freewheeling-current detection of high- and low-side power devices. The presented scheme includes the freewheeling-current polarity detection circuit and the PWM control generator without dead time. It will be shown that the presented scheme eliminates the dead time of PWM control for inverter/converter and therefore dramatically improves output voltage loss and current distortion. Experimental results derived from a field-programmable-gate-array-based PWM-controlled inverter are shown to demonstrate the effectiveness.      

Dead-time effect and compensations of three-level neutral pointclamp inverters for high-performance drive applications

Due to the use of high-power devices and slow-switching frequency in a three-level neutral point clamp inverter, the dead-time effect may not be compensated sufficiently fast by using methods developed for the two-level inverter. In this paper, the dead-time effect in a three-level inverter with snubber circuits is analyzed to reveal that it does not only depend on load current direction, but also on magnitude. The snubber network also plays an important role in determining the output phase voltage during the dead-time period. Software techniques are proposed to compensate the dead-time effect as soon as it occurs as demanded by the slow-switching frequency. Experimental results show their effectiveness     

一种三相SVPWM逆变器死区补偿方法

在分析三相SVPWM逆变器死区时间内工作过程基础上,采用了一种基于死区优化设置法消除死区效应的策略。该策略通过对电流极性的判断,只对逆变器每相桥臂上的某一个开关管加入死区,并通过仿真和实验验证了理论分析的正确性和补偿措施的有效性。     

Inverter Nonlinearity Compensation in the Presence of Current Measurement Errors and Switching Device Parameter Uncertainties

This paper proposes a compensation strategy for the unwanted disturbance voltage due to inverter nonlinearity. We employ an emerging learning technique called support vector regression (SVR). SVR constructs a motor dynamic voltage model by a linear combination of the current samples in real time. The model exhibits fast observer dynamics and robustness to observation noise. Then the disturbance voltage is estimated by subtracting the constructed voltage model from the current controller output. The proposed method compensates for all of the inverter nonlinearity factors at the same time. All the processes in estimating distortions are independent of the dead time and power device parameters. From the analysis of the effect on current measurement errors, we confirmed that the sampling error had little negative impact on the proposed estimation method. Experiments demonstrate the superiority of the proposed method in suppressing voltage distortions caused by inverter nonlinearity     

逆变器中死区效应及其补偿策略分析

对死区时间对逆变器输出电压的影响进行了分析。死区效应引起的电压偏差可以等效为一个与电流相为相反的方波。并对死区效应的补偿策略进行了研究。     

A novel control scheme for the multilevel rectifier/inverter

A novel three-level pulsewidth modulation (PWM) rectifier/inverter is proposed: this single-phase three-level rectifier with power factor correction and current harmonic reduction is proposed to improve power quality. A three-phase three-level neutral point clamped (NPC) inverter is adopted to reduce the harmonic content of the inverter output voltages and currents. In the adopted rectifier, a switching mode rectifier with two AC power switches is adopted to draw a sinusoidal line current in phase with mains voltage. The switching functions of the power switches are based on a look-up table. To achieve a balanced DC-link capacitor voltage, a capacitor voltage compensator is employed. In the NPC inverter, the three-level PWM techniques based on the sine-triangle PWM and space vector modulation are used to reduce the voltage harmonics and to drive an induction motor. The advantages of the adopted th-ree-level rectifier/inverter are (1) the blocking voltage of power devices (T1, T2, S_a1-S_c4) is clamped to half of the DC-link voltage, (2) low conduction loss with low conduction resistance due to low voltage stress, (3) low electromagnetic interference, and (4) low voltage harmonics in the inverter output. Based on the proposed control strategy, the rectifier can draw a high power factor line current and achieve two balance capacitor voltages. The current harmonics generated from the adopted rectifier can meet the international requirements. Finally, the proposed control algorithm is illustrated through experimental results based on the laboratory prototype.     

Design of adaptive dead-time control circuit for resonant half-bridge driver

To decrease the switching loss and the dead-time effect of resonant half-bridge inverter, a novel adaptive dead-time control circuit of resonant half-bridge driver Integrated Circuit (IC) is presented. Without increasing the pin number of IC, this circuit takes a novel strategy to adaptively regulate dead time to a temperate range between high and low thresholds. The high and low thresholds are adaptive to the fall time of output signal in a half-bridge clock cycle. The IC of the designed circuit is suitable for high-voltage applications. The dead-time regulation range of this circuit achieves 0–3.5?µs. The range of temperate dead-time state is 300?ns. The failure signal of this circuit can protect the IC and peripheral power devices by regulating operation in three clock cycles. Both simulation and measurement of the proposed circuit in a half-bridge driver IC with an operating frequency at 50?kHz are presented based on the 0.5?µm 700?V BCD process. The results of simulation and measurement show that the presented circuits’ performance is perfect.     

On-line dead-time compensation technique for open-loop PWM-VSIdrives

A new on-line dead-time compensation technique for low-cost open-loop pulsewidth modulation voltage-source inverter (PWM-VSI) drives is presented. Because of the growing numbers of open-loop drives operating in the low-speed region, the synthesis of accurate output voltages has become an important issue where low-cost implementation plays an important role. The so-called average dead-time compensation techniques rely on two basic parameters to compensate for this effect: the magnitude of the volt seconds lost during each PWM cycle and the direction of the current. In a low-cost implementation, it is impractical to attempt an on-line measurement of the volt-seconds error introduced in each cycle-instead an off-line measurement is favored. On the other hand, the detection of the current direction must be done on line. This becomes increasingly difficult at lower frequencies and around the zero crossings, leading to erroneous compensation and voltage distortion. This paper presents a simple and cost-effective solution to this problem by using an instantaneous back calculation of the phase angle of the current. Given the closed-loop characteristic of the back calculation, the zero crossing of the current is accurately obtained, thus allowing for a better dead-time compensation. Experimental results validating the proposed method are presented     

Hybrid Cascaded H-Bridge Multilevel-Inverter Induction-Motor-Drive Direct Torque Control for Automotive Applications

This paper presents a hybrid cascaded H-bridge multilevel motor drive direct torque control (DTC) scheme for electric vehicles (EVs) or hybrid EVs. The control method is based on DTC operating principles. The stator voltage vector reference is computed from the stator flux and torque errors imposed by the flux and torque controllers. This voltage reference is then generated using a hybrid cascaded H-bridge multilevel inverter, where each phase of the inverter can be implemented using a dc source, which would be available from fuel cells, batteries, or ultracapacitors. This inverter provides nearly sinusoidal voltages with very low distortion, even without filtering, using fewer switching devices. In addition, the multilevel inverter can generate a high and fixed switching frequency output voltage with fewer switching losses, since only the small power cells of the inverter operate at a high switching rate. Therefore, a high performance and also efficient torque and flux controllers are obtained, enabling a DTC solution for multilevel-inverter-powered motor drives.      

准恒频电流滞环控制的死区补偿

详细分析了逆变器的死区效应,结合变环宽准恒频滞环控制的特点,本文采用按电流极性对脉冲给予补偿的方法,并对环宽进行修正。另外针对零电流箝位现象和滞环控制本身造成的过零点附近电流极性难以检测的问题,采用零电流附近极性给定策略;针对峰值处占空比为1的情况,通过对环宽进行限幅,减小电压波形的畸变。仿真和实验验证了该方案的可行性...     

A new quasi-resonant DC-link PWM inverter using single switch for soft switching

This paper presents a new quasi-resonant DC-link (QRDCL) inverter. Only one switching device is used to create zero voltage instants under all load conditions. The maximum voltage across the inverter devices is maintained at around (1.01-1.1) times the input source voltage. The circuit has the flexibility of selecting switching instants of the resonant link in synchronism with any PWM technique. Control technique does not require the help of inverter switches to create the zero voltage instants in the DC-link, and voltage and current sensors are eliminated from the control circuit. In this paper, the principle of operation and detailed analysis of the proposed QRDCL inverter are presented and design considerations for achieving soft switching are obtained. Detailed PSPICE simulation studies are carried out to study the feasibility of the proposed topology under various load conditions. The experimental results of the proposed QRDCL PWM inverter feeding a three phase induction motor are given.     

1000-V, 30-A 4H-SiC BJTs with high current gain

This paper presents the development of 1000 V, 30A bipolar junction transistor (BJT) with high dc current gain in 4H-SiC. BJT devices with an active area of 3/spl times/3 mm/sup 2/ showed a forward on-current of 30 A, which corresponds to a current density of 333 A/cm/sup 2/, at a forward voltage drop of 2 V. A common-emitter current gain of 40, along with a low specific on-resistance of 6.0m/spl Omega//spl middot/cm/sup 2/ was observed at room temperature. These results show significant improvement over state-of-the-art. High temperature current-voltage characteristics were also performed on the large-area bipolar junction transistor device. A collector current of 10A is observed at V/sub CE/=2 V and I/sub B/=600 mA at 225/spl deg/C. The on-resistance increases to 22.5 m/spl Omega//spl middot/cm/sup 2/ at higher temperatures, while the dc current gain decreases to 30 at 275/spl deg/C. A sharp avalanche behavior was observed at a collector voltage of 1000 V. Inductive switching measurements at room temperature with a power supply voltage of 500 V show fast switching with a turn-off time of about 60 ns and a turn-on time of 32 ns, which is a result of the low resistance in the base.     

Characteristics of a new BBOS with an AlGaAs-/spl delta/(n/sup +/)-GaAs-InAlGaP collector structure

Two-terminal switching performances are observed in a new AlGaAs-GaAs-InAlGaP npn bulk-barrier optoelectronic switch (BBOS) with an AlGaAs-/spl delta/(n/sup +/)-GaAs-InAlGaP collector structure. The device shows that the switching action takes place from a low-current state to a high-current state through a region of negative differential resistance (NDR). The transition from either state to the other may be induced by an appropriate optical or electrical input. It is seen that the effect of illumination increases the switching voltage V/sub s/, holding voltage V/sub H/, and holding current I/sub H/, and decreases the switching current I/sub S/, which is quite different from other results reported. In addition, it possesses obvious NDR even up to 160/spl deg/C. This high-temperature performance provides the studied device with potential high-temperature applications.     

An accurate approach of nonlinearity compensation for VSI inverter output voltage

An accurate nonlinearity compensation technique for voltage source inverter (VSI) inverters is presented in this paper. Because of the nonlinearity introduced by the dead time, turn-on/off delay, snubber circuit and voltage drop across power devices, the output voltage of VSI inverters is distorted seriously in the low output voltage region. This distortion influences the output torque of IM motors for constant V/f drives. The nonlinearity of the inverter also causes 5th and 7th harmonic distortion in the line current when the distributed energy system operates in the grid-connected mode, i.e., when the distributed energy system is parallel to a large power system through the VSI inverter. Therefore, the exact compensation of this nonlinearity in the VSI inverter over the entire range of output voltage is desirable. In this paper, the nonlinearity of VSI inverter output voltage and the harmonic distortion in the line current are analyzed based on an open-loop system and a L-R load. By minimizing the harmonic component of the current in a d-axis and q-axis synchronous rotating reference frame, the exact compensation factor was obtained. Simulations and experimental results in the low frequency and low output voltage region are presented.     

一种基于SVPWM的死区补偿策略

对三相桥式逆变器死区效应进行了理论分析,提出了一种改进的基于SVPWM的死区补偿策略。理论分析和实验结果均表明该补偿策略能有效改善死区效应引起的电流畸变,且运算量小,实用性强。