Design and Optimization of Multiplierless FIR Filters Using Sub-Threshold Circuits

This paper develops and demonstrates the design and optimization method for fixed coefficient Finite Impulse Response (FIR) filters using sub-threshold circuits to achieve the minimum energy per operation. Sub-threshold circuit current, delay, power consumption, energy per operation and temperature dependence are modeled theoretically and analyzed using Matlab. Then the filter design and optimization are presented. With a frequency characteristic of 80 dB magnitude and 9.6 kHz bandwidth, the 16-bit fixed-point coefficients of the linear phase equiripple low-pass filter are generated from Matlab. Canonical Signed Digit (CSD) arithmetic is used for multiplierless design to improve both cost and performance. The transposed structure and symmetry structure are applied to optimize the delay and cost further. Horner’s rule is used to improve the precision. Tree-height reduction and subexpression sharing at Register Transfer Level (RTL) are used for further delay and cost reduction. Six versions of the filter with the same group of coefficients are designed and synthesized using Design Compiler with a 65 nm process. Synthesis results show that the area of the final version is reduced by 44% compared with the original design at a fixed frequency of 250 MHz, and at the highest frequency of each design, the area is reduce by about 23% while the performance is improved by 60%. These results show the design and optimization method developed in this paper can improve both the area and performance significantly. One adder from the synthesis netlist is simulated at the transistor-level using HSPICE to obtain characteristics of sub-threshold operations. The supply voltage varies from 1.2 to 0.08 V and temperatures from 0 to 110°C. The experiment results verify most characteristics of the sub-threshold models, but also reveal some limitations and defects of the theoretical models and previous results. The observations are discussed carefully with quantitative and qualitative analysis. For 25°C, the minimum energy point for the adder is 0.22 V. Finally, the results of the adder are used to estimate the energy per operation for the filters. For a fixed frequency of 36.4 kHz at 0.22 V, the estimated energy values vary from 4.8 to about 2.7 pJ for the six designed filters.     

A DFT Technique for Testing High-Speed Circuits with Arbitrarily Slow Testers

This paper presents a design for testability (DFT) technique for testing high-speed circuits with a low-speed test mode clock. With this technique, the test mode clock frequency can be reduced with virtually no lower limit. Even with the reduced speed requirement on the automatic test equipment (ATE), our method facilitates the test of the rated-speed timing and allows performance binning. A CMOS implementation of the DFT hardware with 50 ps timing accuracy is presented. To demonstrate the effectiveness of the technique we designed a 16-bit, 1.4 GHz pipelined multiplier as a test vehicle. Simulations using a test clock frequency much lower than the rated clock frequency show that delay faults of sizes as small as 50 ps are detected and that the new test technique provides correct performance binning.     

Jittery Signal Generation for High-Speed Interconnect Simulation

By generating clock and data waveforms in the frequency domain through a truncated Fourier series, absolute control over both voltage noise and symbol transition timing is achieved. A parameterized Fourier series signal model is derived and used to form clock and data waveforms exhibiting arbitrary noise and jitter characteristics. The method not only facilitates more accurate interconnect modeling in tools like Matlab and Simulink, but also provides a simple means for generating realistic signals that may be imported into Spice-based simulators.      

High-Speed IIL Circuits Using a Sidewall Base Contact Structure

New high-speed self-aligned IIL structures with 3 /spl mu/m X 3 /spl mu/m collectors that produce minimum gate delays of 290 ps/gate(fanout is 1) and power delay products. of 15 fJ/gate at low injector current levels are described. Maximum toggle frequency in an IIL T-type flip-flop is measured at 5 mW and found to be up to 315 MHz.     

一种采用常跨导偏置技术的高速多相时钟发生器

介绍了一种基于电荷泵型锁相环的高速多相时钟发生器。采用常跨导偏置技术，使锁相环的频率响应对工艺、电源电压和温度的变化不敏感；在压控振荡器中采用镜像偏置，使该时钟发生器无需外部精确的偏置电压或电流。电路采用UMC 0．18m N阱CMOS工艺实现。仿真结果显示，在SSS、TTT和FFF三种条件下，环路带宽变化仅为12％，相位裕量只变化0.1。     

高速电路与MCM互连线的分析

介绍了高速电路与 MCM互连线分析方面的研究与开发工作 ,包括两种新的传输线瞬态分析方法 ,及基于 SPICE的互连线分析系统。     

多层AHB系统中基于时分复用的高速从设备互连电路

片上系统在性能和功能上的突破性进展带来了新的挑战,包括大量IP模块之间的有效互连.虽然前人已经研究并实现了多种基于共享总线的多通道平行访问方案,但是当同一个IP块被多个通道同时访问时仍然存在数据传输的瓶颈.针对经常引起资源冲突的IP块,提出了一个基于时分复用的互连电路.该电路在同一个IP块被同时访问时重新安排传输信息,以时分复用的方式分配有限的资源.它将实现多个传输通道并行访问同一个IP核时不引入额外的延时,且对IP核是透明的.最后,在双层AHB总线系统的基础上实现了该电路.     

集成电路互连线串扰的模型与分析

针对集成电路中互连线之间的串扰问题,建立了一个基于电阻和电容的串扰分析模型,给出了干扰信号为线性倾斜信号时串扰的时域响应公式,并得出了串扰峰值的估算公式,明确了干扰信号上升沿对串扰的影响。利用该公式,能对全局互连性能的影响做出正确的估计,在互连布局前预先进行路由规划和资源选择。     

Self-Timed Regenerators for High-Speed and Low-Power On-Chip Global Interconnect

In this paper, we propose a new circuit technique called self-timed regenerator (STR) to improve both speed and power for on-chip global interconnects. The proposed circuits are placed along global wires to compensate the loss in resistive wires and to amplify the effect of wire inductance in the wires to enable transmission line like behavior. For different wire widths, the number of STR and sizing of the transistors are optimized to accelerate the signal propagation while consuming minimum power. In 90-nm CMOS technology, STR design achieved a delay improvement of 14% over the conventional repeater design. Furthermore, 20% power reduction is achieved for iso-delay, and 8% delay improvement for iso-power compared with the repeater design. The proposed technique has also been applied to a clock distribution network, reducing clock power by 26%.     

A Current-Mode Logic for Low-Voltage, High-Speed Mixed-Mode VLSI Circuits

A wired-AND current-mode logic (WCML) circuit is designed for high performance mixed analog and digital system designs on a common silicon substrate, using standard CMOS process. Current is used for digital information carrier in order to be able to reduce supply voltage, power consumption, digital switching noise and to increase operating frequency. The WCML circuit uses current-steering technique. It is composed of a simple current mirror with a current injector. Wired-AND connections cause the logic circuit to operate as a NAND logic gate which provides to implement any boolean function. High-speed is achieved by varying the injection current level even at low-voltage supply (<1.5 V) with low-power consumption.     

基于CMOS模拟电路的高速模糊神经网络设计

本文提出了可构成多规则模糊神经网络的CMOS模拟单元电路,包括:类Gauss型隶属度函数电路,电压求小电路和重心算法去模糊电路.基于这些电路设计了一个两输入/一输出、25条规则的控制系统,并通过非线性函数逼近进行了验证.所有单元均采用SMIC 0.18-μm CMOS数模混合工艺制造,芯片测试结果表明:提出的单元电路结构简单,输出电压偏差小,便于扩展和调节;因而适于实现多规则,自适应调节的高速高精度控制系统.     

Scalable Test Generators for High-Speed Datapath Circuits

This paper explores the design of efficient test sets and test-pattern generators for on-line BIST. The target applications are high-performance, scalable datapath circuits for which fast and complete fault coverage is required. Because of the presence of carry-lookahead, most existing BIST methods are unsuitable for these applications. High-level models are used to identify potential test sets for a small version of the circuit to be tested. Then a regular test set is extracted and a test generator TG is designed to meet the following goals: scalability, small test set size, full fault coverage, and very low hardware overhead. TG takes the form of a twisted ring counter with a small decoder array. We apply our technique to various datapath circuits including a carry-lookahead adder, an arithmetic-logic unit, and a multiplier-adder.     

MSI High-Speed Low-Power GaAs Integrated Circuits Using Schottky Diode FET Logic

A new planar high-density (10/sup -3/ mm/sup 2//gate) GaAs IC technology has been used for fabricating MSI digital circuits containing up to 75 gates/chip. These digital circuits have potential application for gigabit microwave data transmission and processor systems. The circuits consist of Schottky diode FET logic NOR gates, which have provided propagation delays in the 75-200-ps range with dynamic switching energies as low as 27 fJ/gate on ring oscillator structures. Power dissipation levels are compatible with future LSI/VLSI extensions. Operation of D flip-flops (DFF) as binary ripple dividers (/spl divide/2-/spl divide/8) was achieved at 1.9-GHz clock rates, and an 8:1 full-data multiplexer and 1:8 data demultiplexer were demonstrated at 1.1-GHz clock rates. This corresponds to equivalent propagation delays in the 100-175-ps range for these MSI circuits. Finally, a 3x3 parallel multiplier containing 75 gates functioned with a propagation delay of 172 ps/gate and with average gate power dissipations of as low as 0.42 mW/gate.     

MEMS电容式压力传感器检测电路比较研究

介绍了MEMS电容式压力传感器检测电路的5种实现方式:脉宽调制法、运算放大器法、电荷注入法、调频法和AC运放法。并从稳定性、测量灵敏度及抗杂散性等方面介绍了不同方式下检测电路的优缺点,为MEMS电容式压力传感器提供了参考。     

A CMOS Active Balun Using Bond Wire Inductors and a Gain Boosting Technique

An active balun with a single-ended input and a pair of differential outputs is presented for the input stages of differential circuits. The active balun, which is composed of an input resonator and cascaded common-gate amplifiers, was implemented using 0.18-mum CMOS technology and bond wire inductors. A body-source cross-coupled configuration was used to enhance the gain of the active balun. The gain is 9.3 dB at 1.8 GHz, and the phase and the amplitude error are less than 2deg and 1 dB, respectively, in the frequency range of 1 to 2 GHz, even for a P_1dB of -2.7 dBm. The balun consumes 9 mA for 3-V supply voltage.     

A Novel IP3 Boosting Technique Using Feedforward Distortion Cancellation Method for 5 GHz CMOS LNA

Low noise amplifier (LNA) in many wireless and wireline communication systems must have low noise, sufficient gain and high linearity performance. This paper presents a novel IP3 boosting technique using Feedforward Distortion Cancellation (FDC) method, that is, use an additional path to generate distortion and then cancel with the original LNA's distortion at its output. Through this technique, the IIP3 of LNA can be boosted from about 0 dBm, which is reported in most public literature to date, to +21 dBm, which is firstly reported to this day, with negligible noise degradation.     

HPE1413C高速A/D转换器的使用

安捷伦公司的HPE1413C A／D转换器基于VXI总线，可采用多种不同的方式读出测量结果，适合于多种不同物理量的测量。文中介绍了HPE1413CA／D转换器硬件设置、软件编程步骤及使用实例。     

高速自隔离三重扩散技术研究

本文介绍双极IC中自隔离的三重扩散(3D)技术的特点和工艺路线,给出了采用全离子注入工艺制作的器件特性,探讨了工艺技术中的关键问题,指出,浅结离子注入与退火条件的选择是影响器件性能的主要因素。     

高速CMOS电路的单元延时模型分析

由于互连线电阻引起的时序问题对IC设计带来了越来越大的影响，选取精确的模型来计算延时变得非常重要。本文结合传统延时模型的特点，对有效电流源模型(ECSM)作了改进，通过分段线性方法精确地匹配了负载激励点波形的非线性特性，有效地解决了原模型中存在的不足。经理论分析和实验验证，该模型能快速有效地求解延时，能很好地应用于超深亚微米工艺下的时序分析。