反馈式ECL记忆门的记忆性能和移位计数器

经过数学论证表明,改进反馈式ECL(MFECL)门可在二个状态中任一态保持稳定,所以认为MFECL门就是一种ECL记忆门或D锁存器.提出了一种由两个ECL记忆门组成的ECL主从D触发器.在上述理论基础上,利用此主从D触发器设计出5进制移位型计数器.经过计算机模拟上述电路,验证了理论和电路的正确性.     

电流开关结构提高 LSI 逻辑速度

大规模集成电路逻辑设计者在电路尺寸和性能方面从事的逻辑结构却不是用作大规模集成电路的。原先设计的 DTL、TTL 和 ECL 结构是作为门功能的,而不是作为高集成功能的。这些电路结构的功率/延迟乘积约为80微微焦耳;典型的8毫微秒传播延迟的 TTL 门功耗约10毫瓦;而 ECL 门是0.9毫微秒,约90毫瓦。     

反馈式ECL记忆门的记忆性能和移位计数器

经过数学论证表明,改进反馈式ECL(MFECL)门可在二个状态中任一态保持稳定,所以认为MFECL门就是一种ECL记忆门或D锁存器.提出了一种由两个ECL记忆门组成的ECL主从D触发器.在上述理论基础上,利用此主从D触发器设计出5进制移位型计数器.经过计算机模拟上述电路,验证了理论和电路的正确性.     

集成超高速ECL电路现状

大家知道,数字电路有饱和型和非饱和型两种,在实现高速方面,饱和型以TTL为代表,非饱和型以发射极耦合逻辑(ECL)为代表。功耗方面以TTL较低,速度方面以ECL较高。因此ECL电路成为超高速电路的重要方式,几年来有了较大的发展,见表1所示。目前ECL电路的应用到计算机中的水平和生产水平是传递延迟为1毫微秒的电路。目前的研究水平是O.3～O.5毫微秒的ECL电路。目前国外应用超高速ECL电路的高性能计算机有IBM公司的360/85、370/195,CDC公司的7600、星—100,通用电气公司的655计算机等。     

ECL结构的PFDCP设计

设计了一种基于ECL结构的PFDCP.PFD电路采用传统构架,通过增加延迟单元的方法克服死区问题,延迟单元由ECL的逻辑门构成.PFD可以工作在0.15 MHz到2 MHz的输入频率范围之间.同时设计了一个高精度低失配的电荷泵,可以提供四种不同大小的电流.PFDCP设计和仿真采用JAZZ 0.35 μm的BICMOS SBC35工艺模型,电源电压5 V.电路仿真结果表明PFD的死区小于30 ps,CP的失配电流小于0.4%.     

高信息密度的ECL集成电路设计

本文从多值逻辑能提高集成电路处理信息量的观点出发对三值ECL高速集成电路进行研究.文中提出符合双极型晶体管工作原理的基本运算,并讨论了有关性质.在此基础上提出差动电流开关理论,并用于设计若干基本三值ECL电路.使用SPICE 2G5程序的计算机模拟表明,这些电路具有正确的逻辑功能及理想的静态与瞬态特性.     

安森美扩展高速逻辑产品组合

安森美半导体公司推出新一代的ECL(射极耦合逻辑)集成电路ECLinPS Plus系列的第二阶段产品。这些逻辑芯片不但可满足2.5V、3.3V及5V的电源需求,更可提供比市场上相似ECL逻辑产品高百分之三十的计算性能,以及更小的歪曲率。 ECLinPS Plus系列包括单一/多重门、多路复用器、正反器等产品组合。两种全新的计时电路IP111及     

NEC美国电子公司生产的TTL、CEL和MOS门阵列电路

据美刊《电子设计》1983年31卷2期报道,NEC(日本电气)美国电子公司电子产品事业部今年可望生产3000门ECL,500门TTL和10,000门CMOS门阵列电路。 目前,该公司的TTL、ECL和CMOS门阵列产品性能列举如下:     

一种ECL可编程分频器的研制

本文在分析TTL可编程分频器逻辑功能的基础上,设计了模数在1～16之间任意可变的ECL可编程分频器,利用SPICE电路模拟程序对电路进行了直流和瞬态分析。同时,针对超高速ECL电路的特点,完成了电路版图及工艺设计,并进行了工艺试制。做出了工作频率可达50MHz以上的ECL可编程分频器,比原TTL可编程分频器的工作频率提高了5倍之多。     

ECL集成电路的四值接口技术

本文介绍了适用于多值ECL电路设计的差动电流开关理论。在该理论中,分别用开关变量和四值信号变量来描写ECL电路中差动晶体管对的开关状态和信号,并引入此两类变量之间的联结运算,以描写电路内部开关元件与信号的相互作用过程。基于该理论,本文对两种接口电路2-4编码器和4-2译码器进行了设计。应用SPICE程序对设计电路的计算机模拟表明,两种电路均具有正确的逻辑功能、理想的DC转移特性和瞬态特性。由于该接口电路具有与二值电路兼容的集成工艺、电源设备、逻辑级差和瞬态特性,因此它可用作现有二值ECL集成电路的输入输出接口,从而达到减少芯片的引脚数和片间连接的目的。     

A fully compensated active pull-down ECL circuit withself-adjusting driving capability

A new active pull-down emitter-coupled logic (ECL) circuit having full compensation against fluctuations in supply voltage and temperature is proposed. This circuit needs no capacitors but a feed-back circuit to adjust its pull-down capability to its load capacitance. The speed performance is compared between the active pull-down ECL circuit and the conventional ECL circuit using 0.8 μm SPICE parameters. The active pull-down ECL circuit is twice as fast as the conventional ECL circuit under the load capacitance of 0.8 pF with the same power dissipation. The relation between the power dissipation and the operating frequency is compared among the CMOS, the conventional ECL, and the active pull-down ECL circuits. The comparison adapts a new method in which the circuit parameters are optimized at each operating frequency. The SPICE simulation using this new method shows the conventional ECL circuit has a lower power dissipation than the CMOS circuit, even in the low operating frequency region of 100 MHz. The new active pull-down ECL circuit has the lowest power dissipation among the three circuits. The power dissipation of this circuit shows 47% lower than the CMOS circuit and 29% lower than the conventional ECL circuit at the operating frequency of 600 MHz and the load capacitance of 0.8 pF     

具有有源下拉电路和图腾柱式输出结构的CML门电路

本文提出了一种高速低功耗、具有有源下拉电路和图腾柱式输出结构的ＣＭＬ（简称ＭＣＭＬ）门电路；详细地阐述了ＭＣＭＬ门电路的工作原理和优点；列出了电路仿真结果；并对其电路特性与ＥＣＬ和ＡＰＤ－ＥＣＬ电路进行了比较。     

2.5-V bipolar/CMOS circuits for 0.25-μm BiCMOS technology

An ECL circuit with an active pull-down device, operated from a CMOS supply voltage, is described as a high-speed digital circuit for a 0.25-μm BiCMOS technology. A pair of ECL/CMOS level converters with built-in logic capability is presented for effective intermixing of ECL with CMOS circuits. Using a 2.5-V supply and a reduced-swing BiNMOS buffer, the ECL circuit has reduced power dissipation, while still providing good speed. A design example shows the implementation of complex logic by emitter and collector dottings and the selective use of ECL circuits to achieve high performance     

Power partition and emitter size optimization for bipolar ECLcircuit

An automated approach for optimizing the performance of a bipolar ECL circuit is described. A quadratic equation representing an approximate surface is used to express the circuit delay in terms of the power partition and current densities in the current-switch and emitter-follower stages. During the iteration of the optimization process, the optimum obtained from each approximate surface is used as the nominal point for the next iteration. As the nominal point converges to the optimal, the approximate surface converges to a section of the real optimum surface. This methodology transforms the circuit optimization into a multivariable optimization problem and is shown to provide an optimum design with circuit analysis accuracy. The design considerations for high-performance ECL circuits are also discussed     

Non-quasi-static effects in advanced high-speed bipolar circuits

A detailed study on the non-quasi-state (NQS) effects in advanced high-speed bipolar circuits is presented. An NQS Gummel-Poon-compatible lumped circuit model, which accounts for carrier propagation delays across various quasi-neutral regions in bipolar devices, is implemented in the ASTAP circuit simulator. The effects are then evaluated and compared with those for the conventional Gummel-Poon model for the emitter-coupled logic (ECL) circuit, the non-threshold-logic (NTL) circuit, and various advanced circuits utilizing active-pull-down schemes. For the ECL circuit, the effect decreases with reduced power level and increased loading. For the NTL circuit, due to its front-end configuration, the effect is more significant than that for the ECL circuit but tends to increase with reduced power level. As the passive resistors (and the associated parasitic RC effect) are decoupled from the delay path and the circuit delay is made more intimately related to the intrinsic speed of the devices in various advanced active-pull-down circuits, the delay degradation due to NQS effect becomes more significant     

一种超高速÷2ECL分频器

本文描述了采用氧化物隔离等平面S工艺、离子注入技术和快速热退火,以及采用电阻网络反馈信号的改进型D触发器的优化电路的设计方法研制的1500MHz÷2ECL分频器。电路在常温下的工作速度超过2000MHz,即使在85℃的高温条件下,其最高工作频率也超过1900MHz,完全满足了用户的要求。     

Analyzing ECL's noise margin

Although CMOS technologies continue to dominate VLSI, advanced bipolar technologies are emerging as a viable alternative, thanks to improvements in circuit density and yield. These bipolar technologies are chiefly directed towards very high-speed applications, mostly in the form of emitter coupled logic (ECL) or current mode logic (CML) circuit configurations. A key advantage of the ECL/CML circuit configuration is its ability to operate reliably at low voltage swings. There is, however, a trade-off: as the voltage swing is reduced, so also is the ability of the circuit to withstand unwanted input voltage variations, i.e., noise. While the speed and power dissipation characteristics of ECL/CML have received considerable analytical and quantitative treatment in the literature, the noise margin has earned little analytical attention. In this article, the authors derive an improved expression for the static noise margin of ECL     

基于开关信号理论的控阈技术与三值ECL施密特电路

基于开关信号理论，本文对ＥＣＬ电路中的阈值控制进行了研究，建立了用于描述旋密特电路中阈值可控开关工作过程听数学表示式。在此基础上设计了具有二次跳阈反应的三值ＥＣＬ旋密特电路。对所设计电路的ＰＳＰＩＣＥ模拟表明它具有理想的施密特电路特性。     

基于多值逻辑的高速ECL模糊控制表查询电路

该文指出了硬件实现模糊控制表查询电路存在结构复杂、用数字式实现时设计困难等问题,提出了将模糊控制表转换为多值K图,利用K图从开关级设计模糊控制表查询电路的方法,并用此方法具体设计了一个论域元素个数为5的ECL模糊控制表查询电路。从设计实例看,该文提出的设计方法简单易行,而设计的ECL查询电路具有结构简单和高速推理的优点。