Novel low leakage and energy efficient dual-pullup/dual-pulldown repeater

Transistor threshold voltage (V_t) scaling causes higher power consumption by increasing the subthreshold leakage and short-circuit currents in CMOS circuits. Leakage currents are significant contributors to the overall power consumption of digital systems-on-chip as threshold voltage, channel length, and gate oxide thickness are reduced with CMOS technology scaling. A new dual-pullup/dual-pulldown (DPU/DPD) repeater is proposed in this paper for higher energy efficiency in low-voltage and low-frequency applications. The standby mode leakage power consumption is reduced by 59.11% with the proposed clock tree as compared to the conventional 3 level H-tree operating with a power supply voltage of 1.0V in a 45 nm CMOS technology. The short-circuit currents are suppressed by selectively employing high-V_t transistors in the repeaters. The clock network with the proposed buffer lowers the active mode energy consumption by up to 24.91% as compared to a conventional clock tree under equal silicon area constraint. Post layout results reveal that the statistical spread of clock skew in the DPU/DPD H-tree is also 20.60% lower than the conventional H-tree network.     

Standby/active mode logic for sub-1-V operating ULSI memory

New gate logics, standby/active mode logic I and II, for future 1 Gb/4 Gb DRAMs and battery operated memories are proposed. The circuits realize sub-l-V supply voltage operation with a small 1-μA standby subthreshold leakage current, by allowing 1 mA leakage in the active cycle. Logic I is composed of logic gates using dual threshold voltage (Vt) transistors, and it can achieve low standby leakage by adopting high Vt transistors only to transistors which cause a standby leakage current. Logic II uses dual supply voltage lines, and reduces the standby leakage by controlling the supply voltage of transistors dissipating a standby leakage current. The gate delay of logic I is reduced by 30-37% at the supply voltage of 1.5-1.0 V, and the gate delay of logic II is reduced by 40-85% at the supply voltage of 1.5-0.8 V, as compared to that of the conventional CMOS logic     

Analysis of leakage reduction technique on FinFET based 7T and 8T SRAM cells

We propose a FinFET based 7T and 8T Static Random Access Memory (SRAM) cells. FinFETs also promise to improve challenging performance versus power tradeoffs. Designers can run the transistors more rapidly and use the similar amount of power, compared to the planar CMOS, or run them at the similar performance using less power. The aim of this paper is to reduce the leakage current and leakage power of FinFET based SRAM cells using Self-controllable Voltage Level (SVL) circuit Techniques in 45nm Technology. SVL circuit allows supply voltage for a maximum DC voltage to be applied on active load or can reduce the supplied DC voltage to a load in standby mode. This SVL circuit can reduce standby leakage power of SRAM cell with minimum problem in terms of chip area and speed. High leakage currents in submicron regimes are primary contributors to total power dissipation of bulk CMOS circuits as the threshold voltage V _th, channel length L and gate oxide thickness t _ox are scaled down. The leakage current in the SRAM cell increases due to reduction in channel length of the MOSFET. Two methods are used; one method in which the supply voltage is reduced and other method in which the ground potential is increased. The Proposed FinFET based 7T and 8T SRAM cells have been designed using Cadence Virtuoso Tool, all the simulation results has been generated by Cadence SPECTRE simulator at 45nm technology.     

Edge hole direct tunneling leakage in ultrathin gate oxidep-channel MOSFETs

This paper examines the edge direct tunneling (EDT) of holes from p⁺ polysilicon to underlying p-type drain extensions in off-state p-channel MOSFETs having ultrathin gate oxides that are 1.2 nm-2.2 nm thick. It is for the first time found that for thinner oxides, hole EDT is more pronounced than both conventional gate-induced drain leakage (GIDL) and gate-to-channel tunneling. As a result, the induced gate and drain leakage is more accurately measured per unit gate width. Terminal currents versus input voltage are measured from a CMOS inverter with gate oxide thickness T_OX=1.23 nm, exhibiting the impact of EDT in two standby modes. For the first time, a physical model is derived for the oxide field E_OX at the gate edge by accounting for the heavy and light holes' subbands in the quantized accumulation polysilicon surface. This model relates E_OX to the gate-to-drain voltage, oxide thickness, and doping concentration of the drain extension. Once E_OX is known, an existing direct tunneling (DT) model consistently reproduces EDT current-voltage (I-V), and the tunneling path size extracted falls adequately within the gate-to-drain overlap region. The ultimate oxide thickness limit due to hole EDT is projected     

A 1-V, 10-MHz, 3.5-mW, 1-Mb MTCMOS SRAM: with charge-recyclinginput/output buffers

This paper presents a high-speed and low-power SRAM for portable equipment, which is operated by a single battery cell of around 1 V. Its memory cells are made up of high-threshold-voltage (high-V_th) MOSFETs in order to suppress the power dissipation due to large subthreshold leakage currents. For designing peripheral circuitry, we use SRAM's special feature that input signals of each logic gate during the standby time can be predicted. Low-V_th MOSFETs are assigned for the critical paths of memory-cell access. The leakage current in each logic gate is reduced by high-V_th MOSFETs, which are cut off during standby. The high-V_th, MOSFET in one logic gate can be shared with another logic gate in order to enlarge effective channel width. To shorten the readout time, a step-down boosted-wordline scheme suitable for current-sense readout and a new half-swing bidirectional double-rail bus are used. The data-writing time is halved by means of a pulse-reset wordline architecture. To reduce the power dissipation, a 32-divided memory array structure is employed with a new redundant address-decoding scheme. Also, data transition detectors and a charge-recycling technique are employed for reducing the power dissipation of data-I/O buffers. A 64-K-words×16-bits SRAM test chip, which was fabricated with a 0.5-μm multithreshold voltage CMOS (MTCMOS) process, has demonstrated a 75-ns address access time at a 1-V power supply. The power dissipation during standby is 1.2 μW, and that at a 10-MHz read operation with the modified checkerboard test pattern is 3.9 mW for 30-pF loads     

A 90-nm CMOS Low-Power GSM/EDGE Multimedia-Enhanced Baseband Processor With 380-MHz ARM926 Core and Mixed-Signal Extensions

To meet the widely varying speed and power requirements of multifunctional mobile devices, an appropriate combination of technology features, circuit-level low-power techniques, and system architecture is implemented in a GSM/Edge baseband processor with multimedia and mixed-signal extensions. Power reduction techniques and performance requirements are derived from an analysis of relevant use cases and applications. The 44 mm² baseband processor is fabricated in a 90-nm low-power CMOS technology with triple-well option and dual-gate oxide core devices. The ARM926 core achieves a maximum clock frequency of 380 MHz at 1.4-V supply due to the usage of thin oxide (1.6 nm) devices. Power dissipation can be adapted to the performance requirements by means of combined voltage and frequency scaling to reduce active power consumption in medium-performance mode by 68%. To reduce leakage currents during standby mode, large SRAM blocks, nFET sleep transistors, and circuit components with relaxed performance requirements are implemented using devices with 2.2-nm gate oxide thickness     

Compact class AB CMOS current mirror

Current mirrors are, together with differential pairs, the most common analogue building blocks in modern analogue and mixed-signal integrated circuits. Desirable features of current mirrors include: low standby power dissipation, wide input and output current swings, low supply voltage requirements, accurate current copy, and high linearity. Conventional class A topologies are unable to achieve simultaneously low quiescent power consumption and wide current swings, since they have maximum input and output currents limited by the DC bias currents. To overcome this shortcoming, class AB current mirrors have been proposed, which feature maximum currents not limited by the quiescent currents and reduced sensitivity to process tolerances [1]. Unfortunately, the additional circuitry required to achieve class AB operation often increases supply voltage requirements. For instance, the most common approach to achieve a class AB CMOS current mirror requires stacking of two MOS gate?source voltages [2]. This additional circuitry also often increases standby power consumption and adds extra intrinsic capacitances at the internal nodes. Another common issue is that quiescent currents are often dependent on supply voltage, process variations or temperature [2]. Other approaches are based on SC dynamic biasing [3], requiring the generation of two non-overlapping clock signals and suffering from charge injection errors.     

Leakage scaling in deep submicron CMOS for SoC

In this paper, we demonstrate the effects of CMOS technology scaling on the high temperature characteristics (from 25°C to 125°C) of the four components of off-state drain leakage (I_off ) (i.e. subthreshold leakage (I_sub), gate edge-direct-tunneling leakage (I_EDT), gate-induced drain-leakage (I_GIDL), and bulk band-to-band-tunneling leakage (I_B-BTBT)). In addition, the high temperature characteristics of I_off with reverse body bias (V_B) for the further reduction of the standby leakage are also demonstrated. The discussion is based on the data measured from three CMOS logic technologies (i.e., low-voltage and high performance (LV), low-power (LP), and ultra-low-power (ULP)) and three generations (0.18 μm, 0.15 μm, and 0.13 μm). Experiments show that the optimum V_B, which minimizes I_off, is a function of temperature. The experiments also show that for CMOS logic technologies of the next generations, it is important to control I_B-BTBT and I_GIDL by reducing effective doping concentration and doping gradient. It seems that in order to conform on-state gate leakage (I_G-on) and I_EDT specifications and to retain a 10-20% performance improvement at the same time, it is indispensable to use high-quality and high-dielectric-constant materials to reduce effective oxide thickness (EOT). The role of each leakage component in SRAM standby current (I_SB) is also analyzed     

Two silicon nitride technologies for post-SiO2 MOSFETgate dielectric

P-MOSFETs with 14 Å equivalent oxide thickness (EOT) were fabricated using both JVD Si₃N₄ and RTCVD Si₃ N₄/SiO_xN_y gate dielectric technologies. With gate length down to 80 nm, the two technologies produced very similar device performances, such as drive current and gate tunneling current. The low gate leakage current, good device characteristics and compatibility with conventional CMOS processing technology make both nitride gate dielectrics attractive candidates for post-SiO₂ scaling. The fact that two significantly different technologies produced identical results suggests that the process window should be quite large     

Minimizing floating-body-induced threshold voltage variation inpartially depleted SOI CMOS

Pulse propagation problems associated with dynamic floating-body effects, e.g., pulse stretching, is measured in partially depleted SOI CMOS inverter chains. Pulse stretching is found to be dependent on pulse frequency and V_DD. Such behavior is attributed to floating-body-induced transient threshold voltage variation in partially depleted SOI CMOS devices due to floating-body charge imbalance between logic states during CMOS switching. Such an imbalance can be minimized through proper device design because of the different dependencies of the gate and drain depletion charges on channel length, silicon film thickness, gate oxide thickness, channel doping, and supply voltage. This is confirmed by measuring the maximum transient threshold voltage variation in discrete partially depleted SOI NMOS devices in configurations which are predictive of CMOS switching behavior     

Characteristics and Modeling of Sub-10-nm Planar Bulk CMOS Devices Fabricated by Lateral Source/Drain Junction Control

Sub-10-nm planar bulk CMOS devices were demonstrated by a lateral source/drain (S/D) junction control, which consists of the notched gate electrode, shallow S/D extensions, and steep halo in a reverse-order S/D formation. Furthermore, the transport properties were also evaluated by using those sub-10-nm planar bulk MOSFETs. The direct-tunneling currents between the S/D regions, with not only the gate length but also the “drain-induced tunneling modulation (DITM)” effects, are clearly observed for the sub-10-nm CMOS devices at low temperature. Moreover, a quantum mechanical simulation reveals that the tunneling currents increase with the increase in the temperatures and gate voltages, resulting in a certain amount of contribution to the subthreshold current even at 300 K. Therefore, it is strongly required that the supply voltage should be reduced to suppress the DITM effects for the sub-10-nm CMOS devices even under the room-temperature operations.     

High-performance CMOS circuits fabricated by excimer-laser-annealedpoly-Si TFTs on glass substrates

High-performance CMOS circuits are fabricated from excimer-laser-annealed poly-Si TFTs on a glass substrate (300×300 mm). The propagation delay time of the 121 stage CMOS ring oscillators with 0.5 μm gate length is 0.18 nsec at 5 V supply voltage. The maximum operating frequency of the 40-stage shift registers with 1 μm gate length is 133 MHz at 5 V supply voltage. This value is high enough for peripheral CMOS circuits with line-at-a-time addressing     

Silicon-gate n-well CMOS process by full ion-implantation technology

A silicon-gate n-well CMOS process for an application of digital circuits operated by TTL compatible supply voltage was developed. Full ion-implantation technology, a new photolithography technique, n⁺-doped polysilicon gate which contain no boron impurities, and thin gate oxide of 65 nm can realize CMOS circuits of 2-µm gate length. Average impurity concentrations measured from substrate bias effect of MOSFET's and junction depth are in good agreement with those expected from impurity profiles calculated by a simple diffusion theory. So, the process design for CMOS circuits operated by any supply voltage is possible, by adjusting threshold voltages. The process can easily be extended to n-MOS/CMOS process (E/D MOS and CMOS on the same chip), if a photomask to fabricate depletion-type n-MOSFET's is provided.     

Low-voltage hot-electron currents and degradation indeep-submicrometer MOSFETs

Hot-electron currents and degradation in deep submicrometer MOSFETs at 3.3 V and below are studied. Using a device with L _eff=0.15 μm and T_ox=7.5 nm, substrate current is measured at a drain bias as low as 0.7 V; gate current is measured at a drain bias as low as 1.75 V. Using the charge-pumping technique, hot-electron degradation is also observed at drain biases as low as 1.8 V. These voltages are believed to be the lowest reported values for which hot-electron currents and degradation have been directly observed. These low-voltage hot-electron phenomena exhibit similar behavior to hot-electron effects present at higher biases and longer channel lengths. No critical voltage for hot-electron effects (such as the Si-SiO₂ barrier height) is apparent. Established hot-electron degradation concepts and models are shown to be applicable in the low-voltage deep submicrometer regime. Using these established models, the maximum allowable power supply voltage to insure a 10-year device lifetime is determined as a function of channel length (down to 0.15 μm) and oxide thicknesses     

High-linearity high-current-drivabilityGa0.51In0.49P/GaAs MISFET usingGa0.51In0.49P airbridge gate structure grown byGSMBE

A novel structure Ga_0.51In_0.49P/GaAs MISFET with an undoped Ga_0.51In_0.49P layer serving as the airbridge between active region and gate pad was first designed and fabricated. Wide and flat characteristics of g_m and f_max versus drain current or gate voltage were achieved. The device also showed a very high maximum current density (610 mA/mm) and a very high gate-to-drain breakdown voltage (25 V). Parasitic capacitances and leakage currents were minimized by the airbridge gate structure and thus high f_T of 22 GHz and high f_max of 40 GHz for 1 μm gate length devices were attained. To our knowledge, both were the best reported values for 1 μm gate GaAs channel FET's     

An 18 ns CMOS/SOS 4K static RAM

A high-speed CMOS/SOS 4K word/spl times/1 bit static RAM is described. The RAM features a MoSi/SUB 2/ gate CMOS/SOS technology with 2 /spl mu/m gate length and 500 /spl Aring/ thick gate oxide. Performance advantage of SOS over bulk is discussed for the scaled-down MOS LSI with 1-2 /spl mu/m gate. A standard 6-transistor CMOS cell and a two-stage sense amplifier scheme are utilized. In spite of the rather conservative 3.5 /spl mu/m design rule except for the 2 /spl mu/m gate length, the cell size of 36/spl times/36 /spl mu/m, the die size of 3.11/spl times/4.07 mm, and the typical read access and cycle time of 18 ns are achieved. The active and standby power dissipation are 200 mW and 50 /spl mu/W, respectively.     

Characterization of 1.9- and 1.4-nm ultrathin gate oxynitride by oxidation of nitrogen-implanted silicon substrate

For gate oxide thinned down to 1.9 and 1.4 nm, conventional methods of incorporating nitrogen (N) in the gate oxide might become insufficient in stopping boron penetration and obtaining lower tunneling leakage. In this paper, oxynitride gate dielectric grown by oxidation of N-implanted silicon substrate has been studied. The characteristics of ultrathin gate oxynitride with equivalent oxide thickness (EOT) of 1.9 and 1.4 nm grown by this method were analyzed with MOS capacitors under the accumulation conditions and compared with pure gate oxide and gate oxide nitrided by N/sub 2/O annealing. EOT of 1.9- and 1.4-nm oxynitride gate dielectrics grown by this method have strong boron penetration resistance, and reduce gate tunneling leakage current remarkably. High-performance 36-nm gate length CMOS devices and CMOS 32 frequency dividers embedded with 57-stage/201-stage CMOS ring oscillator, respectively, have been fabricated successfully, where the EOT of gate oxynitride grown by this method is 1.4 nm. At power supply voltage V/sub DD/ of 1.5 V drive current Ion of 802 /spl mu/A//spl mu/m for NMOS and -487 /spl mu/A//spl mu/m for PMOS are achieved at off-state leakage I/sub off/ of 3.5 nA//spl mu/m for NMOS and -3.0 nA//spl mu/m for PMOS.     

DC I-V characteristics of field emitter triodes

A simple model that is applicable to Spindt-type emitter triodes is presented. Experimentally, it has been observed that the gate current at zero collector voltage follows the same Fowler-Nordheim law as the collector current at high collector voltage, and that for low emission current densities, the sum of gate and collector currents is constant for any collector voltage and is given by the Fowler-Nordheim current I_FN. Based on these observations, a simple model has been developed to calculate the I-V characteristics of a triode. By measuring the Fowler-Nordheim emission, emission area and field enhancement can be obtained assuming a value for the barrier height. Incorporating the gate current, the collector current can be calculated from I_c=I_FN-I_g as a function of collector voltage. The model's accuracy is best at low current density. At higher emission currents, deviations occur at low collector voltages because the constancy of gate and collector currents is violated     

CMOS current steering logic for low-voltage mixed-signal integratedcircuits

A quiet logic family-complementary metal-oxide-semiconductor (CMOS) current steering logic (CSL)-has been developed for use in low-voltage mixed-signal integrated circuits. Compared to a CMOS static logic gate with its output range of ΔV_logic≈V_dd , a CSL gate swings only ΔV_logic≈V_T+0.25 V because the constant current supplied by the PMOS load device is steered to ground through either an NMOS diode-connected device or switching network. Owing to the constant current, digital switching noise is 100× smaller than in static logic. Another useful feature which can be used to calibrate CSL speed against process, temperature, and voltage variations is propagation delay that is approximately constant versus supply voltage and linear with bias current. Several CSL circuits have been fabricated using 0.8 and 1.2 μm high-V_T n-well CMOS processes. Two self-loaded 39-stage ring oscillators fabricated using the 1.2 μm process (1.2 V power supply) exhibited power-delay products of 12 and 70 fJ with average propagation delays of 0.4 and 0.7 ns, respectively. High-V_T and low-V_T CSL ALU's were operational at V _dd≈=0.70 V and V_dd≈0.40 V, respectively     

Cutoff frequency and propagation delay time of 1.5-nm gate oxideCMOS

The high-frequency AC characteristics of 1.5-nm direct-tunneling gate SiO₂ CMOS are described. Very high cutoff frequencies of 170 GHz and 235 GHz were obtained for 0.08-μm and 0.06-μm gate length nMOSFETs at room temperature. Cutoff frequency of 65 GHz was obtained for 0.15-μm gate length pMOSFETs using 1.5-nm gate SiO₂ for the first time. The normal oscillations of the 1.5-nm gate SiO₂ CMOS ring oscillators were also confirmed. In addition, this paper investigates the cutoff frequency and propagation delay time in recent small-geometry CMOS and discusses the effect of gate oxide thinning. The importance of reducing the gate oxide thickness in the direct-tunneling regime is discussed for sub-0.1-μm gate length CMOS in terms of high-frequency, high-speed operation