超低功耗逐次逼近寄存器型模数转换器的设计

采用逐次逼近方式设计了一个12 bit的超低功耗模数转换器(ADC).为减小整个ADC的芯片面积、功耗和误差,提高有效位数(ENOB),在整个ADC的设计过程中采用了一种改进的分段电容数模转换器(DAC)阵列结构.重点考虑了同步时序产生电路结构,对以上两个模块的版图设计进行了精细的布局.采用0.18 μm CMOS工艺,该ADC的信噪比(SNR)为72 dB,有效位数(ENOB)为11.7 bit,该ADC的芯片面积只有0.36 mm2,典型的功耗仅为40 μW,微分非线性误差小到0.6 LSB、积分非线性误差只有0.63 LSB.整个ADC性能达到设计要求.     

应用于高速高精确度流水线ADC参考电压缓冲器

通过分析流水线数字转换器(ADC)中参考电压缓冲器的工作过程,提出了相应的负载模型,并推导出缓冲器的指标,设计了一种能用于高速高精确度流水线ADC的参考电压缓冲器。该缓冲器采用了改进的开环结构,降低了设计复杂度、功耗和面积,同时采用增强型源跟随结构,提高了缓冲器驱动能力和稳定性。该参考电压缓冲器采用华力55 nm CMOS工艺进行电路和版图设计,版图面积为320 μm×260 μm。Spectre后仿真结果表明,参考电压缓冲器功耗为3 mA,建立时间为4.3 ns,成功应用于60 MS/s 12 bit流水线ADC。     

8位高速低功耗流水线型ADC的设计技术研究

采用7级子ADC流水线结构设计了一个8位80MS/s的低功耗模数转换电路。为减小整个ADC的芯片面积和功耗,改善其谐波失真和噪声特性,重点考虑了第一级子ADC中MDAC的设计,将整个ADC的采样保持电路集成在第一级子ADC的MDAC中,并且采用逐级缩放技术设计7级子ADC的电路结构,在版图设计中考虑每一级子ADC中的电容及放大器的对称性。采用0.18μm CMOS工艺,该ADC的信噪比（SNR）为53dB,有效位数（ENOB）为7.98位,该ADC的芯片面积只有0.56mm2,典型的功耗电流仅为22mA。整个ADC性能达到设计要求。     

12位逐次逼近模数转换器关键设计技术研究

采用逐次逼近方式设计了一个12位的超低功耗模数转换电路。为减小整个ADC的芯片面积、功耗和误差,提高有效位数,对整个ADC的采样保持电路结构进行了精确的设计,重点考虑了其中的高精度比较器电路结构;对以上两个模块的版图设计进行了精细的布局。采用0.18μmCMOS工艺,该ADC的信噪比（SNR）为72dB,有效位数（ENOB）为11.7位,该ADC的芯片面积只有0.36mm2,典型的功耗仅为40μW,微分非线性误差DNL小到0.6LSB、积分非线性误差INL只有0.63LSB。整个ADC性能达到设计要求。     

采用双采样结构和Class-AB OTA的低功耗14bit，51.2KS/s扩展计数型ADC设计

本文设计并实现了一种14bit,51.2KS/S扩展计数型模数变换器(ADC)。该ADC采用两种技术来降低电路的功耗。首先,提出了一种基于全浮空双线性(fully-floating bilinear)积分器的双采样结构,并利用这种结构降低时钟频率。其次,采用了AB类运算跨导放大器(OTA)来提高电路的功耗效率。另外,该ADC还采用了斩波技术消除1/f噪声的影响。该ADC结构采用0.18μm CMOS工艺进行了实现,单个ADC的面积仅为0.04mm2。其转换速率为51.2KS/s,测试所得无杂散动态范围(SFDR)为94dB,有效位数(ENOB)为11.6位,电源电压为1.8V,功耗为77μW。该ADC的优值仅为0.48pJ/step。     

一种用于10位50 MS/s流水线ADC的MDAC

利用运放共享技术,设计了一种用于10位50 MS/s流水线ADC的增益D/A转换器(MDAC).采用SMIC 0.25 μm 1P5M标准数字CMOS工艺,整个MDAC模块的版图面积为0.064 mm2.仿真结果表明,在50 MHz采样率下、输入信号为2 MHz(1.5 V振幅)正弦波时,整个电路模块的功耗为7.12 mW.     

一种带二进制校正的10位100 MS/s SAR ADC

基于SMIC 65 nm CMOS工艺,设计了一种带二进制校正的10位100 MS/s逐次逼近型模数转换器(SAR ADC),主要由自举开关、低噪声动态比较器、电容型数模转换器(C-DAC)、异步SAR逻辑以及数字纠错电路组成。电容型数模转换器采用带2位补偿电容的拆分单调电容转换方案,通过增加2位补偿电容,克服了电容型数模转换器在短时间内建立不稳定和动态比较器失调电压大的问题,使SAR ADC的性能更加稳定。数字纠错电路将每次转换输出的12位冗余码转换成10位的二进制码。使用Spectre进行前仿真验证,使用Virtuoso进行版图设计,后仿真结果表明,当电源电压为1.2 V、采样率为100 MS/s、输入信号为49.903 MHz时,该ADC的SNDR达到58.1 dB,而功耗仅为1.3 mW。     

一种采用电阻串复用结构的12位SAR ADC

针对带数字校准功能的逐次逼近模/数转换器(SAR ADC),提出将主DAC、校准DAC和基准电压产生电路的电阻串进行复用,从而显著减少了芯片面积,降低了功耗。相比6+6两段电容结构DAC,采用电阻电容混合结构的主DAC和校准DAC节约了37%的版图面积。在0.18μm CMOS工艺下,通过Hspice仿真,SAR ADC的DNL和INL均小于0.4LSB,SNR为75dB。系统正常工作时,总功耗为3.1mW,比不采用电阻串复用的结构减少0.9mW。     

应用于无线传感网络的低功耗10bit 300Ksps多通道逐次逼近型模数转换器的设计

本文给出了一款可应用于无线传感网络的低功耗10bit 300Ksps的逐次逼近型模数转换器(SAR ADC)的设计。采用了单端结构低功耗的拆分式电容阵列DAC和具有轨到轨输入级的比较器来实现本文中的ADC,可以减小功耗同时扩展满量程输入范围。为了实现功耗优化,采用2V的低电源电源供电。设计的ADC还具有4个模拟信号通道,使其更适用于无线传感网络的应用。电路样片采用3.3V 0.35μm 2P4M CMOS工艺实现,占用了1.23mm2的芯片面积,测试结果表明在2V供电166Ksps的采样速率下,ADC的功耗只有200uW,计算得到的信噪比为58.25dB,有效位数为9.38bit,品质因子FOM为4.9pJ/conversion-step。     

一种12位4 MS/s异步SAR ADC

设计了一种12位4 MS/s的异步逐次逼近型模数转换器(SAR ADC)。采用一种既能节省开关动态功耗又能减小电容面积的开关切换策略,与传统结构相比,开关动态切换功耗节省了95%,电容总面积减小了75%。为了避免使用高频时钟,采用了异步控制逻辑,采样开关采用栅压自举开关以便提高ADC的线性度,动态锁存比较器的使用减小了静态功耗,片上集成了电压参考电路和相关驱动电路。基于SMIC 0.18 μm CMOS工艺,在1.8 V电源电压和4 MS/s转换速率条件下,经后仿真得到ADC的信号噪声失真比SNDR为70.2 dB,功耗仅为0.9 mW,品质因素FOM为109 fJ/conversion-step。     

一种10bit双通道流水线SAR ADC设计

为了提高模数转换器的采样频率并降低其功耗,提出一种10 bit双通道流水线逐次逼近型（SAR）模数转换器（ADC）。提出的ADC包括两个高速通道,每个通道都采用流水线SAR结构以便低功率和减小面积。考虑到芯片面积、运行速度以及电路复杂性,提出的处于第二阶段的SAR ADC由1 bit FLASH ADC和6 bit SAR ADC组成。提出的ADC由45 nm CMOS工艺制作而成,面积为0.16 mm2。ADC的微分非线性和积分非线性分别小于0.36 最低有效位（LSB）和0.67 LSB。当电源为1.1 V时,ADC的最大运行频率为260 MS/s。运行频率为230 MS/s和260 MS/s的ADC的功率消耗分别为13.9 mW和17.8 mW。     

一种低功耗11位100MS/s采样率SAR ADC IP

本文介绍了一种双通道11位100MS/s采样率的混合结构SAR ADC IP。每个通道均采用flash-SAR结构以达到高速低功耗的目的。为了进一步降低功耗,flash和SAR中的比较器均采用全动态比较器。SAR中逐次逼近逻辑所需要的高速异步触发时钟采用门控环形振荡器产生。为了提高电容的匹配性,在版图设计中,采用底板包围顶板的MOM电容结构,有效减小电容寄生。本设计制造工艺为SMIC55nm的低漏电CMOS工艺,双通道的总面积为0.35mm2且核心面积仅为0.046 mm2。双通道模数转换器在1.2V供电电压下消耗的总电流为2.92mA。在2.4MHz输入和50MHz输入下的有效转换位数（ENOB）分别为9.9位和9.34位。计算得出本设计的FOM值为18.3fJ/conversion-step。     

A combined low power SAR capacitance-to-digital analog-to-digital converter for multisensory system

A combined successive approximation (SAR) capacitance-to-digital converter (CDC)/analog-to-digital converter (ADC) for biomedical multisensory system is presented in this paper. The two converters have same circuit blocks and can be exchanged by four switches. Capacitance or voltage from different sensing elements can be measured and converted to digital output directly. This single chip takes place of separated CDC and ADC so that the power consumption of the multisensory system is reduced. The asynchronous SAR circuit has low power and small area. A dynamic comparator with zero-static power is adopted. Switches are carefully designed to reduce the non-idealities of the converter. Several techniques, such as bootstrapped switches, bottom-plate sampling, dummy switches are used to improve the performance of the circuit. The CDC/ADC is fabricated in 0.18 μm CMOS process. Measurement results show that the ENOB of this 11 bits converter is 10.15 bits and its FOM is 45 fJ/conversion-step under 200 kHz sampling. The power consumption is 9.4 μW with 1.4 V power supply voltage and the core area is 0.1764 mm².     

An area-efficient 55 nm 10-bit 1-MS/s SAR ADC for battery voltage measurement

An area-efficient CMOS 1-MS/s 10-bit charge-redistribution SAR ADC for battery voltage measurement in a SoC chip is proposed. A new DAC architecture presents the benefits of a low power approach without applying the common mode voltage. The threshold inverter quantizer(TIQ)-based CMOS Inverter is used as a comparator in the ADC to avoid static power consumption which is attractive in battery-supply application. Sixteen level-up shifters aim at converting the ultra low core voltage control signals to the higher voltage level analog circuit in a 55 nm CMOS process. The whole ADC power consumption is 2.5 mW with a maximum input capacitance of 12 pF in the sampling mode. The active area of the proposed ADC is 0.0462 mm2 and it achieves the SFDR and ENOB of 65.6917 dB and 9.8726 bits respectively with an input frequency of 200 kHz at 1 MS/s sampling rate.     

一种3.3 V 9位50 MS/s CMOS流水线A/D转换器

设计了一种3.3 V 9位50 MS/s CMOS流水线A/D转换器。该A/D转换器电路采用1.5位/级,8级流水线结构。相邻级交替工作,各级产生的数据汇总至数字纠错电路,经数字纠错电路输出9位数字值。仿真结果表明,A/D转换器的输出有效位数(ENOB)为8.712位,信噪比(SNR)为54.624 dB,INL小于1 LSB,DNL小于0.6 LSB,芯片面积0.37 mm2,功耗仅为82 mW。     

A 12 bit 100 MS/s pipelined analog to digital converter without calibration

A 1.8 V 12 bit 100 MS/s pipelined analog to digital converter(ADC) in a 0.18μm complementary metal-oxide semiconductor process is presented.The first stage adopts a 3.5 bit structure to relax the capacitor matching requirements.A bootstrapped switch and a scaling down technique are used to improve the ADC's linearity and save power dissipation,respectively.With a 15.5 MHz input signal,the ADC achieves 79.8 dB spurious-free dynamic range and 10.5 bit effective number of bits at 100 MS/s.The power consumpt...     

一种基于新型低功耗开关策略的10 bit 120 MS/s SAR ADC

设计了一种10 bit 120 MS/s高速低功耗逐次逼近模数转换器(SAR ADC)。针对功耗占比最大的CDAC模块,基于电容分裂技术并结合C-2C结构,提出了一种输出共模保持不变的双电平高能效开关控制策略;在降低CDAC开关功耗的同时,摆脱了CDAC开关过程中对中间共模电平的依赖,使得该结构适用于低电压工艺。在速度提升方面,控制逻辑使用异步逻辑进行加速;比较器采用一种全动态高速结构,在保证精度的前提下其工作频率达到3 GHz; CDAC中插入冗余位,以降低高位电容对充电时间的要求。所设计的SAR ADC使用40 nm CMOS工艺实现,采用1.1 V低电压供电。在不同工艺角下进行性能仿真,结果显示,在120 MHz采样率下,有效位数为9.86 bit,无杂散动态范围为72 dB,功耗为2.1 mW,优值为18.9 fJ/(conv·step)。     

An 8-bit flash analog-to-digital converter with an array of redundant comparators

The circuit design and the topology of an 8-bit analog-to-digital converter (ADC) are presented. It is shown that the differential nonlinearity can be reduced by using three comparators and a majorizing element for formation of each bit of the thermometric code. Computer simulation and measurements of reference ADC chips fabricated using the UMC 180-nanometer CMOS technology confirmed the operability of the proposed design. A power consumption of 93 mW, an effective number of bits of 5.8, and a differential nonlinearity of 0.03 bits have been obtained     

A 12-bit 40 MS/s pipelined ADC with over 80 dB SFDR

This paper describes a 12-bit 40 MS/s calibration-free pipelined analog-to-digital converter (ADC), which is optimized for high spurious flee dynamic range (SFDR) performance and low power dissipation. With a 4.9 MHz sine wave input, the prototype ADC implemented in a 0.18-μm 1P6M CMOS process shows measured differential nonlinearity and integral nonlinearity within 0.78 and 1.32 least significant bits at the 12-bit level without any trimming or calibration. The ADC, with a total die area of 3. 1 × 2.1 mm~2, demonstrates a maximum signal-to-noise distortion ratio (SNDR) and SFDR of 66.32 and 83.38 dB, respectively, at a 4.9 MHz analog input and a power consumption of 102 mW from a 1.8 V supply.     

An Ultra-Energy-Efficient Wide-Bandwidth Video Pipeline ADC Using Optimized Architectural Partitioning

The classical pipeline analog-to-digital converter (ADC) architecture is analyzed to determine optimal partitioning for high effective resolution bandwidth (ERBW) and low-power consumption at reduced supply voltages. It is found that multibit inter-stage partitioning, in particular 2.5 bits per stage, is optimum for the reduction of power consumption in subsampling video ADCs for mobile/handheld receivers. To validate the analysis, a 1.5-V, 10-bit pipeline ADC for the digital video broadcast-handheld application was realized in a standard 3.3-V, 0.35-mum CMOS technology, with 2.5-2.5-2.5-4 partitioning employed. At the target sampling rate of 20.48 MS/s, measured results show that the converter achieves 56-dB SNR, 60-dB spurious-free dynamic range, 100-MHz ERBW and a power consumption of 19.5 mW. Energy consumption per conversion is only 0.19 pJ, making it the most energy-efficient 10-bit video-rate pipeline ADC reported to date