超深亚微米工艺下模拟IC仿真的MOSFET模型

对MOSFET器件特性、MOSFET建模方法和建模发展历程进行了回顾,分析了在模拟集成电路低功耗设计中比较流行的模型(BSIM3和EKV模型),对它们进行了比较,分析其各自的优点和缺点。结果表明获得能够精确地预测高性能模拟系统的模型是很困难的,而EKV模型在模拟集成电路的低功耗设计中具有一定的优势。     

SiC MOSFET栅极驱动电路研究综述

凭借碳化硅(SiC)材料的宽禁带、高击穿电场、高电子饱和速率和高导热性等优点,SiC MOSFET广泛应用在高压、高频等大功率场合。传统基于硅(Si)MOSFET的驱动电路无法完全发挥SiC MOSFET的优异性能,针对SiC MOSFET的应用有必要采用合适的栅驱动设计技术。目前,已经有很多学者在该领域中有一定的研究基础,为SiC MOSFET驱动电路的设计提供了参考。对现有基于SiC MOSFET的PCB板级设计技术进行了详细说明,并从开关速度、电磁干扰噪声以及能量损耗等方面对其进行了总结和分析,给出了针对SiC MOSFET驱动电路的设计考虑和建议。     

Junctionless MOS-Transistor with a Low Subthreshold Current

Russian Microelectronics - The junctionless MOS-transistors (junctionless MOSFET) have a number of advantages over conventional transistors in terms of the simplicity of design, manufacturing...     

MOSFET的驱动保护电路的设计与应用

率场效应晶体管由于具有诸多优点而得到广泛的应用;但它承受短时过载的能力较弱,使其应用受到一定的限制。分析了MOSFET器件驱动与保护电路的设计要求;计算了MOSFET驱动器的功耗及MOSFET驱动器与MOS-FET的匹配;设计了基于IR2130驱动模块的MOSFET驱动保护电路。该电路具有结构简单,实用性强,响应速度快等特点。在驱动无刷直流电机的应用中证明,该电路驱动能力及保护功能效果良好。     

A novel split-gate MOSFET design realized by a fully silicided gate process for the improvement of transconductance and output resistance

Work function tuning of nickel silicide (NiSi) gates was utilized to fabricate a novel split-gate MOSFET with improved device performance. The MOSFET with a NiSi split gate has been achieved by implanting antimony into the polysilicon gate from the drain side with a tilt angle, followed by a full nickel-silicidation process. The laterally nonuniform antimony implantation causes the NiSi gate work function to vary from the source side to the drain side due to the dopant segregation effect. Improved current drive and output resistance are observed in the MOSFET with such a NiSi split gate. Metal gate advantages and NiSi process simplicity were also realized in the split-gate process, and gate oxide quality did not degrade due to the low temperature process. This split-gate design is expected to be applicable in the nanoscale regime by optimizing process conditions.     

全耗尽SOI MOSFET的阈电压的解析模型

本文在近似求解全耗尽ＳＯＩＭＯＳＦＥＴ所满足的二维泊松方程的基础上，建立了阈电压的解析模型。     

模拟集成电路仿真中的UDSM MOSFET建模

对MOSFET器件特性、MOSFET建模方法和建模发展历程进行了回顾,重点分析了在模拟集成电路设计中较为流行的几种模型:BSIM3、EKV和SP2001模型,对其各自的优缺点进行了比较。结果表明,获得能够精确地预测高性能模拟系统的模型是很困难的;几种模型中,EKV模型在模拟集成电路的低功耗设计中具有一定的优势。     

A novel nanoscaled device concept: quasi-SOI MOSFET to eliminate the potential weaknesses of UTB SOI MOSFET

For the first time, a novel device concept of a quasi-silicon-on-insulator (SOI) MOSFET is proposed to eliminate the potential weaknesses of ultrathin body (UTB) SOI MOSFET for CMOS scaling toward the 35-nm gate length, and beyond. A scheme for fabrication of a quasi-SOI MOSFET is presented. The key characteristics of quasi-SOI are investigated by an extensive simulation study comparing them with UTB SOI MOSFET. The short-channel effects can be effectively suppressed by the insulator surrounding the source/drain regions, and the suppression capability can be even better than the UTB SOI MOSFET, due to the reduction of the electric flux in the buried layer. The self-heating effect, speed performance, and electronic characteristics of quasi-SOI MOSFET with the physical channel length of 35 nm are comprehensively studied. When compared to the UTB SOI MOSFET, the proposed device structure has better scaling capability. Finally, the design guideline and the optimal regions of quasi-SOI MOSFET are discussed.     

硅基液晶像素电路的研究

分析研究了微显示器件的场缓存技术与现有硅基液晶场缓存像素电路的结构特点,提出了一种新型的像素电路结构,此电路改变了以往电路结构中专门采用一个晶体管对像素电容进行放电的做法,通过同一个晶体管对像素电容进行充放电。电路经过Hspice仿真,对结果进行分析表明,其功能及特性符合设计要求,像素电容电荷保持率达到99%。电路具有结构简单,占用芯片面积小,像素电容电荷保持率高等优点,适合高亮度、高分辨率微显示器件的设计与制造。     

S波段GaN大功率放大器的设计与实现

本文介绍了基于新型GaN宽禁带半导体材料的大功率器件的特点和优势,采用微波仿真软件ADS对一款S波段的GaNMOSFET进行优化仿真设计,得到了良好的仿真结果,并给出了该功放的实物和测试数据。测试结果表明,该功放适用于2．1～2．7GHz,功率量级为IOOW,连续波和脉冲制式均可工作,对GaNMOSFET功率器件高增益...     

Trench MOSFET的研究与进展

研究总结了功率MOSFET器件与BJT器件相比的发展优势.介绍了作为VDMOSFET进一步发展的新型器件Trench MOSFET研究提出的背景及意义,并从其基本结构出发阐述了TrenchMOSFET与VDMOS相比的电学性能特点.最后对其发展现状,关键技术和结构参数及其发展趋势进行了概括、总结和展望.     

MOSFET失配的研究现状与进展

特定工艺条件下的器件失配程度限制了射频／模拟集成电路的设计精度和成品率。电路设计者需要精确的MOSFET失配模型来约束电路优化设计,版图设计者需要相应的设计规则来减小芯片失配。本文介绍了MOSFET失配的基本概念;回顾了MOSFET模型的研究进展及相关的版图设计技术、计算机仿真方法;总结了MOSFET失酉己对电路性能的影响及消除技术。最后探讨了MOSFET失配的研究趋势。     

Modular, portable, and easily simulated ESD protection networks for advanced CMOS technologies

This paper introduces a new distributed active MOSFET rail clamp network that offers surprising advantages in layout area efficiency, bus resistance tolerance, design modularity, and ease of reuse. SPICE simulation results using an extended vertical PNP bipolar transistor compact model and a new method for optimizing distributed rail clamp networks are presented along with chip-level test results.     

功率MOSFET的研究与进展

器件设计工艺、封装、宽禁带半导体材料和计算机辅助设计4大技术的发展进步使得功率MOSFET的性能指标不断达到新的高度。超级结技术使得高压功率MOSFET的导通电阻大大降低,降低栅极电荷和极间电容的改进沟槽工艺和横向扩散工艺技术进一步提高了低压功率MOSFET的优值因子,中小功率MOSFET继续朝着单片集成智能功率电子发展。功率MOSFET封装呈现出集成模块化、增强散热性和高可靠性的特点。基于宽禁带半导体材料SiC和GaN的功率MOSFET具有高温、高频和低功耗等优异性能,计算机辅助设计工具引领功率MOSFET在工艺设计、制造和电路系统应用方面快速发展。     

沟槽型MOSFET的发展

在功率变换器中沟槽型MOSFET取代功率二极管传递能量有两个优点：可以用PWM驱动电路灵活地控制MOSFET为不同的负载提供所需的能量;导通电阻低,能耗小。文章介绍了新研究出来的厚栅氧MOSFET,RSOMOSFET,集成肖特基二极管的沟槽型MOSFET,并对它们的机理和性能进行了阐述和分析。     

The impact of plasma-charging damage on the RF performance ofdeep-submicron MOSFET

Integration of RF analog functions with CMOS digital circuits offers great advantages in terms of cost and performance. Plasma-charging damage is known to degrade MOSFET characteristics and can be expected to impact the RF performance as well. In this work, we present for the first time a thorough investigation of the impact of plasma-charging damage on the RF characteristics of deep-submicron MOSFET. Our result shows that, with ultra-thin gate oxide, a 400°C forming gas annealing can completely recover the RF performance degradation due to plasma-charging damage     

基于MOSFET设计优化的功率驱动电路

在分析了功率MOSFET结构特性的基础上,讨论驱动电路的设计,从而优化MOSFET的驱动性能,提高设计的可靠性。     

Nanowire Crossbar Logic and Standard Cell-Based Integration

Nanowire crossbar is one of the most promising circuit solutions for nanoelectronics. However, it is still unclear whether or how they can be competitive in implementing logic circuits, as compared to their MOSFET counterparts. We analyze nanowire crossbars in area, speed, and power, in comparison with their MOSFET counterparts. We show nanowire crossbars do not scale well in terms of logic density and speed. To achieve performance close to their MOSFET counterparts, crossbar circuits need faster field-effect transistors (FETs) to compensate the high resistance of nanowires. Motivated by the analysis and comparative study, we propose a crossbar cells design based on judicious use of silicon nanowires. The crossbar cell is compatible with the conventional MOSFET fabrication and design methodologies, in particular, standard cell-based integrated circuit design. We evaluate logic circuits synthesized with crossbar cells and MOSFET cells based on the MCNC91 benchmark. The results show that crossbar cells can provide a density advantage of more than four times over the traditional MOSFET circuits with the same process technology, while achieving close performance and consuming less than one third power.      

Design and performance analysis of cylindrical surrounding double-gate MOSFET for RF switch

In this paper, we have analyzed the design parameters of Cylindrical Surrounding Double-Gate (CSDG) MOSFETs as an RF switch for the advanced wireless telecommunication systems. The proposed CSDG RF MOSFET is operated at the microwave regime of the spectrum. We emphasize on the basics of the circuit elements such as drain current, threshold voltage, resonant frequency, resistances at switch ON condition, capacitances, energy stored, cross talk and switching speed required for the integrated circuit of the radio frequency sub-system of the CSDG RF CMOS device and the physical significance of these basic circuit elements is also discussed. We observed that the total capacitance between the source to drain for the proposed CSDG MOSFET is more compared to the Cylindrical Surrounding Single-Gate (CSSG) MOSFET due to the greater drain current passing area of the CSDG MOSFET, which reveals that the isolation is better in the CSDG MOSFET compared to that of the simple double-gate MOSFET and single-gate MOSFET. We analyzed that the CSDG MOSFET stores more energy (1.4 times) as compared to the CSSG MOSFET. Therefore, the CSDG MOSFET has more stored energy. The ON-resistance of CSDG MOSFET is half than that of the double-gate MOSFET and single-gate MOSFET, which reveals that the current flow from source to drain in CSDG MOSFET is better than the double-gate MOSFET and single-gate MOSFET.     

Design for silicon infrared sensing MOSFET

A design is described for an infrared sensing MOSFET (IRFET). The high-gain high-resolution dc or static readout and inherent integrating and memory characteristics of the infrared sensing MOSFET should make it ideal for infrared imaging and target tracking applications employing a large-scale integrated array. The devices are based on silicon MOSFET technology where large-scale integrated arrays are routinely fabricated.