数字闭环光纤陀螺输出滤波器设计

在数字闭环光纤陀螺中,数字输出信号由高抽样率的反馈信号抽取得到,为避免抽取过程中发生频域混迭,应加入输出滤波器对信号进行低通滤波。根据多抽样率数字信号理论,采用多级抽取滤波器的设计方法,为陀螺设计输出滤波器。和一级低通滤波器比较说明,所设计的三级抽取滤波器,运算量小、滤波效果好。测试结果表明,加入输出滤波器不改变陀螺静态特性,抑制了振动时引起的高频误差,提高了陀螺精度。     

Improved Analysis of Implicit RMS Detectors

In this paper, the output voltage of the implicit root-mean-square (RMS) detector, which is composed of two voltage-to-current converters, a multiplier/divider, and a low-pass filter and excited by an input voltage comprising a single sinusoid, is approximated using a Fourier cosine series. Using this approximation, closed-form analytical expressions for the output voltage components of the implicit RMS detector are derived. The results obtained are compared with previously published results. This comparison shows that, using the proposed approximation, an improved estimation of the RMS value and the amplitudes of the second- and fourth-harmonic components of the implicit RMS detector can be achieved for any value of the input frequency and is not restricted to large values compared with the cutoff frequency of the low-pass filter.      

谐振式光纤陀螺的数字检测方案及其优化设计

提出了一种基于 DSP 芯片实现的双频率数字调制谐振式光纤陀螺系统的闭环检测方案。在此方案中,利用带通滤波器从探测器的输出光强信号中提取其基波频率的正弦信号,通过相关检测原理去掉干扰的噪声,并利用低通滤波器提取与探测器输出光强幅度直接成正比的直流信号,将其转换成相应的谐振频差,利用此频差即可求得陀螺的旋转角速度。此方案检测线路简单,操作方便,基于 DSP 芯片的实现则大大提高了系统处理速度。同时,还利用 Matlab 软件对检测系统中的滤波器参数进行了优化设计,提高了系统的检测精度。     

双STC时钟恢复电路的设计与实现

针对数字电视机顶盒的重要功能——多节目解码对播放同步的需求,设计了一种双时钟计数器(STC)的时钟恢复电路,并在支持先进音视频编码标准(AVS)的高清解码芯片中得到实现。该电路使用主从两个STC,主STC由一个混合型的锁相环驱动,该锁相环产生的27MHz时钟同时用于产生音视频解码时钟;从STC则由一个全数字的锁相环驱动,它仅用于与展示时间戳(PTS)比较产生显示同步控制信号。同时提出了一个硬件的低通滤波算法,该算法保证了STC在稳态下追踪传输流中的节目时钟参考(PCR)的变化,并且提供稳定的时钟输出,同时有效降低了主控CPU的负荷。仿真实验结果表明,所提出的时钟恢复电路和低通滤波算法具有较好的性能和较低的计算复杂度,并有效地降低了硬件开销。     

照明用大功率无桥LED驱动电路输入电流谐波分析

对作者介绍的照明用大功率无桥LED驱动电路的输入交流工频电流波形在设定电路条件后的频谱和谐波含量进行了分析和计算,其结果是,在电路最低工作频率以下的频率范围内基本不存在谐波成分,电路输入电流的总谐波含量THD随最小输入电流脉冲宽度T₀(min) 增大而上升,随电路的输出直流电压与输入交流电压有效值的比U_o/U_i的增大而下降.并指出在电路的输入端需要一个滤波电路,分析了滤波电路的滤波效果,给出了滤波电路的设计方法.     

一种改善DDS电路系统杂散方法研究

针对直接数字频率合成器(DDS)电路系统输出杂散问题,分析DAC非线性对输出杂散的影响,在此基础上给出DDS电路系统杂散的来源模型。提出通过合理选择输出频段来减小DDS输出杂散的方案,并给出了仿真实例。实测结果验证了该方案可以有效地降低DDS输出杂散,对提高DDS电路输出信号的质量有很好的促进作用,在DDS电路设计方面具有指导意义。     

集成锁相环在激光脉冲调制系统中的应用

锁相环由鉴相器、环路滤波器及压控震荡晶体组成,是一个能跟踪输入信号频率和相位的闭环自动控制系统。研制的激光脉冲调制系统采用锁相技术,以单片、集成锁相环代替分立元件,实现了片内鉴频和鉴相的功能。研制的腔倒空驱动器能够输出 4MHz, 800kHz, 400kHz, 80kHz,40kHz, 8kHz, 4kHz, 800Hz, 400Hz 等不同重复频率的脉冲信号,输出功率达到瓦级,满足了声光布拉格池的要求。该激光脉冲调制系统已经应用在皮秒时间相关单光子计数光谱仪系统中,取得了比较理想的效果。     

Characterization of Frequency Stability: Effect of RF Filtering

This paper shows that the RF filtering of a signal generated by an oscillator affects the characterization of the frequency stability in a manner that differs from the filtering of the phase of this signal. The effect on both the frequency domain and the time domain measurement is considered. It is shown that the spectral density of the phase fluctuations of the filtered signal is a function of the spectral densities of the amplitude fluctuations and of the phase fluctuations of the original signal. The corresponding expression for the two-sample variance (Allan variance) is then also a function of these two contributions. Detailed calculation is made for the case of a signal with frequency stability limited by white phase noise and filtered by a first-order, low-pass filter. It is found that the frequency stability is improved by more filtering if the cutoff frequency, fc, is higher than the signal frequency, f0, as is the case for phase filtering. However, the stability will degrade with more filtering if fc < f0. An optimum frequency stability is reached when fc = f0/?2. Experimental measurements confirm these theoretical predictions.     

A new method for DAC corrections for application in nuclear ADC

The paper describes a new method for measurement and correction of errors associated with DACs. Very small errors of a few μV can be measured and corrected. The method enables us to correct commercially available monolithic DACs, so that they can be used in nuclear ADCs where high integral accuracy and low differential nonlinearity (DNL) are required. This cuts down the circuit size and cost for DACs applied in nuclear ADCs.The paper proposes a “theorem of DAC code correction” which is based on the relationship existing between the errors associated with different bits of a DAC. Complete mathematical proof is given to establish the correctness of the method. The “theorem” can be implemented if the correct value of any bit or of the full scale voltage is known.The method also provides a check on whether errors are correctly measured and whether they are perfectly compensated.The illustration of the relationship between errors associated with different bits also reveals that the conventional ways of adjusting DNL for 16-bit and 18-bit (0.5 LSB) DACs followed by commercial manufacturers are not accurate. These corrections can be implemented more effectively if the procedure described is followed.     

Optical signal processing in dual-wavelength optoelectronic drop analyzer

Dual-wavelength optical signals are injected into the liquid drop through optical fibers in order to study the light intensity variation during the drop growth. Modulation and demodulation are used to reduce the influence of ambient light on the valuable optical signals. HA17555 chip composes the oscillating circuit for light modulation, with different high oscillating frequency for different light source. The light signal collected by a fiber detector after propagation inside the drop is changed into electric signal through the OPA2111 photoelectric circuit. The second-order band-pass filter composed of MAX275 chip is used for signal-separation. The high-pass filter is used to prevent the low frequency signal of ambient light. The valuable signal related to the drop is demodulated by a linear demodulation circuit including a half-wave rectifier, full-wave composition and low-pass filter.     

Mode-locked ring laser with output pulse width of 0.4 ps

The output pulse width of a mode-locked ring laser composed of an erbium-doped fiber amplifier, Mach-Zehnder optical modulator, and optical band-pass filter depends largely on the repetition frequency and the wavelength characteristics of these optical circuit elements. In previous experiments, the output pulse width was in the order of 5 ps at a repetition frequency of 5 GHz. The principal reason was that the narrow passage band of the optical circuit elements made it extremely difficult to generate an ultra-short optical pulse. Consequently, we examined how to narrow the optical pulse width by flattening the wavelength characteristics of these optical circuit elements. Furthermore, we drove the optical modulator in the cavity using a frequency multiplier to operate at an effectively higher frequency By widening the wavelength passage band of all the devices in the optical circuit, we achieved an output pulse width of 0.4 ps at a repetition frequency of 5 GHz; the pulse peak power was more than +23 dBm, and the time-bandwidth product was 0.34. We successfully tested an ultra-short optical pulse source with an output pulse width of 0.4 ps with no external pulse compression using a mode-locked ring laser     

CCD读出电路中数字补偿式一阶模拟滤波器设计

CCD读出电路中低通滤波器在改善系统输出信噪比的同时,不可避免地会产生像素串扰,造成信息畸变.本文针对CCD读出电路中像素串扰造成的信息畸变问题进行理论分析,推导出信息畸变度与一阶低通模拟滤波器截止频率的关系.并针对视频模拟滤波电路中高阶滤波器的实现困难,提出一种数字补偿式一阶低通模拟滤波器的设计方法,该方法根据本文对信息畸变理论的分析,采用一阶低通滤波器,在满足信息畸变度的前提下,极大降低系统截止频率,达到了应用系统的带宽要求,从而可以在应用系统设计中以一阶滤波器替代高阶滤波器.并设计实验进行验证,证明了该方法的正确性与有效性.     

Phase and amplitude disturbances in direct digital frequency synthesizers

The problem of the spurious phase and amplitude disturbances in direct digital frequency synthesizers (DDFS) at the digital-to-analog (DAC) output is discussed. Such a situation is met when a commercial synthesizer lacks the output filter (e.g., the whole set of the so-called Number-controlled oscillators) or is supplied, for some reasons, with a lower clock frequency. Authors of recent books on DDFS mention this phenomenon but lack to provide the explanation. The problem is dealt with in detail in this paper.     

A Comparison of Integration and Low-Pass Filtering

A comparison of the ideal integrator and low-pass filters has been made. Many experimenters use an integrator to filter out high-frequency noise from their data, whereas a properly designed low-pass filter will remove more noise and distort the signal less. Viewed as a low-pass filter, the integrator is superior to the RC filter but inferior to higher order filters. An integrating digital voltmeter (DVM) integrates and samples the input signal. If the signal has a varying component and is mixed with noise, it would be more accurate to use a low-pass filter followed by a sampler, than the integrating DVM.     

Envelope signal selective emphasis in a polar radio frequency transmitter architecture

The linearity of an efficient polar transmitter architecture, with a 1 bit oversampled delta?sigma (DS) modulating the envelope signal, depends, to a high degree, on low-pass envelope filtering. This filter is compulsory to attenuate the DS quantisation noise. A high cut-off frequency results in more noise being included. In contrast, using a filter with a low cut-off frequency results in attenuation of the information content of the envelope signal. Either way, the result is unwanted spectral regrowth. By pre-emphasising the envelope signal, the filter?s attenuation of the information is mitigated. The pre-emphasis is implemented by a digital pseudo-derivative high-pass filter, with inverse magnitude characteristics of the analogue low-pass filter, within a limited interest band. Consequently, the low-pass filter can be designed with a lower cut-off frequency to attenuate more of the DS modulator noise, and the modulator can switch at lower frequencies. With this technique, the WLAN output spectrum, at the critical 30 MHz offset corner frequency, is improved by 12.5 dB, considering a second order DS sampling at 1.28 GHz. The technique was verified with an experimental setup and the behaviour agrees well with simulations.     

First-order PMD compensation using optical FIR filter

We present a synthesis algorithm to design an optical finite impulse response (FIR) filter for compensating a first-order polarization mode dispersion (PMD) by minimizing the differential group delay (DGD). The desired frequency response was approximated using two widely used methods in designing digital FIR filters: the Fourier series expansion method and the frequency sampling method. A numerical simulation was performed for an eighth-order filter to demonstrate the difference between the two methods. The simulation results produced a sharper cutoff for the Fourier series expansion and higher stopband attenuation for the frequency sampling method. The Fourier series method produced better results in reducing the DGD.     

Direct digital synthesizer with jittered clock

Since the direct digital synthesizer (DDS) can potentially be used as a flexible clock source, it is of interest to study its spectrum purity as well as jitter characteristic. In this paper, we investigate the jitter transfer characteristic of the DDS clock driven by a jittered digital-to-analog converter (DAC) clock. We first derive the dosed form expressions of the spectrum of the DAC output signal with jittered driving clock. These expressions are then used to investigate the spectral structure of the DDS clock. Equations are derived for the calculation of the SNR. For a small phase noise power in the driving clock, the DDS clock SNR is obtained in a simple closed form and is shown to be lower than that of the input driving clock by the amount of 20 log(f_s/d_d) dB, where f_s is the nominal driving clock frequency and f_d is the desirable DDS output clock frequency     

开关电流高阶椭圆低通滤波器的设计(英文)

提出了一种新的开关电流高阶椭圆低通滤波器通用综合方法,该法遵循从RLC滤波器到有源RC滤波器,再到开关电容滤波器,最后到开关电流滤波器的顺序进行设计,方法简单易行.文中给出了5阶开关电流椭圆低通滤波器的设计实例,ASIZ仿真频率响应满足所需的频率技术要求.     

A programmable self-adaptive digital frequency multiplier

Existing self-adaptive frequency multipliers work well if the master clock frequency is an integral multiple of the input signal frequency; otherwise they lose an output pulse after a certain interval of time. The frequency of this missing pulse could be as high as half of the input frequency. Since existing self-adaptive frequency multipliers are not programmable, the multiplication factor can not be changed without doing some major changes in the hardware. The reason for missing an output pulse is explained, and design and implementation of a programmable self-adaptive digital frequency multiplier, that does not have this missing pulse problem are presented. The errors associated with the multiplier are discussed     

The new design of AGC circuit for the sinusoidal oscillator with wide oscillation frequency range

The typical automatic gain control (AGC) schemes are not suitable for the sinusoidal oscillator with wide oscillation frequency range. To solve this problem, the up-down counter, multiplying digital-to-analog converter, and high-speed comparators are employed to achieve the proposed AGC circuit, which corrects the complex roots of the overall system automatically to the imaginary axis of the complex frequency plane. The negative feedback technique with digital hardware is applied on the loop gain control. No low-pass filter is needed to detect the oscillation amplitude. Thus, this technique is suitable for the sinusoidal oscillator with wide oscillation frequency range. The oscillation frequencies ranging from 7 Hz to 1 MHz are tested with the proposed AGC circuit. The experimental results demonstrate the static characteristics and dynamic responses of the overall system.