A 285-MHz pipelined MAP decoder in 0.18-/spl mu/m CMOS

Presented in this paper is a pipelined 285-MHz maximum a posteriori probability (MAP) decoder IC. The 8.7-mm/sup 2/ IC is implemented in a 1.8-V 0.18-/spl mu/m CMOS technology and consumes 330 mW at maximum frequency. The MAP decoder chip features a block-interleaved pipelined architecture, which enables the pipelining of the add-compare-select kernels. Measured results indicate that a turbo decoder based on the presented MAP decoder core can achieve: 1) a decoding throughput of 27.6 Mb/s with an energy-efficiency of 2.36 nJ/b/iter; 2) the highest clock frequency compared to existing 0.18-/spl mu/m designs with the smallest area; and 3) comparable throughput with an area reduction of 3-4.3/spl times/ with reference to a look-ahead based high-speed design (Radix-4 design), and a parallel architecture.     

A unified turbo/Viterbi channel decoder for 3GPP mobile wireless in 0.18-/spl mu/m CMOS

A channel decoder chip compliant with the 3GPP mobile wireless standard is described. It supports both data and voice calls simultaneously in a unified turbo/Viterbi decoder architecture. For voice services, the decoder can process over 128 voice channels encoded with rate 1/2 or 1/3, constraint length 9 convolutional codes. For data services, the turbo decoder is capable of processing any mix of rate 1/3, constraint length 4 turbo encoded data streams with an aggregate data rate of up to 2.5 Mb/s with 10 iterations per block (or 4.1 Mb/s with six iterations). The turbo decoder uses the logMAP algorithm with a programmable logsum correction table. It features an interleaver address processor that computes the 3GPP interleaver addresses for all block sizes enabling it to quickly switch context to support different data services for several users. The decoder also contains the 3GPP first channel de-interleaving function and a post-decoder bit error rate estimation unit. The chip is fabricated in a 0.18-/spl mu/m six-layer metal CMOS technology, has an active area of 9 mm/sup 2/, and has a peak clock frequency of 110.8 MHz at 1.8 V (nominal). The power consumption is 306 mW when turbo decoding a 2-Mb/s data stream with ten iterations per block and eight voice calls simultaneously.     

Generalization of the /spl Sigma//sub 0/-rank criteria for space-time codes

Recently, Liu et al., developed the /spl Sigma//sub 0/-rank criteria for space-time codes. It provides a sufficient condition on codeword and generator matrices defined over finite rings /spl Zopf//sub 2k/(j) to ensure full spatial diversity with 2/sup 2k/-QAM modulation. Here, we generalize the /spl Sigma//sub 0/-rank criteria and derive a sufficient condition on the generator matrices defined over finite rings /spl Zopf//sub 2l/(j) to ensure full spatial diversity with 2/sup 2k/-QAM modulation for any positive integer l/spl les/k. We also show that generator matrices defined over GF(2) satisfying the BPSK stacking construction constraint of Mammons and El Gamal achieve full spatial diversity when used with 2/sup 2k/-QAM modulation.     

Cyclic codes over GR(4/sup m/) which are also cyclic over /spl Zopf//sub 4/

Let GR(4/sup m/) be the Galois ring of characteristic 4 and cardinality 4/sup m/, and /spl alpha/_={/spl alpha//sub 0/,/spl alpha//sub 1/,...,/spl alpha//sub m-1/} be a basis of GR(4/sup m/) over /spl Zopf//sub 4/ when we regard GR(4/sup m/) as a free /spl Zopf//sub 4/-module of rank m. Define the map d/sub /spl alpha/_/ from GR(4/sup m/)[z]/(z/sup n/-1) into /spl Zopf//sub 4/[z]/(z/sup mn/-1) by d/spl alpha/_(a(z))=/spl Sigma//sub i=0//sup m-1//spl Sigma//sub j=0//sup n-1/a/sub ij/z/sup mj+i/ where a(z)=/spl Sigma//sub j=0//sup n-1/a/sub j/z/sup j/ and a/sub j/=/spl Sigma//sub i=0//sup m-1/a/sub ij//spl alpha//sub i/, a/sub ij//spl isin//spl Zopf//sub 4/. Then, for any linear code C of length n over GR(4/sup m/), its image d/sub /spl alpha/_/(C) is a /spl Zopf//sub 4/-linear code of length mn. In this article, for n and m being odd integers, it is determined all pairs (/spl alpha/_,C) such that d/sub /spl alpha/_/(C) is /spl Zopf//sub 4/-cyclic, where /spl alpha/_ is a basis of GR(4/sup m/) over /spl Zopf//sub 4/, and C is a cyclic code of length n over GR(4/sup m/).     

1.3-/spl mu/m InAs quantum-dot laser with high dot density and high uniformity

We realized a triple-stacked 1.3-/spl mu/m InAs quantum dot (QD) with a high density of 2.4/spl times/10/sup 11/ cm/sup -2/ and a high uniformity of below 24 meV that employs an As/sub 2/ source and a gradient composition (GC) strain-reducing layer (SRL) grown on a GaAs substrate. We demonstrated the 1.3-/spl mu/m wavelength emission of this triple-stacked QD laser with a 0.92-mm cavity length and a cleaved facet at room temperature. In addition, we realized the highest maximum modal gain yet reported of 8.1 cm/sup -1/ per QD layer at beyond 1.28 /spl mu/m by using our high-density and high-uniformity QD.     

Demonstration of 1789 V, 6.68 m/spl Omega/ /spl middot/ cm/sup 2/ 4H-SiC merged-PiN-Schottky diodes

The design, fabrication and characterisation of a high performance 4H-SiC diode of 1789 V-6.6 A with a low differential specific-on resistance (R/sub SP/spl I.bar/ON/) of 6.68 m/spl Omega/ /spl middot/ cm/sup 2/, based on a 10.3 /spl mu/m 4H-SiC blocking layer doped to 6.6/spl times/10/sup 15/ cm/sup -3/, is reported. The corresponding figure-of-merit of V/sub B//sup 2//R/sub SP/spl I.bar/ON/ for this diode is 479 MW/cm/sup 2/, which substantially surpasses previous records for all other MPS diodes.     

High-performance 1-Gb-NAND flash memory with 0.12-/spl mu/m technology

A 1.8-V, 1-Gb NAND flash memory is fabricated with 0.12-/spl mu/m CMOS STI process technology. For higher integration, a 32-cell NAND structure, which enables row decoder layout in one block pitch, is applied for the first time. Resulting cell and die sizes are 0.076 /spl mu/m/sup 2/ and 129.6 mm/sup 2/, respectively. A pseudo-4-phase charge pump circuit can generate up to 20 V even under the supply voltage of 1.6 V. A newly applied cache program function and expanded page size of (2 k + 64) byte lead to program throughput of 7 MB/s. The page copy-back function is provided for on-chip garbage collection. The read throughput of 27 MB/s is achieved by simply expanding I/O width and page size. A measured disturbance free-window of 3.5 V at 1.5 V-V/sub DD/ is obtained.     

Improved algorithm for division over GF(2/sup m/)

An improved algorithm for division over GF(2/sup m/) is proposed. It is based on a look-ahead procedure that allows division over GF(2/sup m/) to be performed in any number of clock cycles up to 2/sup m/-1. The hardware complexity of the divider depends on the level of look-ahead chosen and hence the speed of operation required. An example using this divider in solving the key equation for single-error correcting Reed-Solomon codes is also considered.<>     

A 10-Gb/s CDR/DEMUX with LC delay line VCO in 0.18-/spl mu/m CMOS

A monolithic 10-Gb/s clock/data recovery and 1:2 demultiplexer are implemented in 0.18-/spl mu/m CMOS. The quadrature LC delay line oscillator has a tuning range of 125 MHz and a 60-MHz/V sensitivity to power supply pulling. The circuit meets SONET OC-192 jitter specifications with a measured jitter of 8 ps p-p when performing error-free recovery of PRBS 2/sup 31/-1 data. Clock and data recovery (CDR) is achieved at 10 Gb/s, demonstrating the feasibility of a half-rate early/late PD (with tri-state) based CDR on 0.18-/spl mu/m CMOS. The 1.9/spl times/1.5 mm/sup 2/ IC (not including output buffers) consumes 285 mW from a 1.8-V supply.     

A high-speed 850-nm optical receiver front-end in 0.18-/spl mu/m CMOS

A high-speed optical interface circuit for 850-nm optical communication is presented. Photodetector, transimpedance amplifier (TIA), and post-amplifier are integrated in a standard 0.18-/spl mu/m 1.8-V CMOS technology. To eliminate the slow substrate carriers, a differential n-well diode topology is used. Device simulations clarify the speed advantage of the proposed diode topology compared to other topologies, but also demonstrate the speed-responsivity tradeoff. Due to the lower responsivity, a very sensitive transimpedance amplifier is needed. At 500 Mb/s, an input power of -8 dBm is sufficient to have a bit error rate of 3/spl middot/10/sup -10/. Next, the design of a broadband post-amplifier is discussed. The small-signal frequency dependent gain of the traditional and modified Cherry-Hooper stage is analyzed. To achieve broadband operation in the output buffer, so-called "f/sub T/ doublers" are used. For a differential 10 mV/sub pp/ 2/sup 31/-1 pseudo random bit sequence, a bit error rate of 5/spl middot/10/sup -12/ at 3.5 Gb/s has been measured. At lower bit-rates, the bit error rate is even lower: a 1-Gb/s 10-mV/sub pp/ input signal results in a bit error rate of 7/spl middot/10/sup -14/. The TIA consumes 17mW, while the post-amplifier circuit consumes 34 mW.     

A 1-/spl mu/m Bipolar VLSI Technology

A 1-/spl mu/m VLSI process technology has been developed for the fabrication of bipolar circuits. The process employs electron-beam slicing writing, plasma processing, ion implantation, and low-temperature oxidation/annealing to fabricate bipolar device structures with a minimum feature size of 0.9 /spl mu/m. Both nonisolated I/sup 2/L and isolated Schottky transistor logic (STL) devices and circuits have been fabricated with this process technology. The primary demonstration vehicle is a seated LSI, I/sup 2/L, 4-bit processor chip (SBP0400) with a minimum feature size of 1 /spl mu/m. Scaled SPB0400's have been fabricated that operate at clock speeds 3X higher than their full-size counterparts at 50-mA chip current. Average propagation delay has been measured as a function of minimum feature size for both I/sup 2/L and STL device designs. Power-delay products of 14 fJ for I/sup 2/L and 30 fJ for STL have been measured.     

A fully integrated 0.13-/spl mu/m CMOS mixed-signal SoC for DVD player applications

This paper describes a fully integrated single-chip CMOS mixed-signal system on a chip (SoC) for DVD player applications. It integrates one digital signal processor (DSP), two 32-bit CPUs, three dedicated processing units, a partial response maximum likelihood (PRML) read channel with an analog front end (AFE), and many other subsystems on the same die. The AFE includes a fifth-order G/sub m/-C filter and attains over 66 dB C/N overall. PR(3,4,4,3) structure is employed in the PRML read channel. Owing to the PRML signal processing and the mixed-signal system level optimization in the PRML read channel, less than 10/sup -6/ of bit-error rate (BER) is obtained for the focus offset margins over /spl plusmn/0.5 /spl mu/m. This SoC is fabricated in 0.13-/spl mu/m one-poly six-Cu CMOS technology. It contains 24 million transistors in a 63.87 mm/sup 2/ die and consumes 1.5 W at 40 MSample/s data rate, which corresponds to DVD 1.5 times playback operation mode.     

Fabrication and analysis of high-contrast InGaAsP-InP Mach-Zehnder modulators for use at 1.55-/spl mu/m wavelength

A high-contrast ratio, low voltage-length product, multiple quantum well InGaAsP-InP Mach-Zehnder interferometer is demonstrated and analyzed. An on/off ratio of over 40 dB and voltage-length product of 1.8 V-mm were measured, results which are superior to previous reports of similar MQW structures. Using the Lanczos-Helmholtz beam propagation method, we find that the linear and quadratic electrooptic coefficients for InGaAsP quantum wells are r=(3.9/spl plusmn/1.7) pm/V and s=(5.0/spl plusmn/1.5)/spl times/10/sup -19/ m/sup 2//V/sup 2/, respectively. We also demonstrate active optical alignment of the modulator guides using integrated waveguide light emitting diodes.     

10-kV, 123-m/spl Omega//spl middot/cm/sup 2/ 4H-SiC power DMOSFETs

10-kV, 123-m/spl Omega//spl middot/cm/sup 2/ power DMOSFETs in 4H-SiC are demonstrated. A 42% reduction in R/sub on,sp/, compared to a previously reported value, was achieved by using an 8 /spl times/ 10/sup 14/ cm/sup -3/ doped, 85-/spl mu/m-thick drift epilayer. An effective channel mobility of 22 cm/sup 2//Vs was measured from a test MOSFET. A specific on-resistance of 123 m/spl Omega//spl middot/cm/sup 2/ were measured with a gate bias of 18 V, which corresponds to an E/sub ox/ of 3 MV/cm. A leakage current of 197 /spl mu/A was measured at a drain bias of 10 kV from a 4H-SiC DMOSFET with an active area of 4.24 /spl times/ 10/sup -3/ cm/sup 2/. A switching time of 100 ns was measured in 4.6-kV, 1.3-A switching measurements. This shows that the 4H-SiC power DMOSFETS are ideal for high-voltage, high-speed switching applications.     

1.5-/spl mu/m InGaAsP-InP slab-coupled optical waveguide lasers

We report the demonstration of high-power semiconductor slab-coupled optical waveguide lasers (SCOWLs) operating at a wavelength of 1.5 /spl mu/m. The lasers operate with large (4/spl times/8 /spl mu/m diameter) fundamental mode and produce output power in excess of 800 mW. These structures have very low loss (/spl sim/0.5 cm/sup -1/) enabling centimeter-long devices for efficient heat removal. The large fundamental mode allows 55% butt-coupling efficiency to standard optical fiber (SMF-28). Comparisons are made between SCOWL structures having nominal 4- and 5-/spl mu/m-thick waveguides.     

1.27 /spl mu/m metamorphic InGaAs quantum well lasers on GaAs substrates

Pulsed operation at a wavelength of 1.27 /spl mu/m from metamorphic ridge-waveguide (RWG) InGaAs quantum well lasers on GaAs substrates using an alloy graded buffer, grown by molecular beam epitaxy, is demonstrated. Laser performance is anisotropic along the two orthogonal <1/spl plusmn/10> directions with lower threshold currents along the <1-10> direction. Post-growth rapid thermal annealing further reduces threshold currents. For 4 /spl mu/m-wide RWG lasers, minimum threshold current densities are 1-2.5 kA/cm/sup 2/ for cavity lengths 0.6-1.5 mm.     

Galois field arithmetic over GF(p/sup m/) for high-speed/low-power error-control applications

This paper presents a very large-scale integration implementation of Galois field arithmetic for high-speed error-control coding applications that is based on the field GF(p/sup m/) with m a small integer such as 2 or 3 and p a prime of sufficient value to generate the required field size. In this case, the Galois field arithmetic operations of addition, multiplication, and inversion are based on architectures using blocks that perform integer arithmetic modulo p. These integer arithmetic operations modulo p have previously been implemented with low delay power products through the use of one hot coding and barrel shifters circuits based on transistor arrays. In this paper, the same one hot coding and barrel shifters circuits are used to construct circuits that implement addition, multiplication, and inversion over GF(p/sup m/). The circuits for GF(p/sup m/) addition and multiplication with p/spl ne/2, achieve a lower power-delay product than designs based on GF(2/sup m/). Also, the architecture for GF(p/sup m/) inversion can be efficiently implemented when m=2 or m=3.     

Characterization of the temperature sensitivity of gain and recombination mechanisms in 1.3-/spl mu/m AlGaInAs MQW lasers

The potential of 1.3-/spl mu/m AlGaInAs multiple quantum-well (MQW) laser diodes for uncooled operation in high-speed optical communication systems is experimentally evaluated by characterizing the temperature dependence of key parameters such as the threshold current, transparency current density, optical gain and carrier lifetime. Detailed measurements performed in the 20/spl deg/C-100/spl deg/C temperature range indicate a localized T/sub 0/ value of 68 K at 98/spl deg/C for a device with a 2.8 /spl mu/m ridge width and 700-/spl mu/m cavity length. The transparency current density is measured for temperatures from 20/spl deg/C to 60/spl deg/C and found to increase at a rate of 7.7 A/spl middot/cm/sup -2//spl middot/ /spl deg/C/sup -1/. Optical gain characterizations show that the peak modal gain at threshold is independent of temperature, whereas the differential gain decreases linearly with temperature at a rate of 3/spl times/10/sup -4/ A/sup -1//spl middot//spl deg/C/sup -1/. The differential carrier lifetime is determined from electrical impedance measurements and found to decrease with temperature. From the measured carrier lifetime we derive the monomolecular ( A), radiative (B), and nonradiative Auger (C) recombination coefficients and determine their temperature dependence in the 20/spl deg/C-80/spl deg/C range. Our study shows that A is temperature independent, B decreases with temperature, and C exhibits a less pronounced increase with temperature. The experimental observations are discussed and compared with theoretical predictions and measurements performed on other material systems.     

1.58-/spl mu/m broad-band erbium-doped tellurite fiber amplifier

This paper describes the development of a 1.58-/spl mu/m broad-band and gain-flattened erbium-doped tellurite fiber amplifier (EDTFA). First, we compare the spectroscopic properties of various glasses including the stimulated emission cross sections of the Er/sup 3+4/ I/sub 13/2/ /sup 4/I/sub 15/2/ transition and the signal excited-state absorption (ESA) cross sections of the Er/sup 3+4/ I/sub 13/2/ - /sup 4/I/sub 9/2/ transition. We detail the amplification characteristics of a 1.58-/spl mu/m-band EDTFA designed for wavelength-division-multiplexing applications by comparing it with a 1.58-/spl mu/m-band erbium-doped silica fiber amplifier. Furthermore, we describe the 1.58-/spl mu/m-band gain-flattened EDTFA we developed using a fiber-Bragg-grating-type gain equalizer. We achieved a gain of 25.3 dB and a noise figure of less than 6 dB with a slight gain excursion of 0.6 dB over a wide wavelength range of 1561-1611 nm. The total output power of the EDTFA module was 20.4 dBm and its power conversion efficiency reached 32.8%.     

High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices

This paper demonstrates gate-all-around (GAA) n- and p-FETs on a silicon-on-insulator with /spl les/ 5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift mask lithography and self-limiting oxidation techniques were utilized to form 140- to 1000-nm-long nanowires, followed by FET fabrication. The devices exhibit excellent electrostatic control, e.g., near ideal subthreshold slope (/spl sim/ 63 mV/dec), low drain-induced barrier lowering (/spl sim/ 10 mV/V), and with I/sub ON//I/sub OFF/ ratio of /spl sim/10/sup 6/. High drive currents of /spl sim/ 1.5 and /spl sim/1.0 mA//spl mu/m were achieved for 180-nm-long nand p-FETs, respectively. It is verified that the threshold voltage of GAA FETs is independent of substrate bias due to the complete electrostatic shielding of the channel body.