A new extension method of retention time for memory cell on dynamic random access memory

Demands have been placed on dynamic random access memory (DRAM) to not only increase memory capacity and data transfer speed but also to reduce operating and standby currents. When a system uses DRAM, the restricted data retention time necessitates a refresh operation because each bit of the DRAM is stored as an amount of electrical charge in a storage capacitor. Power consumption for the refresh operation increases in proportion to memory capacity. A new method is proposed to reduce the refresh power consumption dynamically, when full memory capacity is not required, by effectively extending the memory cell retention time. Conversion from 1 cell/bit to 2^N cells/bit reduces the variation of retention times among memory cells. The proposed method reduces the frequency of disturbance and power consumption by two orders of magnitude. Furthermore, the conversion itself can be realized very simply from the structure of the DRAM array circuit, while maintaining all conventional functions and operations in the full array access mode.     

基于GMR及TMR效应的磁随机存储器的最新应用开发

介绍了巨磁电阻（GMR）及隧道磁电阻（TMR）效应,讨论了计算机磁随机存储器（MRAM）的最新应用开发。     

一种基于碳纳米管的随机存储器

随着传统存储器集成度的不断提高,每个存储单元的电子数目不断减少,并逐渐接近其极限。为了解决传统存储器件发展遇到的困难,利用碳纳米管之间范德瓦耳斯力,设计了一种基于碳纳米管的可读写的随机存储器,研究了系统的双稳性,讨论了存储器的优点和可行性,并认为系统具有良好存储效应所应满足的条件。     

Transparent random access memory testing for pattern sensitive faults

This paper presents a new methodology for RAM testing based on the PS(n, k) fault model (the k out of n pattern sensitive fault model). According to this model the contents of any memory cell which belongs to an n-bit memory block, or the ability to change the contents, is influenced by the contents of any k -1 cells from this block. The proposed methodology is a transparent BIST technique, which can be efficiently combined with on-line error detection. This approach preserves the initial contents of the memory after the test and provides for a high fault coverage for traditional fault and error models, as well as for pattern sensitive faults. This paper includes the investigation of testing approaches based on transparent pseudoexhaustive testing and its approximations by deterministic and pseudorandom circular tests. The proposed methodology can be used for periodic and manufacturing testing and require lower hardware and time overheads than the standard approaches.This work was supported by the NSF under Grant MIP9208487 and NATO under Grant 910411.     

Preparation of (Pb0.88La0.12)TiO3 thin films for dynamic random access memory by low pressure-metalorganic chemical vapor deposition

La-modified lead titanate (PLT) thin films were prepared by hot-wall type low pressure-metalorganic chemical vapor deposition method. Pb(dpm)₂, La(dpm)₃, and titanium tetraisopropoxide were used as source materials. The films were deposited at 500°C under the low pressure of 1000 mTorr and then annealed at 650°C for 10 min in oxygen ambient. Sputter-deposited platinum electrodes and 180 nm thick PLT thin films were employed to form MIM capacitors with the best combination of high charge storage density (26.7 μC/cm² at 3V) and low leakage current density (1.5 × 10^-7 A/cm² at 3V). The measured dielectric constant and dielectric loss were 1000∼1200 and 0.06∼0.07 at zero bias and 100 kHz, respectively.     

Multiuser detectors for large CDMA random access systems over Rayleigh fading channels

In this paper, large code division multiple access (CDMA) random access systems employing the decorrelator and minimum mean square error (MMSE) detectors are investigated over Rayleigh fading channels under the assumption that both the number of users and the spreading gain tend to infinity, but their ratio converges to a constant. The signal to interference ratio (SIR) is shown to converge almost surely to a constant and the bit‐error rate (BER) is expressed as a function of the traffic load, transmission probability, channel coefficient, and distribution of transmission power. Furthermore, the throughput, the spectrum efficiency, and the stability region are analyzed and simulated. For dominating systems, it is shown that the MMSE detector achieves much higher throughput and spectral efficiency than decorrelator detector. Besides, it is also disclosed that, when the signal to noise ratio (SNR) is larger than an optimum value, the spectrum efficiency increases as the ratio of bit energy to noise power spectrum density (E_b/N₀) increases; however, when SNR is smaller than the optimum value, the spectrum efficiency decreases as E_b/N₀ increases. For ordinary stable systems, it is demonstrated that their stability region gets narrower as the traffic load increases. Copyright © 2010 John Wiley & Sons, Ltd.     

一种固定位置MTC设备的随机接入改进算法

针对海量机器类通信(Massive Machine Type Communications, mMTC)场景下传统随机接入存在大量前导碰撞问题,提出了一种对终端侧和基站侧的接入改进算法,利用前导标记序列和固定位置随机接入终端的定时提前(Timing Advance, TA)信息,使得基站能合理地确定应该向哪些终端回复随机接入响应消息,避免碰撞终端占用资源发送消息3(Message 3,Msg3),实现前导高效利用。仿真表明,该算法在均匀分布和Beta分布接入模型下均能有效降低前导碰撞概率,提高终端的接入成功率,并且拥有合理的平均接入时延。     

Flexible and transparent ReRAM with GZO memory layer and GZO-electrodes on large PEN sheet

Fabrication of flexible transparent resistive random access memory (FT-ReRAM) which consists of Ga doped ZnO (GZO) film not only as a memory layer but also as electrodes on the large Poly Ethylene Naphthalate sheet was attained by introducing RF plasma assist DC magnetron sputtering method. The averaged transmittance in the visible region (400-800 nm) was 66%. The memory effect was studied by using conducting atomic force microscope. It was suggested that the increase of Joule heating and oxygen vacancy density enhances memory effect, which is consistent with the redox model which has been proposed as the switching mechanism for conventional ReRAM. Stable and repeatable bi-polar resistive switching by application of the low voltage less than 2 V and low current less than 100 μA was confirmed in the FT-GZO-ReRAM. Reset switching, which is a switching from the low to the high resistance states, in GZO-ReRAM was confirmed to be smooth and continuous, which will enable a multilevel application. It was suggested that the smooth and continuous reset was brought about by Ga-doping.     

机器类设备基于不同时延需求分组的随机接入方法

针对大规模机器类通信中拥塞导致的时延敏感设备时延高和接入成功率低的问题，提出将小区中设备按时延要求分组，对不同组设备引入不同的退避模型，分析时延敏感设备的时延和吞吐量，按照不同组中设备的时延需求动态分配前导数目，同时通过调整接入类限制因子实现吞吐量的优化。仿真结果表明，在给定时延敏感设备的时延限制条件时，与统一退避的机制对比，所提分组机制的时延敏感设备能够满足时延要求，并且提高了接入效率。     

Ar/CO/NH3等离子体刻蚀多种磁性金属叠层

基于磁性合金的等离子体刻蚀工艺,在中国科学院微电子研究所自主研发的刻蚀设备中,使用Ar,CO和NH3的混合气体对用于形成磁随机存储器(MRAM)的多种磁性金属叠层进行刻蚀.采用两步刻蚀的方法刻蚀了多层磁性金属叠层,每一步的刻蚀气体组分不同,研究了Ar气在混合气体中的体积分数对材料刻蚀速率和侧壁形貌的影响.结果表明,刻蚀速率随着Ar气体积分数的增加而增加,而侧壁倾角则随着Ar气体积分数的增加而减小.两步刻蚀的方法可以根据材料的结构特点来控制Ar离子轰击的作用,可以得到大于21.4 nm/min的刻蚀速率和约90°的侧壁倾角.     

Performance analysis of STT-RAM with cross shaped free layer using Heusler alloys

We have investigated the performance of a spin transfer torque random access memory (STT-RAM) cell with a cross shaped Heusler compound based free layer using micromagnetic simulations. We have designed a free layer using a Cobalt based Heusler compound. Simulation results clearly show that the switching time from one state to the other state has been reduced, also it has been found that the critical switching current density (to switch the magnetization of the free layer of the STT RAM cell) is reduced.     

A mechanism for asymmetric data writing failure

As dynamic random access memory (DRAM) technology develops further, it is more difficult to sustain a sufficient sensing margin to detect weak cell data. Therefore, a high data writing performance is necessary in order to guarantee the data sensing margin. In this paper, an analysis of the phenomenon of an asymmetric data writing failure (ADWF) is presented, taking account of a bit line sense amplifier (BLSA) offset, and the failure mechanism has been studied through the use of measurement analysis.     

Analysis of read speed latency in 6T-SRAM cell using multi-layered graphene nanoribbon and cu based nano-interconnects for high performance memory circuit design

In this study, we designed a 6T-SRAM cell using 16-nm CMOS process and analyzed the performance in terms of read-speed latency. The temperature-dependent Cu and multilayered graphene nanoribbon (MLGNR)-based nano-interconnect materials is used throughout the circuit (primarily bit/bit-bars [red lines] and word lines [write lines]). Here, the read speed analysis is performed with four different chip operating temperatures (150K, 250K, 350K, and 450K) using both Cu and graphene nanoribbon (GNR) nano-interconnects with different interconnect lengths (from 10 μm to 100 μm), for reading-0 and reading-1 operations. To execute the reading operation, the CMOS technology, that is, the16-nm PTM-HPC model, and the16-nm interconnect technology, that is, ITRS-13, are used in this application. The complete design is simulated using TSPICE simulation tools (by Mentor Graphics). The read speed latency increases rapidly as interconnect length increases for both Cu and GNR interconnects. However, the Cu interconnect has three to six times more latency than the GNR. In addition, we observe that the reading speed latency for the GNR interconnect is ~10.29 ns for wide temperature variations (150K to 450K), whereas the reading speed latency for the Cu interconnect varies between ~32 ns and 65 ns for the same temperature ranges. The above analysis is useful for the design of next generation, high-speed memories using different nano-interconnect materials.     

光通信系统中一种新颖的随机交织型级联码方案

基于LDPC码,提出一种新颖的随机交织型级联码(RICC,random interleaved concatenatedcode)方案。在编码阶段,根据LDPC码中不同度数的变量节点采用不同纠错能力的BCH外码,分别进行保护的思想进行集分割编码;在译码阶段,采用硬判决辅助软判决的联合迭代译码。不同于传统的单极型和交织型级联方式,它是一种根据LDPC码变量节点(VN)度数来决定交织深度,因而交织方式是随机的。仿真结果分析表明,在误比特率(BER)为10-8时,四集合分割的RICC-4P的净编码增益(NCG)比无分割的单级型级联码提高了0.15dB,比ITU-T G.709和G.975.1标准中的RS(255,239)、RS(255,239)+CSOC(n/k=7/6,J=8)级联码和开销为25%的正交级联BCH码的NCG分别提高了3.0、1.5和0.4dB,其纠错性能的提升得益于采用集分割保护和硬判决辅助软判决的联合迭代译码。     

栅介质氧化层缺失缺陷的形成原因及解决方案

氮氧化技术是45 nm及以下技术节点栅介质制备的关键工艺,严格控制由氮氧化工艺所诱发的界面缺陷是提高栅介质质量的重点.研究了形成栅介质氧化层缺失缺陷的原因,并提出了解决方案.结果表明,原位水蒸气生成(ISSG)热氧化形成栅介质氧化层后的实时高温纯惰性氮化热处理工艺是形成栅介质氧化层缺失缺陷的主要原因;在实时高温纯惰性氮化热处理工艺中引入适量的O2,可以消除栅介质氧化层的缺失缺陷.数据表明,引入适量O2后,栅介质氧化层的界面陷阱密度(Dit)和界面总电荷密度(ΔQtot)分别减少了12.5％和26.1％;pMOS器件负偏压不稳定性(NBTI)测试中0.1％样品失效时间(t0.1％)和50％样品失效时间(t50％)分别提高了18％和39％;32 MB静态随机存储器(SRAM)在正常工作电压和最小工作电压分别提高了9％和13％左右.