CMOS planar spiral inductor modeling and low noise amplifier design

During this study, various narrowband single-ended inductive source degenerated Low Noise Amplifiers (LNAs) for GSM and S-band low earth orbit (LEO) space applications have been designed, simulated and compared using Mietec CMOS 0.7 μm process and the Cadence/BSIM3v3. To get more realistic results, parasitic effects due to layout have been calculated and added to the simulations. Also, considering the inductive source degenerative topology, most of the attention is given on the modeling of planar spiral inductor by lumped element circuits. Moreover to decrease the substrate effects, the inductors have been surrounded by grounded guard rings and have patterned ground shield (PGS) under them. The simulation results of LNA including the parasitic effects indicate a forward gain of 9 dB with noise figure of 4.5 dB while drawing 18 mW from+3 V supply at 2210 MHz. The area occupied is 1.8 mm×1.6 mm with pads, 1.3 mm×1.2 mm without pads.     

A CMOS low noise amplifier with integrated front-side micromachined inductor

The paper presents the design and characterization of a low noise amplifier (LNA) in a 0.18 μm CMOS process with a novel micromachined integrated stacked inductor. The inductor is released from the silicon substrate by a low-cost CMOS compatible dry front-side micromachining process that enables higher inductor quality factor and self-resonance frequency. The post-processed micromachined inductor is used in the matching network of a single stage cascode 4 GHz LNA to improve its RF performance. This study compares performance of the fabricated LNA prior to and after post-processing of the inductor. The measurement results show a 0.5 dB improvement in the minimum noise figure and a 1 dB increase in gain, while good input matching is maintained. These results show that the novel low-cost CMOS compatible front-side dry micromachining process reported here significantly improves performance and is very promising for System-On-Chip (SOC) applications.     

Low-loss active inductor with independently adjustable self-resonance frequency and quality factor parameters

This work presents a new low-loss active inductor whose self-resonance frequency and quality factor parameters can be adjusted independently from each other. In order to achieve this property, a new input topology has been employed which consists of cascode structure with a diode connected transistor. Furthermore, the proposed input topology makes the device robust in terms of its performance over variation in process, voltage and temperature. Additionally, RC feedback is used to cancel series-loss resistance of the active inductor, which allows self-resonant enhancement as well. Schematic and post-layout simulation results show the theoretical validity of the design. To validate the design feasibility for process, voltage and temperature changes, Monte Carlo and temperature analysis are done. Suggested structure shows inductor behavior in the frequency range of 0.3–11.3 GHz. Maximum quality factor is obtained as high as 2.1k at 5.9 GHz. Total power consumption is as low as 1 mW with 1.8 V power supply.     

A low-noise widely tunable Gm-C filter with frequency calibration

A fourth-order Gm-C Chebyshev low-pass filter is presented as channel selection filter for reconfigurable multi-mode wireless receivers. Low-noise technologies are proposed in optimizing the noise characteristics of both the Gm cells and the filter topology. A frequency tuning strategy is used by tuning both the transconductance of the Gm cells and the capacitance of the capacitor banks. To achieve accurate cut-off frequencies, an on-chip calibration circuit is presented to compensate for the frequency inaccuracy introduced by process variation. The filter is fabricated in a 0.13 μm CMOS process. It exhibits a wide programmable bandwidth from 322.5 kHz to 20 MHz. Measured results show that the filter has low input referred noise of 5.9 nV/√Hz and high out-of-band ⅡP3 of 16.2 dBm. It consumes 4.2 and 9.5 mW from a 1 V power supply at its lowest and highest cut-off frequencies respectively.     

相控阵雷达中频信号模拟器设计与实现

中频信号模拟器是相控阵雷达不可缺少的一个分系统,其设计和实现上有着独特的特点.采用模拟控制处理器实时接收雷达主控机的控制字的方法,按雷达天线波束指向,判断当前目标是否在波束内.若在波束内,则按目标距离和工作模板产生相应距离和波形的模拟回波.模拟器用于雷达系统的自动化监测、雷达各分系统对接试验和模拟试验、操作人员的培训、雷达系统的功能测试和检查以及模拟动态飞行目标.     

A UWB CMOS low-noise amplifier with noise reduction and linearity improvement techniques

In this paper, a highly linear CMOS low noise amplifier (LNA) for ultra-wideband applications is presented. The proposed LNA improves both input second- and third-order intercept points (IIP2 and IIP3) by canceling the common-mode part of all intermodulation components from the output current. The proposed LNA structure creates equal common-mode currents with the opposite sign by cascading two differential pairs with a cross-connected output. These currents eliminate each other at the output and improve the linearity. Also, the proposed LNA improves the noise performance by canceling the thermal noise of the input and auxiliary transistors at the output. Detailed analysis is provided to show the effectiveness of the proposed LNA structure. Post-layout circuit level simulation results using a 90 nm RF CMOS process with Spectre-RF reveal 9.5 dB power gain, -3 dB bandwidth (BW_−3dB) of 8 GHz from 2.4 GHz to 10.4 GHz, and mean IIP3 and IIP2 of +13.1 dBm and +42.8 dBm, respectively. The simulated S₁₁ is less than −11 dB in whole frequency range while the LNA consumes 14.8 mW from a single 1.2 V power supply.     

Voltage difference transresistance amplifier and its application: floating FDNR simulator circuit

In this article, a new active building component with electronically tunable transresistive block, voltage difference transresistance amplifier, and its floating frequency dependent negative resistor simulator circuit application is presented. The simulator circuit is shown to operate using single active building block with two grounded passive components, to be electronically tunable over its value which is controlled by an independent current source, not to require any conditions of component matching and to have good sensitivity performance with respect to tracking errors. To examine functionality of the design, a CRD band-pass filter example is given.

Numerous simulation program with integrated circuit emphasis (SPICE) simulations are performed and depicted through the article to verify validity of the study. Taiwan semiconductor manufacturing company (TSMC) 0.18 µm complementary metal oxide semiconductor technology parameters are used through simulations.     

A high-efficiency low-voltage class-E PA for IoT applications in sub-1 GHz frequency range

We present and propose a complete and iterative integrated-circuit and electro-magnetic (EM) co-design methodology and procedure for a low-voltage sub-1 GHz class-E PA. The presented class-E PA consists of the on-chip power transistor, the on-chip gate driving circuits, the off-chip tunable LC load network and the off-chip LC ladder low pass filter. The design methodology includes an explicit design equation based circuit components values'' analysis and numerical derivation, output power targeted transistor size and low pass filter design, and power efficiency oriented design optimization. The proposed design procedure includes the power efficiency oriented LC network tuning, the detailed circuit/EM co-simulation plan on integrated circuit level, package level and PCB level to ensure an accurate simulation to measurement match and first pass design success. The proposed PA is targeted to achieve more than 15 dBm output power delivery and 40% power efficiency at 433 MHz frequency band with 1.5 V low voltage supply. The LC load network is designed to be off-chip for the purpose of easy tuning and optimization. The same circuit can be extended to all sub-1 GHz applications with the same tuning and optimization on the load network at different frequencies. The amplifier is implemented in 0.13 μm CMOS technology with a core area occupation of 400 μm by 300 μm. Measurement results showed that it provided power delivery of 16.42 dBm at antenna with efficiency of 40.6%. A harmonics suppression of 44 dBc is achieved, making it suitable for massive deployment of IoT devices.     

A dual band-pass amplifier-filter circuit for simultaneous recording of spikes and local field potentials from live neuronal tissue using multielectrode arrays

The paper presents the design and test results of a novel circuit with dual band-pass filter for simultaneous recording of Local Filed Potentials and spikes from individual neurons. Single readout channel is built of an input AC-coupling circuit with the cut-off frequency below 0.1 Hz, a low noise preamplifier and two parallel band-pass filters with nominal bandwidths from 2 Hz to 100 Hz and from 200 Hz to 2 kHz. The design is optimized for low noise, high dynamic range, and low power dissipation. The circuit has been designed and manufactured in a 0.35 μm CMOS process as a multichannel chip comprising also an analog multiplexer for serialization of the analog output signals.     

A unified analytical and scalable lumped model of RF CMOS spiral inductors based on electromagnetic effects and circuit analysis

An enhanced scalable compact model for on-chip RF CMOS spiral inductors is presented. By considering layout and technology parameters, under quasi-static approximation, the model elements are all expressed analytically and based on electromagnetic effects. Frequency dependent behavior of CMOS spiral such as skin and proximity effects, and decrease of equivalent series resistance due to substrate coupling is considered. The model is suitable to be easily implemented in design kits by foundry and provides interesting accuracy to be used by CMOS Radio Frequency Integrated Circuits designers.     

Analysis and optimization of the impact of channel resistance on CMOS LNA noise performance

The intrinsic channel resistance, which is caused by the finite charging time of the carriers in the inversion layer, has remarkable impact on RF CMOS circuits, especially low noise amplifier (LNA), the first block of receiver. The impact of channel resistance on the noise performance of LNA is thoroughly studied and analyzed in this paper, and then new formulae are proposed systematically. Moreover, revised noise figure optimization technique is presented. All of this work will be very instructive for the design of high performance LNA.     

一种低功耗高增益复合共源共栅放大器

基于TSMC 0.25 μm工艺,设计了一种复合共源共栅两级CMOS运算放大器.与传统CMOS运算放大器相比,该运放利用MOS管工作在弱反型区时跨导较大、工作电流较小的特点,有效提高了运放的增益,同时降低了功耗,提高了输出电压摆幅.运放结构简单,降低了补偿难度,3.5 pF的补偿电容就可以支持运放稳定工作.仿真与实验数据表明,设计的运算放大器直流增益可达110 dB以上,功耗为110 μW.     

Two stage class AB-AB amplifier using FGMOS for low voltage operation and SSF for frequency compensation

The paper presented here offers a two stage amplifier where both stages are in class AB mode. The input stage makes use of a floating gate metal oxide semiconductor (FGMOS) transistor which enables this circuit to operate at lower voltage and also increases overall linearity. The frequency compensation is done using voltage buffer scheme. A super source follower (SSF) acts as voltage buffer and exploited here with a series capacitor. The function of SSF is to enhance phase margin (PM) and gain bandwidth product (GBW) of the amplifier. The small signal equivalent and mathematical analysis of circuit is also given. The performance of the proposed circuit has been verified by using Mentor Graphics Eldo simulation tool with TSMC CMOS 0.18 μm process parameters. The ac simulation results of amplifier show that GBW is 9 MHz and power consumption is 0.5 mW.     

A 5-GHz low-voltage and low-power CMOS LC voltage controlled oscillator for 802.11a wireless LAN applications

In this paper, a low phase noise and low power 5.15?GHz LC-tank VCO is presented and analysed. The phase noise achieved is??91,??116 and??126?dBc/Hz at 100?KHz, 1?MHz and 3?MHz offsets respectively from the carrier frequency of 5.15?GHz, with 1.8?V power supply voltage and giving a very low power consumption of about 2.5?mW by considering the proposed oscillator topology, which consumes less power than the classical oscillator using the traditional differential transconductor pair. A broad tuning range has been achieved by means of standard mode PMOS varactors. The tunability of the designed VCO covers 530?MHz, from 4.78?GHz up to 5.31?GHz. Predicted performance has been verified by analyses and simulations using ELDO-RF tool with 0.35?µm CMOS TSMC parameters.     

A controllable resistor and its applications in pole-zero tracking frequency compensation methods for LDOs

This paper presents a controllable resistor, which is formed by a MOS-resistor working in the deep triangle region and an auxiliary circuit. The auxiliary circuit can generate the gate-source voltage which is proportional to the output current of an low dropout regulator for the MOS-resistor. Thus, the equivalent output resistance of the MOS-resistor is inversely proportional to the output current, which is a suitable feature for pole-zero tracking frequency compensation methods. By switching the type of the MOS-resistor and current direction through the auxiliary circuit, the controllable resistor can be suitable for different applications. Three pole-zero tracking frequency compensation methods based on a single Miller capacitor with hulling resistor, unit-gain compensation cell and pseudo-ESR （equivalent serial resistor of load capacitor） power stage have been realized by this controllable resistor. Their advantages and limitations are discussed and verified by simulation results.     

A controllable resistor and its applications in pole-zero tracking frequency compensation methods for LDOs

unit-gain compensation ceil and pseudo-ESR (equivalent serial resistor of load capacitor) power stage have been realized by this controllable resistor.Their advantages and limitations are discussed and verified by simulation results.     

A 2.4 GHz high output power and high efficiency power amplifier operating at inductive breakdown in CMOS technology

In this paper, a novel CMOS power amplifier (PA) with high output power and power added efficiency is designed to operate in the avalanche region by increasing the supply voltage for the first time. With the X-parameter measurement based poly-harmonic distortion (PHD) behavioral model including the X^S and X^T terms, the simulation results can reveal accurate large signal characteristics of the whole PA at breakdown. The output power at 1-dB compression point of 30.2 dBm with 34.1% PAE at 2.4 GHz is obtained.     

A simple real‐time frequency scaling technique for rain attenuation and its performance

A new algorithm has been proposed for frequency scaling of rain attenuation. It uses the real‐time estimates of a spatial variation index in the rain rate profile suggested in simple atmospheric model (SAM) to obtain the scaled attenuation. Measured data are used to validate the algorithm which showed a typical accuracy of better than 2.5 dB for 95% confidence. The time profile of a model parameter derived from measured values has also been effectively utilized to envisage the rain cell movement, particularly for high elevation conditions. Simulated data with predefined rain rate profiles were also used for validations. The relative contributions of the model error and the measurement noise to the final error were obtained. The errors are attributed to the modelling mismatch and intermediate parameter estimation error. The estimation accuracy of the algorithm was found to worsen with reducing elevation. The overall error remains within 3 dB for 0.5 dB of measurement noise and up to lowest elevation of 30°. The simple approach of the model in conjunction with the adequate accuracy makes this algorithm a potential candidate to be used for real‐time open‐loop fade mitigation.     

一种用于便携式射频识别阅读器的CMOS功率放大器

针对一种特定的射频识别技术的通讯协议(ISO1800-6B),提出了一种应用于射频识别读写器中的发射机前端结构,以实现发射信号的OOK调制.采用0.18μm CMOS工艺实现的这种高效率、高度集成的无线发射机前端由射频信号调制器、E类功率放大器以及相应的逻辑控制单元组成,其中的功率放大器的小信号增益约为23dB,其1dB压缩点输出功率为17.6dBm,最大输出功率为19.0dBm,而最大功率增加效率为35.4%.整个发射机的输出信号满足相应协议的特定要求,可以实现不同调制深度(18%和100%)的射频信号输出.