RF Band‐Pass Sampling Frontend for Multiband Access CR/SDR Receiver

Radio frequency (RF) subsampling can be used by radio receivers to directly down‐convert and digitize RF signals. A goal of a cognitive radio/software defined ratio (CR/SDR) receiver design is to place the analog‐to‐digital converter (ADC) as near the antenna as possible. Based on this, a band‐pass sampling (BPS) frontend for CR/SDR is proposed and verified. We present a receiver architecture based second‐order BPS and signal processing techniques for a digital RF frontend. This paper is focused on the benefits of the second‐order BPS architecture in spectrum sensing over a wide frequency band range and in multiband receiving without modification of the RF hardware. Methods to manipulate the spectra are described, and reconstruction filter designs are provided. On the basis of this concept, second‐order BPS frontends for CR/SDR systems are designed and verified using a hardware platform.     

基于软件无线电的中短波接收机设计

目前广播系统正由模拟体制向数字化体制过渡,数字版权管理（DRM,Digital Radio Mondiale）系统就是针对30 MHz以下频段的数字广播标准。作为软件无线电的核心技术之一,数字接收机技术得到了越来越普遍的应用。介绍了一种基于软件无线电的中短波接收机的硬件系统结构,这种软件无线电接收机结构可以同时解码音频和数据流,兼容目前的模拟调幅广播和数字调幅广播标准。重点讨论了电调滤波器的设计,最后使用EDA软件进行仿真,并给出了仿真结果。     

Design of a digital FM demodulator based on a 2nd-order all-digital phase-locked loop

Software-defined radio (SDR) is a revolution in radio design due to the ability to create radios that can self-adapt on the fly. In SDR devices, all of the signal processing is implemented in the digital domain, mainly on DSP blocks or by DSP software. By simply downloading a new program, a SDR device is able to interoperate with different wireless protocols, incorporate new services, and upgrade to new standards. Therefore, massively parallel signal processing at higher frequencies are needed to implement a realistic SDR. Thus, FPGAs have been used extensively for implementing essential functions in SDR architectures at lower frequencies. In this paper, we explore the design of a digital FM receiver using the approach of an All-Digital Phase Locked-Loop (ADPLL). The circuit is designed in VHDL, then synthesized and simulated using LeonardoSpectrum Level 3 and ModelSim SE 6, respectively. It operates at a frequency up to 150 MHz and occupies the area of roughly 15 K logic gates.     

Software defi ned radio: Part 22 in a series of tutorials on instrumentation and measurement

A software defined radio (SDR) [1] is a communication system that performs many of its required signal processing tasks in a programmable digital signal processing (DSP) engine. The engine is coupled to the air interface of analog circuits and antennae by analog-to-digital and digital-to-analog converters (ADCs and DACs). The SDR's software reprograms the DSP segment of the radio's physical layer to reconFigure the radio system parameters and can thus synthesize multiple radios. The software can also select and alter the air interface components as well as the higher level data processing layers of the radio system.     

软件无线电技术综述

软件无线电是最近几年提出的一种实现无线电通信的体系结构,被认为是继模拟通信、数字通信之后的第三代无线电通信技术。在无线电应用领域,软件无线电已经成为一个重要的研究课题。特别是在信息成为主导市场竞争优胜劣汰、军事斗争成败等重大问题的关键因素后,软件无线电技术作为一种有利于技术体制改革创新、有利于提高信息处理能力的关键技术,已经得到了飞速的发展。介绍了软件无线电的基本概念、功能结构、关键技术等问题,同时阐述了软件无线电的应用和发展前景。     

Signal processing challenges for applying software radio principles in future wireless terminals: an overview

The general idea of software radio is to develop highly integrated radio transceiver structures with high degree of flexibility and multimode capabilities, achieved through increased role of digital signal processing software in defining the functionalities which have traditionally been implemented with analog RF techniques. This paper explores the software radio concept from the receiver architecture and signal processing points of view, with mainly the wireless terminal application in mind. We first discuss the critical issues in alternative receiver architectures with simplified analog parts and increased configurability. We also introduce certain advanced digital signal processing techniques which could potentially relieve some of the essential problems and pave the way towards DSP‐based, highly integrated, and highly configurable terminals. Big emphasis is on efficient digital multirate signal processing methods and complex (I/Q) signal processing. Copyright © 2002 John Wiley & Sons, Ltd.     

FPGA Implementation of a Power Amplifier Linearizer for an ETSI-SDR OFDM Transmitter

Most satellite digital radio （SDR） systems use orthogonal frequency-division multiplexing （OFDM） transmission, which means that variable envelope signals are distorted by the RF power amplifier （PA）. It is customary to back off the input power to the PA to avoid the PA nonlinear region of operation. In this way, linearity can be achieved at the cost of power efficiency. Another attractive option is to use a linearizer, which compensates for the nonlinear effects of the PA. In this paper, an OFDM transmitter conforming to European Telecommunications Standard Institute SDR Technical Specifications 2007-2008 was designed and implemented on a low-cost field-programmable gate array （FPGA） platform. A weakly nonlinear PA, operating in the L-band SDR frequency, was used for signal transmission. An adaptive linearizer was designed and implemented on the same FPGA device using digital predistortion to correct the undesired effects of the PA on the transmitted signal. Test results show that spectral distortion can be suppressed between 6-9 dB using the designed linearizer when the PA is driven close to its saturation region.     

Resource management implications and strategies for SDR clouds

This paper analyzes the computing resource management implications of SDR base stations implemented as SDR clouds. SDR clouds describe distributed antennas that connect to a data center for digital signal processing. The data center employs cloud computing technology, providing a virtualized computing resource pool. The service area of a single SDR cloud may be a metropolitan area with a high user density. Hence, the data center will execute thousands of SDR applications in parallel, providing wireless communications services to several radio cells. Whenever a user initiates or terminates a wireless communications session, computing resources need to be allocated or deallocated in real time. We therefore propose a hierarchical resource management. This paper justifies such an approach and analyzes different resource management strategies. The results indicate the need for strategies that can dynamically adapt to the given user traffic distribution.     

SDR——未来无线通信设备的基本概念

根据国际上的最新进展,本文对软件定义无线电（SDR）进行讨论和介绍。SDR是一个新的概念和体系,它是一个可重编程的可重构的,能支持多种无线通信体制和标准的无线通信设备。本文介绍了美国对SDR设备的要求,此技术为产品开发、制造商、运营商及最终用户带来了好处,以及SDR所面临的挑战。显然,在几年内,SDR技术将广泛使用于新一代通信产品的设计中,基于SDR的无线通信设备将成为市场中的主要部分。     

Postcanceling techniques for simultaneous broadcasting of analog FM and digital data

We consider simultaneous broadcasting of low-power digital data and analog FM and present reliable receivers for the digital data. Due to the relatively low power level of the digital data and the interference suppression capability of analog FM, standard analog FM receivers can reliably recover the analog FM audio signal. To recover the digital data, an extended Kalman filter front end is developed that exploits the capture capability of analog FM to reconstruct and postcancel the analog FM component from the received composite signal. Simulations are conducted with artificial analog FM signals, suggesting that postcanceling schemes can provide higher data rates than their precanceling counterparts, at a lower transmission delay penalty but higher digital receiver complexity. For analog FM to digital signal power level ratios in the range of 30-50 dB, the postcanceler digital signal recovery appears fairly robust, providing digital signal-to-noise ratios of 2-7.5 dB. The corresponding uncoded bit error rates strongly depend on the power level difference between the host analog FM and the digital data signal. In particular, at 260 kb/s and E/sub b//N/sub o/=10 dB they range between 1% to about 15%, and can be reduced to acceptable levels using standard channel coding techniques.     

Analysis and Implementation of a Time-Interleaved ADC Array for a Software-Defined UWB Receiver

A software-defined radio (SDR) for ultrawideband (UWB) communication systems places several stringent requirements on the analog-to-digital converter (ADC). One alternative to using a single ADC is to sample the received signal with an array of lower speed ADCs that were driven by interleaved sampling clocks; however, mismatches among the ADCs will result in signal distortion. This paper makes three important contributions to overcoming this problem: 1) analytical quantification of the impact of ADC gain, offset, and timing mismatches on the performance of a time-interleaved sampling ADC array for UWB signals; 2) demonstration of the efficacy of using a pilot-based matched-filter architecture to mitigate the impact of timing mismatches in the presence of multipath; and 3) implementation of an 8-ADC time-interleaved UWB SDR testbed that operates at an effective sampling frequency of 6.4 GHz. In addition, our findings allow for the design specification of the number of pilots required to obtain a desired system performance. The simulation and measured performance results from this paper demonstrate that ADC mismatches can be controlled to within plusmn10%, yielding acceptable levels of distortion and bit-error-rate (BER) performance on the UWB SDR testbed. Both analytical and simulation results also demonstrate the efficacy of a pilot-based matched filter in mitigating the impact of timing mismatch errors, even in the presence of multipath.     

Toward Wide-Band High-Resolution Analog-to-Digital Converters Using Hybrid Filter Bank Architecture

The paper presents the problem of design and simulation of a high-speed wide-band high-resolution analog-to-digital (ADC) converter working in a bandpass scenario. Such converters play a crucial role in software-defined radio and in cognitive radio technology. One way to circumvent the limits of today’s ADC technologies is to split the analog input signal into multiple components and then sample them with ADCs in parallel. The two main split approaches, time interleaved and frequency splitting, can be modeled using a filter bank paradigm, where each of these two architectures requires a specific analysis for its design. In this research, the frequency splitting approach was implemented with the use of a hybrid filter bank ADC, which requires an output digital filter bank perfectly matched to the input analog filter bank. To achieve this end, an analog transfer function, together with an assumption of strictly band-limited input signal, has been used to design the digital filter bank so far. In contrast, the author proposes dropping the band-limit assumption and shows that the out-of-band input signal has to be taken into account when designing a hybrid filter bank.     

频谱分析仪的数字中频设计方案

为了提高频谱分析仪的频率分辨率,同时降低模拟中频、视频电路组件的生产难度,现代频谱分析仪大多采用数字中频技术,利用模数转换器把模拟中频信号转换为数字信号,经过数字下变频、数字滤波、数字检波或快速傅里叶变换运算后得到射频信号的幅度和频率信息,再经过视频滤波处理后得到清晰的信号频谱.文中论述的信号处理方案实现了频谱的数字分析,在实际应用中验证了其指标的稳定.     

Filter Bank Channelizers for Multi-Standard Software Defined Radio Receivers

The ability to support multiple channels of different communication standards, in the available bandwidth, is of importance in modern software defined radio (SDR) receivers. An SDR receiver typically employs a channelizer to extract multiple narrowband channels from the received wideband signal using digital filter banks. Since the filter bank channelizer is placed immediately after the analog-to-digital converter (ADC), it must operate at the highest sampling rate in the digital front-end of the receiver. Therefore, computationally efficient low complexity architectures are required for the implementation of the channelizer. The compatibility of the filter bank with different communication standards requires dynamic reconfigurability. The design and realization of dynamically reconfigurable, low complexity filter banks for SDR receivers is a challenging task. This paper reviews some of the existing digital filter bank designs and investigates the potential of these filter banks for channelization in multi-standard SDR receivers. We also review two low complexity, reconfigurable filter bank architectures for SDR channelizers based respectively on the frequency response masking technique and a novel coefficient decimation technique, proposed by us recently. These filter bank architectures outperform existing ones in terms of both dynamic reconfigurability and complexity.     

Increasing SDR Receiver Dynamic Range by ADC Diversity

Nowadays, most radio implementations are based on software-defined radio (SDR) technologies. The capabilities of digital signal processing enable new applications like low power wide area networks (LPWAN), which are expected to play a decisive role in the upcoming Internet of Things. Centralized gateways, usually realized in an SDR architecture, are used to connect many thousands of objects to the internet. Due to the high variance of the received signal level, a high dynamic range is required for the SDR receiver front-end. In current receiver architectures, the dynamic range is mainly limited by the analog-to-digital converter (ADC). Several techniques have been proposed to extend the dynamic range by stacking multiple ADCs and driving them with different gain factors. Correlation of quantization noise was identified as key parameter to determine the dynamic range enhancement. This paper compares the proposed techniques and extends existing analysis tools for the use of arbitrary gain factors. Additionally, the influence of further noise sources like thermal noise and jitter are taken into account. The theoretical considerations are supported by simulations and measurements using a real LPWAN SDR implementation.     

双模对讲机中数字编码静噪系统的实现

由于数字对讲机的频谱利用率比模拟对讲机高得多,还由于数字对讲机能够提供模拟对讲机无法达到的数据处理种类及灵活性,因此模拟对讲机的数字化改造进程已势不可挡.在这个过渡时期,需要开发数模兼容的双模对讲机,以满足市场需要并实现平缓过渡.双模对讲机的数字基带信号处理系统已经用数字信号处理器(DSP)实现,以往使用专用芯片实现的...     

Effects of Noise and Jitter in Bandpass Sampling

BandPass Sampling (BPS) is an undersampling technique by intentional aliasing. BPS enables one to have an interface between the IF stage and the ADC in a radio receiver. Conventional uniform BPS at Nyquist rate normally results in a low Signal-to-Noise Ratio (SNR) due to noise spectrum aliasing. The noise (e.g. kT/C noise introduced in a voltage-mode sampler) is combined in each of the Nyquist bands within the bandwidth of the sampling device. Also timing jitter causes a performance degradation in BPS.In this paper, signal spectrum aliasing, noise aliasing and jitter effects in BPS is analyzed. It is verified by simulation that NonUniform Sampling (NUS) has the potential to suppress signal spectrum aliasing and relax the requirement on the anti-aliasing (AA) filter. Jitter effects in BPS are compared to LowPass Sampling (LPS) case. However, a signal cannot be reconstructed from its nonuniform samples by using only ideal lowpass filtering (classic Shannons reconstruction). Finally, signal reconstruction in the presence of noise and jitter are investigated for three Reconstruction Algorithms (RAs) aimed at NUS.Yi-Ran Sun received her bachelor degree in physics in 1998 and master degree in Electronic engineering in 2002 in China and in Sweden, respectively. She is currently pursuing the Ph.D. degree in electronic engineering at Royal Institute of Technology (KTH), Stockholm. Her current research interests are in the area of mixed-signal system design in radio receiver front-ends. Of special focus is bandpass sampling technique and corresponding area of signal processing.Svante Signell (M 95) received the Dr. Sc. degree from the Royal Institute of Technology (KTH) Stockholm, Sweden, in 1987, in the area of periodically time-varying linear systems with applications to filters.From 1987 to 1991, he was with ABB HAFO, working on mixed-signal system-on-chip design, mainly in the area of hearing aids and pacemakers. Between 1991 and 2003, he was with Ericsson Radio working with technology research for base stations and signal processing for future wireless systems. He has been holding various positions such as project leader and as an expert on analog and digital signal processing at the company level.Since 1988, he has been involved as a Consultant to companies such as ABB Hafo, Ericsson Radio, Ericsson Telecom, Siemens Elema, and Standard Radio & Telefon, as well as course developer and lecturer in courses held at companies and universities. Since the beginning of 2000, he is an Adjunct Professor in Mixed Signal System Design at KTH.He has authored around 50 papers published in international conference proceedings and magazines and holds eight patents, with more pending. He has been reviewer for IEEE magazines and conferences, program committee member, expert reviewer for a European Commission project 1997–2001, and reviewer for national research programs on both project and program level. His main research interests include, but are not limited to, systems-on-chip (SoC), software-defined radio (SDR) and critical technologies for the realization of SoC and SDR, in particular, on how to find the best combination of analog and digital signal processing.     

Equalization of microwave digital radio channels with a hybridacousto-optic and digital processor

Digital radio transmission systems use complex modulation schemes that require powerful signal processing techniques to correct channel distortions and to minimize bit-error rates (BERs). Combined analog and digital processors are investigated for minimizing the mean square error (MSE) of the radio receiver. The analog filters are implemented using acousto-optic (AO) processing since rapidly adaptable, inverse channel filters can be produced for either minimum or nonminimum phase channels. A specific architecture is identified and a laboratory system is tested to verify the ability of the processor to track and correct time-varying channels. Computer simulations are used to show that hybrid analog and digital equalization allows an increase in the modulation capacity of radio, relative to all digital equalization, while maintaining similar equipment signatures     

软件无线接收数字前端的实现

基于软件无线电(SDR)基本思想,提出数字前端概念,对数字前端的组成、功能和基于CORDIC算法的数字下变频、多速率滤波等关键技术进行了介绍。设计了一种软件无线电接收系统,实验表明该设计方案扩展性和移植性好,技术性能达到要求。仿照GSM接收系统技术参数,设计了多速率滤波器,仿真表明,数字前端采用多速率滤波器,能节省成本。对SDR的发展进行了展望。