Performance Investigation of Silicon-on-Insulator Junctionless Drain Extended FinFET for High Power,Radio Frequency Applications

Silicon - This research article explores the scope of Silicon-On-Insulator (SOI) Junctionless (JL) Drain Extended (De) FinFET and compared it with Conventional SOI Drain Extended FinFET (Conv. SOI...     

A Comprehensive Analysis of Junctionless Tri-Gate (TG) FinFET Towards Low-Power and High-Frequency Applications at 5-nm Gate Length

Silicon - Tri-Gate (TG) FinFETs are the most reliable option to get into deeply scaled gate lengths. This paper analyses an optimized 5 nm gate length (LG) n-channel TG Junctionless SOI...     

Dual-Gate Junctionless FET on SOI for High Frequency Analog Applications

Silicon - This paper presents a dual-gate junctionless FET (DGJLT) on SOI for enhanced analog/RF performance. The Si channel of device is sandwiched between the two gates placed in separate...     

Process Variation Study of SELBOX Inverted- T Junctionless FinFET for High-Performance Applications

This work investigates the performance of the inverted-T (IT) junctionless (JL) FinFET with selective buried oxide (SELBOX) topology. The electrical charac     

Design and Performance Evaluation of Sub-10 nm Gaussian Doped Junctionless SOI and SELBOX FinFET

Silicon - In this paper influences of uniform and non-uniform doping on the performance of SOI and SELBOX FinFET at gate length of sub-7 nm are evaluated. Junctionless devices require very...     

Circuit Analysis and Optimization of GAA Nanowire FET Towards Low Power and High Switching

Silicon - The main aim of this work is to study the effect of symmetric and asymmetric spacer length variations towards source and drain on n-channel SOI JL vertically stacked (VS) nanowire (NW)...     

Investigation of Recessed Junctionless Double Gate MOSFET for Radio Frequency Applications

Silicon - Junctionless Metal Oxide Semiconductor Field-Effect Transistor (JL MOSFET) is one of the promising candidate to replace the junction based MOSFET for upcoming technology nodes....     

Analysis of Sub-Threshold Adiabatic Logic Model Using Junctionless MOSFET for Low Power Application

Silicon - In this paper Junctionless Double Gate MOSFET based Efficient Charge Recovery Logic (JL-ECRL) circuits have been driven in sub-threshold regime for the first time in literature to...     

Core-Shell Nanowire Junctionless Accumalation Mode Field-Effect Transistor (CSN-JAM-FET) for High Frequency Applications - Analytical Study

Silicon - Here, an analytical model has been proposed for Core-Shell-Nanowire-Junctionless-Accumulation-Mode- Field-Effect Transistor (CSN-JAM-FET) for High Frequency Applications. CSN-JAM-FET has...     

A Holistic Approach on Junctionless Dual Material Double Gate (DMDG) MOSFET with High k Gate Stack for Low Power Digital Applications

Silicon - The 2D analytical models for electrostatic potential, threshold voltage, subthreshold swing, Drain Induced Barrier Lowering (DIBL) and drain current of the Dual Material Double Gate...     

Design and Analysis of Gate Stack Silicon-on-Insulator Nanosheet FET for Low Power Applications

Silicon - Since the introduction of fast integrated circuits, semiconductor manufacturers have concentrated their efforts on reducing the size of transistors. Increased working frequencies (shorter...     

Design and Simulation Analysis of Silicon Germanium Nanowire FET for Low Power Applications

Silicon - In this paper the performance analysis of nanowire has been presented. The comparison of Si Nanowire FET and Ge Nanowire FET has been carried out. The sub threshold slope of Si Nanowire...     

Reliability and Power Analysis of FinFET Based SRAM

Silicon - Demand for accommodating more and new functionalities within a single chip such as SOC needs novel devices and architecture such as FinFET devices instead of MOSFET. FinFET emerged as a...     

Analytical Model of Double Gate Stacked Oxide Junctionless Transistor Considering Source/Drain Depletion Effects for CMOS Low Power Applications

This paper proposes a 2-D analytical model developed for Double Gate Junctionless Transistor with a SiO2/HfO2 stacked oxide structure. The model is solved     

Extensive Study of Underlap Length Effect for 3-D SOI FinFET to Achieve High Switching Ratio and Low Power

Silicon - The primary purpose of this work is to study the effect of symmetric and asymmetric variation of underlap regions both on source and drain side of 3D SOI n-FinFET. Underlap length is...     

Modified Core-Shell Double Gate Junctionless MOSFET with High ON-State and Low Leakage Currents

Silicon - In this proposed article, an investigation has been studied for low leakage current and high on-state current with heavily doping in source and drain region of Double Gate Junctionless...     

Linearity and Analog Performance Analysis of Silicon Junctionless Bulk FinFET Considering Gate Electrode Workfunction Variability and Different Fin Aspect Ratio

Silicon - In case of conventional MOSFET structures, Short-Channel Effects (SCEs) are key issues for device performance as dimensions of these devices are reaching nanometer scales following...     

Subthreshold Current Modeling of Stacked Dielectric Triple Material Cylindrical Gate All Around (SD-TM-CGAA) Junctionless MOSFET for Low Power Applications

Silicon - Stacked Dielectric Triple Material Cylindrical Gate All Around (SD-TM-CGAA) Junctionless MOSFET has been explored for low power applications. This paper presents an analytical model of...     

Linearity Distortion Analysis of Junctionless Quadruple Gate MOSFETs for Analog Applications

Silicon - This paper examines a Junctionless quadruple gate (JLQG) MOSFET for analog and linearity distortion performance by numerically calculating transconductance and its higher order...     

Design and Optimization of Dual Material Gate Junctionless FinFET Using Dimensional Effect,Gate Oxide and Workfunction Engineering at 7 nm Technology Node

Silicon - In this paper, we designed and analyzed the performance of Dual Material Gate Junctionless FinFET(DMG JLFinFET) using gate engineering with high-k dielectrics for nanoscale applications....