前馈环形振荡器的结构与相位噪声研究

基于高速串行通信系统中锁相环和时钟数据恢复电路的需求,研究了前馈环形振荡器的结构与工作原理;在传统结构的基础上,将前馈路径耦合至主路径反相器的源极,可以提高输出信号的边沿速率;最后基于Hajimiri模型的脉冲灵敏度函数进行分析,提出的结构有效降低了热噪声和闪烁噪声的引入.在28 nm CMOS工艺下设计了单源极前馈型...     

Application of the computer‐aided analysis for modeling the behavior of a TCXO

Quartz crystal oscillators for many radio frequency (RF) applications must provide a high‐frequency stability in a wide temperature range. To do this, a temperature compensation network is commonly included. This study analyzes and determines the frequency behavior of an oscillator circuit with variations in temperature and shows how simulation may be employed for the design of high‐stability quartz crystal oscillators. © 2001 John Wiley & Sons, Inc. Int J RF and Microwave CAE 11: 22–32, 2001.     

Accurate Simulation of RF MEMS VCO performance including phase noise

A new coupled circuit and electrostatic/mechanical simulator (COSMO) is presented for the design of low phase noise radio frequency (RF) microelectromechanical systems (MEMS) voltage-controlled oscillators (VCOs). The numerical solution of device level equations is used to accurately compute the capacitance of a MEMS capacitor. This coupled with a circuit simulator facilitates the simulation of circuits incorporating MEMS capacitors. In addition, the noise from the MEMS capacitor is combined with a nonlinear circuit-level noise analysis to determine the phase noise of RF MEMS VCO. Simulations of two different MEMS VCO architectures show good agreement with experimentally observed behavior.     

Real-time reconfigurable subthreshold CMOS perceptron.

In this paper, a new, real-time reconfigurable perceptron circuit element is presented. A six-transistor version used as a threshold gate, having a fan-in of three, producing adequate outputs for threshold of T =1, 2 and 3 is demonstrated by chip measurements. Subthreshold operation for supply voltages in the range of 100-350 mV is shown. The circuit performs competitively with a standard static complimentary metal-oxide-semiconductor (CMOS) implementation when maximum speed and energy delay product are taken into account, when used in a ring oscillator. Functionality per transistor is, to our knowledge, the highest reported for a variety of comparable circuits not based on floating gate techniques. Statistical simulations predict probabilities for making working circuits under mismatch and process variations. The simulations, in 120-nm CMOS, also support discussions regarding lower limits to supply voltage and redundancy. A brief discussion on how the circuit may be exploited as a basic building block for future defect tolerant mixed signal circuits, as well as neural networks, exploiting redundancy, is included.     

低压低功耗CMOS微电容式传感器数字型接口电路研究

针对便携、无线设备的低电压、低功耗需求,基于TSMC 0.18μm CMOS工艺设计提出一种面向CMOS微电容式传感器的接口转换电路。将敏感电容、参考电容与接口电路集成于同一芯片,可以将对湿度敏感的电容变化量线性转换为方波脉冲信号的宽度,并直接输出数字信号。实验仿真结果显示在1.5 V电源供压下电路消耗的功耗仅为1.95 mW,转换分辨率达到4.38μs/pF,与同类接口电路相比具有线性度好、有效减少电容间失配和对温度与工艺角变化不敏感等优点。     

面向FPGA应用的硬件木马植入与检测技术研究

近年来,FPGA的应用愈加广泛。为确保FPGA中数据安全可信,在基于环形振荡器的硬件木马检测方法之上,提出一种在Altera FPGA中使用增量编译技术实现环形振荡器和木马植入的方法以及使用归一化差值算法发现并定位木马的数据分析方法。设计基于环形振荡器的硬件木马检测电路,根据系统规模共部署6级振荡环,每级环形振荡器由121个与非门构成。根据木马电路类型和功耗来源,在电路中依次植入四种典型硬件木马,使用归一化差值算法分析环形振荡器振荡频率,最终实现所有类型的木马定位与检测。检测结果表明,基于环形振荡器的硬件木马检测方法在FPGA中具有很好的木马检出效果,不仅能够检测具有较大动态功耗的木马,也可以完成对具有很小的静态功耗木马的检测。所提出的方法已经在实际FPGA工程中使用,为及时发现木马提供了一种有效途径。     

Low power quadrature voltage controlled oscillator

In this article, a low voltage low power quadrature voltage controlled oscillator (QVCO) coupled by four P&N transistors is presented. First, a novel negative resistance inductance capacitor (LC) oscillator is described, the N‐metal oxide semiconductor (NMOS) and P‐metal oxide semiconductor (PMOS) transistors are in series with the LC tank in the direct‐current (DC) path, and they generate the required negative resistance to compensate the energy loss of the LC tank and maintain the steady oscillation of the oscillator. Then, based on two identical LC oscillators, four P&N transistors are used as coupling terminals to generate quadrature outputs. The proposed QVCO is designed and simulated with GlobalFoundries' 0.18 μm CMOS RF process. The Cadence IC design tools postlayout simulation results demonstrate that the oscillation frequency of the QVCO can be tuned from 2.0 to 5.6 GHz by adjusting the bias voltage, and the phase noise of the voltage controlled oscillator is ?114 dBc/Hz at 1 MHz offset. Moreover, the proposed QVCO consumes only 2.31 mW from a 1.2 V supply voltage and it occupies a compact area of 0.45 mm² including the bond pads.     

一种频率稳定的低功耗振荡器电路设计

设计了一种频率稳定的低功耗张弛振荡器电路。采用恒流源对电容两端同时充电和放电,然后将电容两端电压送入后级比较器进行判决,使得输出频率只与恒流源电流、电容以及比较器比较窗口相关。该电路采用GSMC 0.18μm CMOS工艺,在5 V电源电压以及室温条件下仿真,输出频率为123.6 kHz,平均电流消耗为2.67μA;在2 V～5.5 V电源电压和-40℃-+85℃的温度变化范围内,输出频率精度在-6.5%-1.3%范围内。     

基于射频单电子晶体管的超灵敏电荷计的模拟研究

集成单电子晶体管(single electron transistor, SET)与射频共振电路的射频单电子晶体管(radio frequency single electron transistor, RF SET)是一种高速高灵敏的电荷计。本文通过建立RF SET的等效电路模型,对共振电路及其与射频传输线的集成进行模拟分析,得到了SET阻抗的最佳匹配,获得了所需的谐振频率、品质因子和对SET阻抗的灵敏度。结果表明,受电荷调制的SET阻抗直接影响着共振电路的品质因子、阻抗和射频透射/反射系数。射频信号随着SET的阻抗降低而减小,峰位基本不变。在SET阻抗小于200 k?时,共振信号幅度随阻抗的变化率较大。透射式与反射式两种结构相比,前者共振频率及品质因子更高,后者则具有更高的灵敏度优势。     

一种三级误差运放单密勒补偿技术的研究

针对新的三级运放单密勒补偿拓扑结构,建立小信号等效模型。从结构的稳定性出发,采用极点复数补偿法对系统进行补偿,优化了相位裕度、转换速率和调整时间。设计三级运放电路,负载为25 kΩ/120 pF,给出了在TSMC 0.18μm CMOS工艺下的仿真验证。     

Design of MMIC oscillators using GaAs 0.2 μm PHEMT technology

We propose a feedback type oscillator and two negative resistance oscillators.These microwave oscillators have been designed in the S band frequency.A relatively symmetric resonator is used in the feedback type oscillator.The first negative resistance oscillator uses a simple lumped element resonator which is substituted by a microstrip resonator in the second oscillator to improve results.The negative resistance oscillator produces 4.207 dBm and 7.124 dBm output power with the lumped element resonator and microstrip resonator respectively,and the feedback type oscillator produces ?10.707 dBm output power.The feedback type oscillator operates at 3 GHz with phase noise levels at-83.30 dBc/Hz and-103.3 dBc/Hz at 100 kHz and 1 MHz offset frequencies respectively.The phase noise levels of the negative resistance oscillator with the lumped element resonator are-94.64 dBc/Hz and-116 dBc/Hz at 100 kHz and 1 MHz offset frequencies respectively,at an oscillation frequency of 3.053 GHz.With the microstrip resonator the phase noise levels are-99.49 dBc/Hz and-119.641 dBc/Hz at 100 kHz and 1 MHz offset frequencies respectively,at an oscillation frequency of 3.072 GHz.The results showed that both the output power and the phase noise of the negative resistance oscillators were better than those of the feedback type oscillator.     

Folded down-conversion mixer for a 60 GHz receiver architecture in 65-nm CMOS technology

We present the design of a folded down-conversion mixer which is incorporated at the final down-conversion stage of a 60 GHz receiver. The mixer employs an ac-coupled current reuse transconductance stage. It performs well under low supply voltages, and is less sensitive to temperature variations and process spread. The mixer operates at an input radio frequency （RF） band ranging from 10.25 to 13.75 GHz, with a fixed local oscillator （LO） frequency of 12 GHz, which down-converts the RF band to an intermediate frequency （IF） band ranging from dc to 1.75 GHz. The mixer is designed in a 65 nm low power （LP） CMOS process with an active chip area of only 0.0179 mm^2. At a nominal supply voltage of 1.2 V and an IF of 10 MHz, a maximum voltage conversion gain （VCG） of 9.8 dB, a double sideband noise figure （DSB-NF） of 11.6 dB, and a linearity in terms of input 1 dB compression point （Pin, 1dB） of-13 dBm are measured. The mixer draws a current of 5 mA from a 1.2 V supply dissipating a power of only 6 roW.     

A CMOS temperature sensor and auto-zeroing circuit with inaccuracy of −1/+0.7 °C between −30 to 150 °C

An energy efficient complementary metal-oxide-semiconductor (CMOS) temperature sensor and signal conditioning circuit with auto zeroing technique has been enunciated in this paper. In the present study, a novel CMOS temperature sensor based on sub-threshold MOS operation has been presented, which is designed for Aerospace applications. The proposed sensor does not use bipolar junction transistor (BJT) for sensing; instead it utilizes the temperature dependency of the threshold voltage of MOSFET. The proposed temperature sensor is designed to sense −30 to 150 °C and its sensitivity is 1.4 mV/°C while the power consumption is 60 nW. The accuracy of sensor is mainly limited by offset and flicker noise (1/f) noise, which is cancel by the autozeroing circuit with the help of switch capacitor circuit. The sensor circuit is designed with biasing sub circuit for controlling the curvature correction. The proposed temperature sensor and signal conditioning are simulated in a Cadence Analog Design Environment with UMC90 nm library. The simulation result shows an inaccuracy of −1/+0.7 °C.

     

A current‐mode tunable low‐supply‐voltage ring oscillator

A new circuit topology using a current‐mode low‐pass filter for sinusoids has been presented. The technique is relatively simple, in the proposed circuit, only three identical current‐mode low‐pass filters are connected to each other to realize the small signal path. No external passive components are required except for three capacitors. When compared with LC oscillators, the die area of this work, without inductors, is much smaller. When compared with voltage‐mode ring oscillators, the supply voltage of this work is much lower. As a particular example, a 2.4 GHz, 1.2‐V power supply, 5‐mW sinusoidal oscillator is demonstrated. The oscillation frequency is tuned by the value of that three capacitors, over ～900 MHz, and the tuning range is 37.5%. The phase noise results in ?94 and ?120 dBc/Hz at 1 and 10 MHz from the carrier, respectively. © 2010 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2010.     

集成CMOS温度传感器设计、实现和测试

基于MOS管的阈值电压和载流子迁移率随温度的变化关系,设计了一种与CMOS工艺兼容的集成温度传感器。该温度传感器选用charted0.35μm工艺库,以Cadence进行电路图、版图设计,并以CadenceSpectre工具进行仿真,最后经流片、测试,实测与仿真对比结果显示:温度在25～105℃之间变化时,输出频率的变化范围为10.19～5.81MHz,且有较好的线性。此传感器对片上系统温度的监测、过热报警和振荡器频率漂移的补偿等均有重要的意义。     

具有频率抖动功能的新型振荡器电路

电源在其开关频率及倍频处,会辐射较大的电磁干扰能量,采用频率抖动技术可以将集中的干扰能量分散到较宽的频带上,从而降低干扰幅值。在对常见的振荡器进行分析的基础上,设计了一种带有频率抖动功能的振荡器。该振荡器中心频率为68.2kHz,可以实现频率上下各抖动7%幅值。在CMOS工艺条件下经过仿真,满足设计要求。     

应用于网络安全协处理器的真随机数产生器

介绍一款基于环形振荡器的真随机数产生器。电路使用固定频率时钟采样可控频率振荡器的输出,使用级间反馈随机改变可控频率振荡器的振荡频率。设计启动电路来保证环形振荡器快速起振,在使能信号无效时断开振荡电路以节省功耗。电路采用CMOS 0．18μm标准工艺实现,使用Hspice-RF仿真环形振荡电路的相位抖动以获得最优设计参数。仿真结果表明,电路在输出速率为1Gb／s时产生的随机序列具有良好的随机性,该设计可用于网络安全协处理器中。     

基于射频单电子晶体管的超灵敏电荷计的数值分析

集成单电子晶体管SET（Single Electron Transistor）与射频共振电路的射频单电子晶体管RF SET（Radio Frequency Single Electron Transistor）是一种高速高灵敏的电荷计。通过建立RF SET的等效电路模型,对共振电路及其与射频传输线的集成进行模拟分析,得到了SET阻抗的最佳匹配,获得了所需的谐振频率、品质因子和对SET阻抗的灵敏度。结果表明,受电荷调制的SET阻抗直接影响着共振电路的品质因子、阻抗和射频透射/反射系数。射频信号随着SET的阻抗降低而减小,峰位基本不变。在SET阻抗小于200 kΩ时,共振信号幅度随阻抗的变化率较大。透射式与反射式两种结构相比,前者共振频率及品质因子更高,后者则具有更高的灵敏度优势。     

矿用无线电系统及设备工作频段选择

提出了矿用无线电系统及设备严禁使用广播、电视、射电天文、安全救助、无线电导航等频率,并给出了严禁使用的频段。提出了矿用无线电系统及设备应优先选用业余频段,优先选用工业、科学和医疗设备频段,并给出了推荐使用的频段。提出了矿用无线电系统及设备若与地面业务一致或相近时,宜选用与地面一致或相近的频段,并给出了业务相近的频段。给出了煤矿井下在用的频段。     

2．4GHz低相位噪声CMOS负阻LC压控振荡器设计

为了有效降低工作于射频段的全集成CMOS负阻LC压控振荡器的相位噪声．介绍了利用电阻电容滤波技术对振荡器相位噪声的优化,并采用Chartered 0．35μm CMOS标准工艺设计了一款全集成CMOS负阻LC压控振荡器,其中心频率为2.4GHz,频率调谐范围达到300MHz,在3．3V电压下工作时,静态电流为12mA,在偏离中心频率600kHz处,仿真得到的相位噪声为-121dBc／Hz。该设计有效地验证了电阻电容滤波技术对相位噪声的优化效果,并为全集成低相位噪声CMOS负阻LC压控振荡器的设计提供了一种参考电路。