Diode multiplexer in the multi-Gbit/s range

A clocked multiplexer circuit was realised which provided 4.48 Gbit/s, 5 Gbit/s, and 7.84 Gbit/s output-pulse streams for p.c.m.-type input tributaries at 1.12 Gbit/s, 0.25 Gbit/s, and 1.12 Gbit/s, respectively. The circuit employed essentially ultra-broadband 180° hybrids, step-recovery diodes, and GaAs Schottky-barrier diodes. Output voltages up to 2 V were obtained across a load of 50 ?. The pulse width of the output pulses was approximately 100 ps.     

Silicon bipolar decision circuit handling bit rates up to 5 Gbit/s

A high-speed silicon bipolar decision circuit is presented which operates up to 5 Gbit/s. It may serve as a subcomponent for integration in a regenerator/repeater circuit for multi-gigabit fiber-optic trunk lines. The circuit was implemented in a standard bipolar silicon technology featuring oxide-wall isolation, 2-μm emitter stripe widths, and a transit frequency of 9 GHZ atV_{CE} = 1V. The measured clock-phase-margin of the decision circuit at 4 Gbit/s corresponds to two thirds of a bit slot and to half a bit slot at 5 Gbit/s. The minimum input sensitivity at 4 Gbit/s is less than 150 mV.     

160 Gbit/s soliton data transmission over 200 km

Polarisation- and time-domain-multiplexed 160 Gbit/s soliton signals have been successfully transmitted over 200 km for the first time. The soliton source was a 10 GHz regeneratively modelocked fibre laser and a planar lightwave circuit was used for optical multiplexing. The soliton pulse width was ~1.5 ps. A polariser and a nonlinear loop mirror were used for demultiplexing from 160 to 10 Gbit/s     

High performance 10-12.5 Gbit/s modulator driver in InP SHBT technology

A high performance modulator driver circuit is presented using 4" InP SHBT technology. The IC was developed for driving EAM modulators in OC-192 (10 Gbit/s) and with forward error correction (FEC: 10.7 Gbit/s or 12.5 Gbit/s) optical fibre systems. The monolithic integrated circuit features output amplitude control, output crossing point control and output DC offset control. Measured results show the circuit operates at 10 to 12.5 Gbit/s with a swing of 3.1 V/sub p-p/ at each output and 20/18 ps rise/fall times. The power dissipation is 1.4 W with a standard power supply of -5.2 V.     

NTT ultra-fast,large-capacity optical transmission at 400 Gbit/s

By combining optical time-division-multiplexing (TDM) and wavelength division-multiplexing (WDM) with a single super-continuum light source NTT Corp. has successfully conducted an ultra-fast, large-capacity optical transmission experiment at 400 Gbit/s (equivalent to sending 100 years of newspapers in a second) over a distance of 100 km. Having already confirmed that the PLL timing extraction circuit and all optical time-division demultiplexer are able to function at 400 Gbit/s and 200 Gbit/s, respectively, NTT plans to continue R&D efforts to develop an optical transmission system exceeding 1 T bit/s.     

IP网中40 Gbit/s链路需求解决方案

本文阐述了IP网中40 Gbit/s链路需求的背景,介绍了40 Gbit/s关键技术,提出了IP网中40 Gbit/s链路应用解决方案.     

56 Gbit/s analogue PLL for clock recovery

A clock-recovery circuit is reported that employs a phase-locked loop (PLL) at 56.88 Gbit/s, and is demonstrated by locking to a 28.44 GHz sinusoidal signal while two additional circuits with adapted on-chip passive components are locked to 29 and 39 Gbit/s pseudorandom bit sequences. To the knowledge of the authors, this is the first demonstration of an integrated PLL integrated circuit for clock recovery at a data rate well above 40 Gbit/s     

25 Gbit/s decision circuit, 34 Gbit/s multiplexer, and 40 Gbit/s demultiplexer IC in selective epitaxial Si bipolar technology

A 25 Gbit/s decision circuit, a 34 Gbit/s multiplexer, and a 40 Gbit/s demultiplexer IC have been realised with selective epitaxial silicon bipolar technology using 0.8 mu m lithography. The data rates achieved are the highest values reported for these types of circuit in any IC technology.<>     

High-bit-rate pulse regeneration and injection laser modulation using a diode circuit

The push-pull diode circuit investigated regenerates pulse trains near 1 Gbit/s with a power amplification of 8.4 dB. As a particular application, the direct modulation of a laser diode was carried out with this circuit at a bit rate of 1 Gbit/s.     

High-speed GaAs SCFL monolithic integrated decision circuit for Gbit/s optical repeaters

A high-speed GaAs monolithic integrated decision circuit for Gbit/s optical repeaters, based on source coupled FET logic (SCFL) and designed to be completely ECL-compatible, has been developed. A clock phase margin of 150 degrees at 2 Gbit/s and IC yields of about 60% are achieved by using SCFL configuration. The developed IC operates stably from 10 to 60°C ambient temperature over a supply voltage fluctuation of more than 2 V.     

160 Gbit/s full optical time-division demultiplexing using FWM ofSOA-array integrated on PLC

160 Gbit/s full time-division demultiplexing using a semiconductor optical amplifier hybrid integrated demultiplexer on a planar lightwave circuit is demonstrated. Error-free, demultiplexing from a 160 Gbit/s signal to eight-channel, 20 Gbit/s signals is successfully demonstrated     

Scalable 10 Gbit/s 4×20.25 μm CMOS/SIMOX ATM switch LSIcircuit based on distributed contention control

A scalable 10 Gbit/s 4×2 ATM switch LSI circuit has been fabricated. It employs a new distributed contention control technique that makes the LSI circuit expandable. To increase the LSI circuit throughput, 0.2 μm CMOS/SIMOX (separation by implanted oxygen) technology is used. It allows the LSI circuit to offer 221 I/O pins, an operating speed of 1.25 Gbit/s and 7 W power consumption     

Fully monolithic integrated 43 Gbit/s clock and data recoverycircuit in InP HEMT technology

A fully monolithic integrated 43 Gbit/s clock and data recovery circuit for optical fibre communication systems is described. The circuit is based on a phase-locked loop technique, and the input data signal is regenerated with the data-rate clock signal. The circuit was fabricated with 0.1 μm gate-length InAlAs/InGaAs/InP HEMTs, and error-free operation was confirmed for 2³¹-1 PRBS data signal at 43 Gbit/s     

5 V, 10 Gbit/s optical receiver module using Si-bipolar IC

A 10 Gbit/s optical receiver module using a Si-bipolar IC has been developed. For low power and low cost, a pure Si-bipolar IC is used in place of a GaAs IC, which is commonly used for over 10 Gbit/s. To widen the frequency bandwidth, multifeedback techniques and a two-stage buffer configuration are used in the preamplifier IC. In addition, a differential circuit configuration is used for stable operation at high frequency. The IC was fabricated using 0.25 μm Si-bipolar technology. The module exhibits sensitivity of <-16 dBm for 10 Gbit/s data with an input dynamic range >15 dB. Small power consumption of 410 mW is achieved with the single power-supply voltage of +5 V     

超高速单电源GaAs判决再生电路

设计并模拟分析了光纤通信用超高速单电源 Ga As判决再生电路 ,采用非掺 SI Ga As衬底直接离子注入、1μm耗尽型 Ga As MESFET、平面电路工艺研制出单片 Ga As判决再生电路。实验测试结果表明 ,该电路可对输入信号进行正确的“0”、“1”判决 ,并经时钟抽样后 ,输出正确的数字信号 ,传输速率可达 2 .8Gbit/s,可用于覆盖 2 .5Gbit/s系列光通信系统     

Clock recovery for a 5 Gbit/s fibre-optic system

A clock recovery circuit has been constructed using dual-gate MESFETs. From a 5 Gbit/s data stream consisting of 50 time division multiplexed 100 MHz channels, the 100 MHz master clock is recovered both in frequency and in phase. Phase jitter is less than 20 ps in the presence of data and channel noise. A significant advantage of this approach over previous ones is the simplicity in the clock recovery circuitry and in demultiplexing individual channels. This permits easy speed upgrading to beyond 10 Gbit/s.     

40 Gbit/s monolithic integrated modulator driver in InP SHBT technology

A high-speed and high-gain modulator driver circuit is presented using 4-inch InP SHBT technology. The IC was developed for driving EAM modulators in 40 Gbit/s optical fibre systems. The monolithic integrated circuit features output amplitude control and output crossing point control. Measured results show the circuit operates at 40 Gbit/s with a swing of 2.5 V/sub p-p/ at each output and 9/8 ps rise/fall times. The power dissipation is 1.5 W with a standard power supply of -5.2 V.     

80 Gbit/s soliton data transmission over 500 km with unequalamplitude solitons for timing clock extraction

Single-polarisation 80 Gbit/s soliton data signals have been successfully transmitted over 500 km. The soliton source was a modelocked fibre laser and a planar lightwave circuit was used for stable optical multiplexing. A nonlinear loop mirror was used for demultiplexing, in which unequal amplitude solitons were used for clock extraction     

Cell processing LSIs for 2.4 Gbit/s SDH-based ATM transmission system

Introduces cell processing large-scale integrated circuits (LSIs) suitable for byte-oriented systems operating at 2.4 Gbit/s. The LSIs are based on a newly proposed cell delineation circuit which uses a pipeline processing technology to realise byte-by-byte shift operations, an error-detect and error-correct circuit and a descrambling circuit. Prototype LSIs, constructed with a super-selfaligned process technology (SST), are tested at up to 3.7 Gbit/s.<>     

40 Gbit/s lumped-element modulator driver in GaAs pHEMTs

A high-speed and high-gain modulator driver circuit using 0.15 /spl mu/m gate length GaAs pHEMT technology is presented. The IC was developed for driving electroabsorption modulators in 40 Gbit/s optical fibre systems. To meet application requirements a lumped-element approach was used with differential configuration. Measured results show the circuit operates at 40 Gbit/s with a swing of 3 V/sub p-p/ for single-ended and 6 V/sub p-p/ for differential output, and 8/10 ps rise/fall times.