Development of a magnetron-enhanced plasma process for tungstenetchback with response-surface methodology

A two-step etchback process to form tungsten plugs in submicron contacts and vias has been developed. the process uses an Applied Materials Inc., P5000 WCVD magnetron-enhanced, single-wafer system with an experimental design and response-surface methodology. Tungsten is first etched with an Ar/SF₆ mixture until excited N₂ molecules from the underlying TiN adhesion layer are detected in the plasma. Residual TiN is then etched for a fixed time with an Ar/Cl ₂ plasma. Both steps employ a rotating 0.5-Hz magnetic field. Although the use of the magnetic field has no pronounced effect on the etch rate of either film, it provides broad regions of high etch uniformity. In addition, the DC-bias voltage measured as part of the TiN study decreases with increasing magnetic field strength without reducing the etch rate of the film     

Study of etch rate characteristics of SF6/He plasmas byresponse-surface methodology: effects of interelectrode spacing

The characteristics of SF₆/He plasmas which are used to etch Si₃N₄ have been examined with experimental design and modeled empirically by response-surface methodology using a Lam Research Autoetch 480 single-wafer system. The effects of variations of process gas flow rate (20-380 sccm), reactor pressure (300-900 mtorr). RF power (50-450 W at 13.56 MHz), and interelectrode spacing (8-25 mm) on the etch rates of LPCVD (low-pressure chemical vapor deposition) Si₃N₄, thermal SiO₂, and photoresist were examined at 22±2°C. Whereas the etch rate of photoresist increases with interelectrode spacing between 8 and 19 mm and then declines between 19 and 25 mm, the etch rate of Si₃N ₄ increases smoothly from 8 to 25 mm, while the etch rate of thermal SiO₂ shows no dependence on spacing between 8 and 25 mm. The etch rates of all three films decrease with increasing reactor pressure. Contour plots of the response surfaces for etch rate and etch uniformity of Si₃N₄ as a function of spacing and flow rate at constant RF power (250 W) display complex behavior at fixed reactor pressures. A satisfactory balance of etch rate and etch uniformity for Si₃N₄ is predicted at low reactor pressure (~300 mtorr), large electrode spacing (12-25 mm), and moderate process gas flow rates (20-250 sccm)     

Reduction of loading effect by tungsten etchback in a magneticallyenhanced reactive ion etcher

The plug loading effect occurring during the etchback of tungsten was investigated in a magnetically enhanced reactive ion etcher using SF ₆/Ar mixtures. It was found that while the plug loading effect is independent of varying SF₆/Ar flow rate ratio and magnetic field intensity, it is reduced under the condition of high selectivity of tungsten relative to TiN which was achieved at high chamber pressure and low RF power. It is proposed that when TiN is used as a glue layer, the W etch rate enhancement in the plug is mainly controlled by a local loading effect. Under the optimized etchback conditions the plug loss was successfully controlled without the tungsten residue left on severe topology     

Reactor characterization for a process to etchSi3N4 formed on thin SiO2

A plasma etching process for patterning LPCVD (low-pressure chemical vapor deposition) Si₃N₄ which has been formed on thin thermally grown SiO₂ has been developed and characterized with an Applied Materials 8110 batch system using 100-mm-diameter silicon wafers. To fulfill the primary process objectives of minimal critical dimension (CD) loss (~0.08 μm), vertical profiles after etch, retention of some of the underlying thermal SiO₂, and batch etch uniformity, the reactor has been characterized by evaluating the effects of variation of reactor pressure (15 to 65 mTorr), O₂ concentration by flow rate (30 to 70%) of an O₂/CHF₂ mixture, and DC bias voltage (-200 to -550 V). Analysis of the resulting etch rate, etch uniformity, dimensional, and profile data suggests that satisfactory processing may be achieved at low reactor pressure (~25 mTorr), 50-60% O₂ by flow rate in O₂/CHF₃, and low DC bias (-200 to -250 V)     

氮化硅的ECCP刻蚀特性研究

本文对氮化硅的增强电容耦合等离子刻蚀进行研究,为氮化硅刻蚀工艺的优化提供参考。针对SF_6+O_2气体体系,通过设计实验考察了功率、压强、气体比、氦气等对刻蚀速率和均一性的影响,并对结果进行机理分析和讨论。实验结果表明:功率越大,刻蚀速率越大,与源极射频电力相比,偏置射频电力对刻蚀速率的影响更为显著;压强增大,刻蚀速率增大,但压强增大到一定程度后,刻蚀速率基本不变,刻蚀均匀性随着压强增大而变差;在保证SF_6/O_2总流量保持不变下,O_2的比例增大,刻蚀速率先增大后减小,刻蚀均匀性逐步变好;He的添加可以改善刻蚀均匀性,但He的添加量过多时,会造成刻蚀速率降低。     

Statistical experimental design in plasma etch modeling

The objective of this work is to obtain a comprehensive set of empirical models for plasma etch rates, uniformity, selectivity, and anisotropy. These models accurately represent the behavior of a specific piece of equipment under a wide range of etch recipes, thus making them ideal for manufacturing and diagnostic purposes. The response characteristics of a CCl₄-based plasma process used to etch doped polysilicon were examined via a 2^6-1 fractional factorial experiment followed by a Box-Wilson design. The effects of variation in RF power, pressure, electrode spacing, CCl₄ flow, He flow and O₂ flow on several output variables, including etch rate, selectivity, and process uniformity, were investigated. Etch anisotropy was also measured by scanning electron microscopy analysis on a 2^6-2 fraction of the original experiment. The screening factorial experiment was designed to isolate the most significant input parameters. Using this information as a platform from which to proceed, the subsequent phase of the experiment allowed the development of empirical models of etch behavior using response surface methodology (G. E. P. Box and N. D. Draper, 1987). The models were subsequently used to optimize the etch process     

Influence of SiH4 on the WNx-PECVD process

Silane was added to an existing WN_x PECVD process in different flow ratios to the WF₆, to obtain higher thermal stability of the barrier in comparison to the WN_x. The deposition rate rises drastically with increased SiH₄/WF₆ ratios. The ternary compositions were investigated with regard to the sheet resistance and thickness. The X-ray diffraction (XRD) measurements of selected layers with low electrical resistivities in the as-deposited state show a broad amorphous peak like the WN_x barrier, indicating an amorphous structure. After characterising the as-deposited state of these samples, thermal treatments of the layers were performed at temperature of 600 °C for 1 h in vacuum.     

Development of an etchant for selectively etching TiWNxin the presence of electroplated 95%Pb-5%Sn solder

Shrinking die sizes and increasing I/O density is motivating the push toward flip chip packages. A flip chip interconnection system with a under bump metallurgy stack containing sputtered TiWN_X/sputtered Cu/electroplated Cu stud/electroplated 95%Pb-5%Sn was developed. An important step in the above process is the selective etching of the sputtered Cu bus layer and the TiWN_X barrier layer, in the presence of the Pb-Sn solder. The Cu bus layer was selectively etched using commercial etchants. However, no commercial etchants were available for selectively etching the TiWN_X layer, H₂O₂-NH₄OH based etching systems, popularly known as Standard Clean-1 cleaning solutions, have been extensively used to clean silicon wafers in front end wafer fabrication where only trace metal contamination exists. Since metals like lead, copper, titanium, tin and tungsten catalyze the heterogeneous decomposition of the peroxide, the unstable H₂O₂-NH₄OH based etching systems are rarely used to etch metal films. In this paper the development of a H ₂O₂-NH₄OH based etchant to selectively etch the sputtered TiWN_X films in the presence of electroplated 95%Pb-5%Sn solder bumps is discussed. A 2³ full factorial experiment with mid point was conducted to establish the etchant composition, as well as process temperature, that give satisfactory responses with respect to etch time, permissable undercut of the Cu stud (caused by the NH₄OH), and acceptable bump shape after reflow. Statistical analysis was used to understand the significant factors influencing the etch rate and undercut. An etchant containing 6% by volume of 30%-H₂O₂ and 0.75% by volume of 30%-NH₄OH operated at a temperature of 37°C was found to give satisfactory results     

Development of a TiW plasma etch process using a mixture experimentand response surface optimization

The characteristics of SF₆/He plasmas used to etch TiW have been studied with statistically designed experiments using a Tegal 804 single wafer system. Two processes were developed using both positive and negative photoresist as the mask material for etching TiW. The goal was to consolidate both processes into one. A two-phase experimental approach was taken to generate the processes. In phase 1 a fractional factorial screening experiment was used to identify key factors, and in phase 2 a mixture experiment was used for process optimization. The fractional factorial experiment was initially used to study the effects of reactor pressure, RF power, SF₆/He gas ratio, overetch time, and hard bake. The results of this initial experiment were used to identify the appropriate levels for the main process parameters. Then, at these parameter levels, a mixture experiment was conducted using the partial pressures of SF₆, He, and the nitrogen ballast as the design variables. Since the total pressure in the system is fixed, these three variables are the components of a mixture, and thus form a constrained design space for the experiment. Quadratic and special cubic response surface models were generated for the following responses: TiW etch rate, photoresist etch-rate, selectivity between the TiW and photoresist, uniformity of all etch rates and selectivities, and critical dimension control for the photoresist and TiW. Contour plots for all responses as a function of the partial pressure of SF₆, He, and nitrogen ballast were generated. The contours from these empirical models were analyzed jointly to optimize the processes     

Characterization of Via Etching in CHF3/CF4 Magnetically Enhanced Reactive Ion Etching Using Neural Networks

This study characterizes an oxide etching process in a magnetically enhanced reactive ion etching (MERIE) reactor with a CHF3/CF4 gas chemistry. We use a statistical 2^4‐1 experimental design plus one center point to characterize the relationships between the process factors and etch responses. The factors that we varied in the design include RF power, pressure, and gas composition, and the modeled etch responses were the etch rate, etch selectivity to TiN, and uniformity. The developed models produced 3D response plots. Etching of SiO₂ mainly depends on F density and ion bombardment. SiO₂ etch selectivity to TiN sensitively depends on the F density in the plasma and the effects of ion bombardment. The process conditions for a high etch selectivity are a 0.3 to 0.5 CF₄ flow ratio and a –600 V to –650 V DC bias voltage according to the process pressure in our experiment. Etching uniformity was improved with an increase in the CF4 flow ratio in the gas mixture, an increase in the source power, and a higher pressure. Our characterization of via etching in a CHF₃/CF₄ MERIE using neural networks was successful, economical, and effective. The results provide highly valuable information about etching mechanisms and optimum etching conditions.     

A simple process to produce a high quality silicon surface prior toselective epitaxial growth

A simple and low-cost process was devised to eliminate etch damage resulting from oxide etching on the seed-hole surface prior to selective epitaxial growth (SEG) of silicon. The process consists of a low power C ₂F₆ RIE step which was performed right after the oxide etch step in the same etch reactor. The use of this step excluded the need of a conventional sacrificial oxide to remove damaged silicon regions and residual polymers. The n-p diodes resulting from n-type SEG grown on p-type substrate were used to evaluate the quality of the silicon surface prior to SEG     

Modeling of a high throughput hot-wall reactor for selectiveepitaxial growth of silicon

A tubular hot-wall silicon epitaxial reactor operated in the selective deposition regime is characterized for growth rate uniformity in both the radial and longitudinal directions. The range of experimental conditions includes temperatures from 900°C to 800°C, pressures from 1 torr to 0.4 torr, concentrations of SiH₂Cl₂ in H₂ from 17% to 4%, and wafer diameters from 125 mm to 75 mm. The simplest possible models that accurately predict these data are formulated. The resulting simulator is used to demonstrate improvements to the existing hot-wall reactor, and to propose a design for a scaled up production-sized hot-wall reactor     

Temperature effects on tungsten etching

The influence of the substrate temperature (from T_s = +20°C to T_s = −45°C) on the etching characteristics (etch rate and anisotropy) of tungsten material has been investigated using a surface-wave sustained magnetoplasma reactor operated with SF₆. By correlating the F-atom concentration and the ion current density to the etching characteristics, we found that ion-assisted etching becomes more important than spontaneous chemical etching as the substrate temperature and SF₆ gas pressure decrease, ensuring, in absence of external biasing, high etching anisotropy together with high microscopic uniformity for submicrometer features (0.2 to 1 μm). Our results reveal the competitive influence between substrate temperature (which inhibits spontaneous chemical reaction as it is lowered) and gas pressure (which favours spontaneous chemical reaction as it is increased). Obtaining high anisotropy requires, in the present case, a substrate temperature of T_s = −20°C for P = 0.5 mTorr and a temperature as low as T_s = −35°C for P = 1.5 mTorr.     

Planar AlGaAs/GaAs heterojunction bipolar transistors fabricatedusing selective W-CVD

The authors describe a planar process for the AlGaAs/GaAs HBTs in which collector vias are buried selectively, even to the base layers, with chemical vapor deposited tungsten (CVD-W) films. By using WF₆ /SiH₄ chemistry, W could be deposited on Pt films, which were overlapped 50 nm thick on the AuGe-based collector electrodes, without depositing W on the surrounding SiO₂ layers. Current gains of planar HBTs with 3.5-μm×3.5-μm emitters were up to 150, for a collector current density of about 2.5×10⁴ A/cm²     

Effects of controlled texturization of the crystalline Si surfaceon the SiO2/Si effective barrier height

A two-stage plasma etch texturination process to control the level of crystalline silicon surface roughness has been investigated. Initially, a Cl₂ plasma etch is used to produce a very rough Si surface. This is followed by an isotropic SF₆ plasma etch, whose etch time is used to reduce and control the level of surface roughness created by the previous step. Oxides grown on texturized Si surfaces with short SF₆ etch times exhibit lower effective SiO₂/Si barrier height and greater electron injection enhancement than those with longer SF₆ etch times     

Modeling magnetically enhanced RIE of aluminum alloy films usingneural networks

Aluminum (Al) and its alloy films are widely used for fabricating VLSI interconnections. The discharge behavior of a magnetically enhanced reactive ion etching (MERIE) of Al(Si) has been modeled using neural networks. A 2^6-1 fractional factorial experiment was employed to characterize etch variations with RF power, pressure, magnetic field and gas mixtures of Cl₂, BCl₃, and N₂. Responses of an Al(Si) film etched in a chlorine-based plasma include etch rate, selectivity to oxide, anisotropy and bias of critical dimension (CD). The generalization accuracy of the models, measured by the root-mean squared error (RMS) on a test set, are 285 Å/min for etch rate, 5.58 for oxide selectivity, 0.08 for anisotropy, and 3.82 Å/min for CD bias. Al(Si) etch rate was found to be chlorine-dependent with significantly affected by magnetic field variations. For the other etch responses, RF power was dominant. Gas additives such as BCl₃ and N₂ were seen to have conflicting effects on etch outputs. Predicted Al(Si) etch behaviors from neural process models were in qualitative good agreement with reported experimental results     

ECCP干法刻蚀条件下的TFT基板绝缘层过孔腐蚀的改善

过孔搭接失效一直是TFT-LCD行业中重点改善的不良之一。为了解决该不良,本文分析了不同刻蚀模式(ICP和ECCP)对过孔形貌的影响,利用四因子法研究ECCP模式刻蚀参数(压力、偏置/源极射频功率及O_2/SF_6气体比例)对刻蚀速率和均一性的影响,并得出ECCP过孔改善的最佳刻蚀参数。结果表明:ECCP模式下,氮化硅刻蚀过程中物理轰击对GI截面的下沿与Cu接触区域形成损伤后产生的缺陷,是诱发过孔腐蚀的主要因素,ICP模式无腐蚀。反应腔压力增大刻蚀速率增大,均一性下降;偏置射频功率增大,速率增大,均一性提高;源极射频功率增大,速率变化小,均一性下降;O_2/SF_6气体比例对速率影响小,O_2含量越高,均一性越高。为达到PR胶保护GI下沿截面的目的,反应压力增大到1.7Pa,偏置射频功率减小到30kW,源极功率增加到30kW,O_2/SF_6气体保持比例1∶1后,增加了氮化硅的刻蚀量,减小PR胶的内缩量,避免物理溅射表面损伤;同时刻蚀速率达到750nm/s,均一性达到10%,腐蚀发生率为10%～0,使ECCP刻蚀模式对过孔的腐蚀影响得到有效解决。     

Interface characteristics of selective tungsten on silicon using anew pretreatment technology for ULSI application

The characteristics of selective tungsten film on silicon strongly depend on the surface properties of the underlying substrate. In this work, a new pretreatment process prior to selective tungsten film deposition has been developed. A CF₄/O₂ mixed plasma modification procedure and a subsequent O₂ plasma ashing step combine to achieve efficient surface precleaning. The damage and contamination induced by reactive ion etching (RIE) are thus eliminated. Concurrently, a subsequent anhydrous HF cleaning was used to remove the native oxide on silicon as well as to obtain a fluorine-passivated silicon surface which can avoid reoxidation during the transport of wafers. This new pretreatment technology produces tungsten films that retain superior physical properties within the aspects of deposition rate, film morphology, and selectivity. Also, excellent interface characteristics with low silicon consumption, low contact resistance, low contact leakage current, and fewer impurities of fluorine, oxygen, and carbon within the interfacial region are obtained     

Good High-Temperature Stability of TiN/ Al2O3/WN/TiN Capacitors

For the first time, good thermal stability up to an annealing temperature of 1000degC has been demonstrated for a new TiN/Al₂O₃/WN/TiN capacitor structure. Good electrical performance has been achieved for the proposed layer structure, including a high dielectric constant of ~ 10, low leakage current of 1.2times10^-7 A/cm² at 1 V, and excellent reliability. A thin WN layer was incorporated into the metal-insulator-metal capacitor between the bottom TiN electrode and the Al₂O₃ dielectric suppressing of interfacial-layer formation at Al₂ O₃/TiN interfaces and resulting in a smoother Al₂O₃/TiN interface. This new layer structure is very attractive for deep-trench capacitor applications in DRAM technologies beyond 50 nm.     

Dielectric deposition process for Cu/SiO2 integration in a dual damascene interconnection architecture

A challenge to integrate Cu in device interconnections is to avoid Cu diffusion into silicon active zone that could seriously damage device performance, and into interlevel dielectric that could induce shorts or degrade dielectric performance. This paper relates the integration of Cu-CVD with SiO₂. Structures studied are SiO₂ deposited on Cu-CVD, and SiO₂/SiN/Cu structure: a thin SiN layer is deposited on Cu before SiO₂ to act as diffusion barrier and as an etch stop during the interconnect structure patterning. Both SiO₂ and SiN dielectric processes are made in plasma-enhanced chemical vapor deposition processes, from SiH₄ precursor with addition of, respectively, N₂O or NH₃. Cu contamination is shown to occur during the dielectric deposition onto Cu, and is enhanced by the fluorine presence in the deposition chamber. Deposition processes were evaluated in order to lower Cu contamination in the dielectric bulk. On an other hand, a noticeable degradation in Cu layer resistance was evidenced after dielectric deposition due to copper contamination during the dielectric deposition process. This issue can be addressed by the optimization of the dielectric deposition process.