A CMOS logarithmic IF amplifier with unbalanced source-coupledpairs

A CMOS logarithmic intermediate-frequency (IF) amplifier that is applied to mobile telecommunications equipment is presented. The CMOS logarithmic IF amplifier has pseudologarithmic rectifiers made from parallel-connecting full-wave rectifiers, consisting of unbalanced source-coupled pairs with the cross-coupled input stage and parallel-connected output stage. A ±3-dB logarithmic accuracy, a 90-dB input dynamic range, and a -30 to 80°C operating temperature range were achieved with the 1.3-μm double-polysilicon n-well CMOS process. Typical power consumption by the logarithmic IF amplifier in the fabricated CMOS LSI was 5.5 mW. The block area for the logarithmic IF amplifier was 0.8 mm²     

CMOS RF power amplifier with reconfigurable transformer

A CMOS RF power amplifier that can change the output transformer ratio is presented. The CMOS power amplifier is fully integrated in a 0.13 /spl mu/m process and has a power added efficiency (PAE) of 38% at 2.1 GHz and an output power of 30.7 dBm with 3.0 V supply voltage. The PAE at an output power of 16 dBm was increased by 40% by altering the transformer ratio.     

Large-swing CMOS buffer amplifier

A circuit configuration for a CMOS buffer amplifier is described. The circuit, which is an enhancement of a previously reported buffer amplifier, features a large output voltage swing and a well-controlled quiescent current. A buffer amplifier of this type has been implemented in a 1.5-μm CMOS technology. The prototype occupies an area of 275 mil². It works with a 5-V supply and can drive more than 4.2 V (peak to peak) in to 300 Ω with a total harmonic distortion of less than 0.025%     

ISO 14443单芯片读卡机发射电路的设计

介绍一种新的CMOS功率放大电路,该电路既有开关型放大器的高效率的特点,同时又具备线性功率放大电路能输出可变包络的特点,而且可以根据实际需要对输出功率进行调节。电路在0.6μm工艺线上流片。经测试验证电路能在-20°C～80°C的温度范围内工作,工作电压范围为2.5V～5.5V,输出功率可在很大范围内进行调节,在5V条件下,最大输出功率可达6.25W。     

Tournament-Shaped Magnetically Coupled Power-Combiner Architecture for RF CMOS Power Amplifier

A tournament-shaped magnetically coupled power-combiner architecture for a fully integrated RF CMOS power amplifier is proposed. Various 1 : 1 transmission line transformers are used to design the power combiner. To demonstrate the new architecture, a 1.81-GHz CMOS power amplifier using the tournament-shaped power combiner was implemented with a 0.18-mum RF CMOS process. All of the matching components, including the input and output transformer, were fully integrated. The amplifier achieved a drain efficiency of 38% at the maximum output power of 31.7 dBm.     

High‐Efficiency CMOS Power Amplifier Using Uneven Bias for Wireless LAN Application

This paper proposes a high‐efficiency power amplifier (PA) with uneven bias. The proposed amplifier consists of a driver amplifier, power stages of the main amplifier with class AB bias, and an auxiliary amplifier with class C bias. Unlike other CMOS PAs, the amplifier adopts a current‐mode transformer‐based combiner to reduce the output stage loss and size. As a result, the amplifier can improve the efficiency and reduce the quiescent current. The fully integrated CMOS PA is implemented using the commercial Taiwan Semiconductor Manufacturing Company 0.18‐μm RF‐CMOS process with a supply voltage of 3.3 V. The measured gain, P_1dB, and efficiency at P_1dB are 29 dB, 28.1 dBm, and 37.9%, respectively. When the PA is tested with 54 Mbps of an 802.11g WLAN orthogonal frequency division multiplexing signal, a 25‐dB error vector magnitude compliant output power of 22 dBm and a 21.5% efficiency can be obtained.     

1.95GHz Doherty功率放大器设计

基于SMIC 0.18 μm RF CMOS工艺,设计了一款1.95 GHz的Doherty功率放大器.为了保持两路功放相位最大一致性,主功放(PA1)和辅功放(PA2)采用了同一种CMOS功率放大器,仅改变其偏压使其工作在不同模式.CMOS功率放大器为工作于AB类的两级放大电路,集成了输入和级间匹配网络;功分器以及λ...     

A 1.5-V high drive capability CMOS op-amp

A novel CMOS operational amplifier with a 1.5 V power supply is presented. It is based on a folded-mirror transconductance amplifier and a high-efficiency output stage. The amplifier achieves an open-loop gain and a gain-bandwidth product higher than 65 dB and 1 MHz, respectively. In addition, a 1 V peak-to-peak output voltage into a 500 Ω and 50 pF output load is provided with a total harmonic distortion of -77 dB. This performance was achieved using maximum aspect ratios of 120/1.2 and 360/1.2 for the NMOS and PMOS transistors, respectively, and a quiescent current as low as 60 μA for the driver transistors. The amplifier was implemented in a standard 1.2 μm CMOS process with threshold voltages around 0.8 V. It dissipates less than 300 μW     

Design and optimization of CMOS RF power amplifiers

A CMOS radio-frequency power amplifier including on-chip matching networks has been designed in a 0.6-μm n-well triple-metal digital CMOS process, and optimized using a simulated-annealing-based custom computer-aided design tool. A compact inductor model enables the incorporation of parasitics as an integral part of the parasitic-aware design and CAD optimization; low-Q metal3 spiral inductors are used in the input and output matching networks. A 3-V 85-mW balanced fully integrated Class-C power amplifier with a measured drain efficiency of 55% at 900 MHz has been designed, optimized, integrated, and tested     

A New CMOS Buffer Amplifier Design Used in Low Voltage MEMS Interface Circuits

To achieve low voltage high drivingcapability with quiescent current control, a class-AB CMOS buffer amplifier usingimproved quasi-complementary output stage and error amplifiers with adaptive loadsis developed. Improved quasi-complementary output stage enables it more suitablefor low voltage applications, while adaptive load in error amplifier is used toincrease the driving capability and reduce the sensitivity of the quiescentcurrent to fabrication process variation. The circuit has been fabricated in 0.8μm CMOS process. With 300 Ω load in a ±1.5 V supply, its outputswing is 2.42 V. The mean value of quiescent current for eight samples is 204μA, with the worst deviation of 17%.     

Broadband amplification in CMOS technology using cascadedsingle-stage distributed amplifier

Feasibility of the cascaded single-stage distributed amplifier (CSDA) for ultra broadband amplification in complementary metal-oxide-semiconductor (CMOS) technology is investigated. A number of unique benefits gained from the CMOS CSDA over the conventional CMOS distributed amplifier structure are highlighted along with bandwidth analysis and helpful consideration. Simulated in the standard digital 0.35 μm CMOS process with realistic parasitic models, a prototype design of a four-stage CMOS CSDA provides 21 dB power gain at 5 GHz bandwidth, better than -10 dB input/output return loss and dissipates < 132 mW     

Kink效应对低温CMOS读出电路的影响

在深低温下(T<50K)，CMOS器件会出现Kink效应，即I-V特性曲线会发生扭曲。当漏源电压较大时(Vds＞4V)，漏电流突然加大，电流曲线偏离正常的平方关系。本文通过实验表明，Kink效应对CMOS读出电路中的一些电路结构产生较严重的影响，Kink效应会导致源跟随器输出产生严重的非线性；对于共源放大器和两级运放，Kink效应会使其增益产生非线性。最后，针对影响低温读出电路性能的Kink效应进行分析和研究，提出在低温CMOS读出集成电路设计中如何解决这些问题的方案。     

Area-Efficient 60 GHz +18.9 dBm Power Amplifier with On-Chip Four-Way Parallel Power Combiner in 65-nm CMOS

This paper presents a compact 60-GHz power amplifier utilizing a four-way on-chip parallel power combiner and splitter. The proposed topology provides the capability of combining the output power of four individual power amplifier cores in a compact die area. Each power amplifier core consists of a three-stage common-source amplifier with transformer-coupled impedance matching networks. Fabricated in 65-nm CMOS process, the measured gain of the 0.19-mm² power amplifier at 60 GHz is 18.8 and 15 dB utilizing 1.4 and 1.0 V supply. Three-decibel band width of 4 GHz and P_1dB of 16.9 dBm is measured while consuming 424 mW from a 1.4-V supply. A maximum saturated output power of 18.3 dBm is measured with the 15.9% peak power added efficiency at 60 GHz. The measured insertion loss is 1.9 dB at 60 GHz. The proposed power amplifier achieves the highest power density (power/area) compared to the reported 60-GHz CMOS power amplifiers in 65 nm or older CMOS technologies.     

A 1.75-GHz polar modulated CMOS RF power amplifier for GSM-EDGE

This work presents a fully integrated linearized CMOS RF amplifier, integrated in a 0.18-/spl mu/m CMOS process. The amplifier is implemented on a single chip, requiring no external matching or tuning networks. Peak output power is 27 dBm with a power-added efficiency (PAE) of 34%. The amplitude modulator, implemented on the same chip as the RF amplifier, modulates the supply voltage of the RF amplifier. This results in a power efficient amplification of nonconstant envelope RF signals. The RF power amplifier and amplitude modulator are optimized for the amplification of EDGE signals. The EDGE spectral mask and EVM requirements are met over a wide power range. The maximum EDGE output power is 23.8 dBm and meets the class E3 power requirement of 22 dBm. The corresponding output spectrum at 400 and 600 kHz frequency offset is -59 dB and -70 dB. The EVM has an RMS value of 1.60% and a peak value of 5.87%.     

Transformer-coupled cascode stage for mm-wave power amplifiers in sub-μm CMOS technology

An amplifier topology based on a transformer-coupled cascode stage is presented and compared with the most used solutions for sub-μm CMOS power amplifiers, which are the common-source stage, cascode stage, and capacitive-coupled cascode stage. The comparison was carried out by designing each amplifier in a 65-nm CMOS technology and for a 60-GHz operating frequency. The design was optimized for a trade off among power gain, saturated output power, and linearity. Operating from a 1.2-V supply voltage, the proposed amplifier improves both small-signal and large-signal performance with respect to the most common approaches, thus demonstrating effectiveness with sub-μm CMOS technologies and mm-wave operation.     

A 700-MHz 1-W fully differential CMOS class-E power amplifier

A 700-MHz fully differential class-E CMOS power amplifier for wireless applications has been built toward maximum efficiency. The prototype can deliver 1 W of output power in a 50-Ω output impedance. The maximum power-added efficiency (PAE) is measured to be 62%. The obtained efficiency and output power is compared with the class-E amplifiers theory     

A 1.9-GHz Triple-Mode Class-E Power Amplifier for a Polar Transmitter

A 1.9-GHz CMOS power amplifier for polar transmitters was implemented with a 0.25-mum radio frequency CMOS process. All the matching components, including the input and output transformers, were fully integrated. The concepts of mode locking and adaptive load were applied in order to increase the efficiency and dynamic range of the amplifier. The amplifier achieved a drain efficiency of 33% at a maximum output power of 28dBm. The measured dynamic range was 34dB for a supply voltage that ranged from 0.7 to 3.3V. The measured improvement of the low power efficiency was 140% at an output power of 16dBm     

A Novel Linearization Method of CMOS Drive Amplifier Using IMD Canceller

A novel linearization method for CMOS drive amplifier using intermodulation distortion (IMD) canceller is presented. The IMD cancellation method is composed of a cascode main amplifier and a common-source IMD canceller. The additional common-source amplifier generates IMD3 signals with 180deg phase difference against the IMD3 of the cascode main amplifier. The linear drive amplifier is designed and fabricated by CMOS 0.18 mum process. The output IP₃ of +13 dBm is achieved with the power gain of +11.6 dB, the output P_{1 dB} of + 5.5 dBm, and the power-added efficiency of 21%.     

应用于GPS接收机的宽带低噪声放大器

本文介绍了一种适用于GPS接收机的CMOS宽带低噪声放大器,带宽设计在1．16Hz-1．7GHz。采用源极电感负反馈结构,并在输入端加入了宽带匹配网络来扩展带宽,放大器提供30dB的增益,使用了两级放大,第二级采用了电流复用技术来节省功耗,最后一级使用了源极跟随器,用来阻抗匹配。采用TSMC55nmCMOS工艺,仿真结果表明,噪声系数小于1．3dB,S21大于29dB,S11小于-10dB,1．2V电源供电下功耗为20mW。     

Fully Integrated CMOS Power Amplifier With Efficiency Enhancement at Power Back-Off

This paper presents a new approach for power amplifier design using deep submicron CMOS technologies. A transformer based voltage combiner is proposed to combine power generated from several low-voltage CMOS amplifiers. Unlike other voltage combining transformers, the architecture presented in this paper provides greater flexibility to access and control the individual amplifiers in a voltage combined amplifier. In this work, this voltage combining transformer has been utilized to control output power and improve average efficiency at power back-off. This technique does not degrade instantaneous efficiency at peak power and maintains voltage gain with power back-off. A 1.2 V, 2.4 GHz fully integrated CMOS power amplifier prototype was implemented with thin-oxide transistors in a 0.13 mum RF-CMOS process to demonstrate the concept. Neither off-chip components nor bondwires are used for output matching. The power amplifier transmits 24 dBm power with 25% drain efficiency at 1 dB compression point. When driven into saturation, it transmits 27 dBm peak power with 32% drain efficiency. At power back-off, efficiency is greatly improved in the prototype which employs average efficiency enhancement circuitry.