A divided/shared bit-line sensing scheme for ULSI DRAM cores

A new dynamic RAM (DRAM) signal sensing principle, a divided/shared bit-line (DSB) sensing scheme, is proposed. This sensing scheme provides folded bit-line sensing operation in a crosspoint-type memory cell array. The DSB scheme offers a high-density DRAM memory core with the common-mode array noise eliminated. A bit-line architecture based on this new sensing principle and its operation are demonstrated. A divided/pausing bit-line sensing (DIPS) scheme, which is an application of this DSB principle to the conventional folded bit-line type of memory cell arrangement, is also proposed. The DIPS architecture achieves complete pausing states for alternate bit lines throughout the active period. These alternate pausing bit lines shield the inter-bit-line coupling noise between active bit lines. Here the inter-bit-line coupling noise is eliminated by a slight architectural change to the conventional folded bit-line memory cell array. These new memory core design alternatives provide high-density DRAM memory cores suitable for the 64-Mb level and beyond. with the memory array noise reduced significantly     

A 30-ns 64-Mb DRAM with built-in self-test and self-repair function

A 64-Mb dynamic random access memory (DRAM) with a 30-ns access time and 19.48-mm×9.55-mm die size has been developed. For reducing inter-bit-line coupling noise, the DRAM features a latched-sense, shared-sense circuit with open bit-line readout and folded bit-line rewrite operations. To reduce test costs and increase chip reliability, it has been equipped with built-in self-test and self-repair (BIST and BISR) circuits that use spare SRAM cells     

Low power dynamic circuit for power efficient bit lines

In this paper, a low power dynamic circuit is presented to reduce the power consumption of bit lines in multi-port memories. Using the proposed circuit, the voltage swing of the pull-down network is lowered to reduce the power consumption of wide fan-in gates employed in memory’s bit lines. Wide fan-in OR gates are designed and simulated using the proposed dynamic circuit in 90 nm CMOS technology. Simulation results show at least 40% reduction of power consumption and 1.2X noise immunity improvement compared to the conventional dynamic circuits at the same delay. Exploiting the proposed dynamic circuit, wide fan-in multiplexers are also designed. The multiplexers are simulated using a 90 nm CMOS model in all process corners. The results show 41% power reduction and 27% speed improvement for the proposed 128-input multiplexer in comparison with the conventional multiplexer at the same noise immunity.     

A high-density dual-port memory cell operation and arrayarchitecture for ULSI DRAMs

A high-density dual-port DRAM architecture is proposed. It realizes a two-transistor/one-capacitor (2Tr-1C) dual-port memory cell array with immunity against the array noise caused by the dual-port operation. This architecture, called a truly dual-port (TDP) DRAM, adopts the previously proposed divided/shared bit-line (DSB) sensing scheme in a dual-port 2Tr-1C DRAM array. A 2Tr-1C dual-port memory cell array with folded bit-line sensing operation, which does not increase the number of bit lines of the 1Tr-1C folded bit-line memory array, is realized, thus reducing the memory cell size. This architecture offers a solution to the fundamental limitations in the 2Tr-1C dual-port memory cell, and it is easily applicable to dual-port memory cores in ASIC environments. An analysis of the memory array noise in various dual-port architectures shows a significant improvement with this architecture. Applications to the complete pipelining operation of a DRAM array and a refresh-free DRAM core are also discussed     

Novel reduced-size coplanar-waveguide bandpass filter using the new folded open stub structure

Proposes a novel folded skill and a simpler method than that of older methods. The advantages of this new structure reveals a better skirt factor than that of the conventional folded /spl lambda//4 series open stub, and it reduces the folded area of the conventional structure by at least 50%. Besides, by using the new folded /spl lambda//4 open stub to realize a bandpass filter, the size of the circuit will be reduced greatly and achieve better stopband rejection.     

A low-impedance open-bitline array for multigigabit DRAM

The noise-generating mechanisms inherent in the open-bitline DRAM array using the 6F² (F: feature size) memory cells and techniques for reducing the noise are described. The sources of differential noise coupled to the paired bitlines laid out in two arrays are the p-well, cell plate, and the group of nonselected wordlines. It was found, by simulation and by experiment with a 0.13-μm 256-Mb test chip, that the level of noise is dramatically reduced by using a low-impedance array with careful layout featuring low-resistivity materials, tight bridging between pairs of adjacent arrays, and a small array, achieving a comparable level of noise to that seen in the twisted and folded-bitline array. On basis of these results, it turns out that the open-bitline array has a strong chance of revival in the multigigabit generation, as long as these noise reduction techniques are applied     

A 0.25-/spl mu/m 3.0-V 1T1C 32-Mb nonvolatile ferroelectric RAM with address transition detector and current forcing latch sense amplifier scheme

Nonvolatile 32-Mb ferroelectric random access memory (FRAM) with-a 0.25-/spl mu/m design rule was developed by using an address transition detector (ATD) control scheme for the application to SRAM and applying a common plate folded bit-line cell scheme with current forcing latch sense amplifier (CFLSA) for increasing sensing margin, and adopting a dual bit-line reference voltage generator (DBRVG) for high noise immunity. Compared to a conventional FRAM device, the total chip size is reduced by 10.87%, which was achieved by using a single section data line (SSDL) and removing large gate-oxide capacitors, which is typically used for reference voltage generator for 1T1C FRAM. Furthermore, the imbalance of reference bit-line capacitance and main bit-line capacitance was resolved by using the CFLSA technique.     

SQUID arrays for simultaneous magnetic measurements: calibrationand source localization performance

Recently developed small arrays of SQUID- (superconducting quantum interference device) based magnetic sensors can, if appropriately placed, locate the position of a confined biomagnetic source without moving the array. A technique is presented having a relative accuracy of about 2% for calibrating such sensors having detection coils with the geometry of a second-order gradiometer. The effects of calibration error and magnetic noise on the accuracy of locating an equivalent current dipole source in the human brain are investigated for five- and seven-sensor probes and for a pair of seven-sensor probes. With a noise level of 5% of peak signal, uncertainties of about 20% in source strength and depth for a five-sensor probe are reduced to 8% for a pair of seven-sensor probes, and uncertainties of about 15 mm in lateral position are reduced to 1 mm for the configuration considered     

A 32-Mb chain FeRAM with segment/stitch array architecture

This paper demonstrates the 32-Mb chain ferroelectric RAM (chain FeRAM) with 0.2-/spl mu/m three-metal CMOS technology. A small die size of 96 mm/sup 2/ and a high cell/chip area efficiency of 65.6% are realized not only by the small cell size using capacitor-on-plug technology but also by two key techniques that utilize the three-metal process: 1) a compact memory cell block structure that eliminates plateline area and reduces block selector area and 2) the segment/stitch array architecture which reduces the area of row decoders and plate drivers. As a result, the average cell size shrinks to 1.875 /spl mu/m/sup 2/, which is smaller than a 0.13-/spl mu/m SRAM cell, and the chip size is reduced to 70% of the chain FeRAM of conventional configuration with two-metal process. Moreover, a power-on/off sequence suitable to the chain FeRAM is introduced to protect the memory cell data from the startup noise. Compatibility with low-power SRAM is a key issue for mobile applications. The low-standby-current bias generator is introduced and the standby current of the chip is suppressed to 3 /spl mu/A. The modified address access mode is also adopted to eliminate the need of intentional address transition after the startup of the chip. The chip enable access time was 50 ns and cycle time was 75 ns at 3.0-V V/sub dd/.     

Crosstalk-insensitive via-programming ROMs using content-aware design framework

Various code patterns of a via-programming read only memory (ROM) cause significant fluctuations in coupling noise between bitlines (BLs). This crosstalk between BLs leads to read failure in high-speed via-programmable ROMs and limits the coverage of applicable code patterns. This work presents a content-aware design framework (CADF) for via-programming ROMs to overcome the crosstalk induced read failure. The CADF ROMs employ a content-aware structure and correspondent code-structure programming algorithm to reduce the amount of coupling noise source while maintaining nonminimal BL load for crosstalk reduction. A 256-Kb conventional ROM and a 256-Kb CADF ROM were fabricated using a 0.25-/spl mu/m logic CMOS process. The measured results ascertain that the read induced read failure is suppressed significantly by CADF. The CADF ROM also reduced 86.2% and 94.5% in power consumption and standby current compared to the conventional ROM, respectively.     

CMOS chip for invasive ultrasound imaging

A very small transmit/receiver chip has been developed for use in an arterial ultrasonic imaging system. In this technique, a solid-state ultrasonic imaging head placed within a small medical catheter is used to provide high quality 360° images of arteries as small as 2 mm in diameter. Novel design and packaging techniques have been used to allow four easily testable 0.86 mm×1.65 mm mixed-signal CMOS die to be placed on a multichip carrier within this 1.83 mm diameter imaging probe. Each chip contains interface circuitry for sixteen transducers including 20 MHz transmit pulsers and receive current amplifiers with approximately 1.3 pA/rt-Hz equivalent input noise performance. The techniques described here are generally applicable to any probe or device with extreme size and performance requirements     

Cross-spectral densities of array elements for folded dipole and loop antennas

When a loop or folded dipole antenna is placed in a noise field the resultant mean-square noise current is a function of the cross-spectral densities between the different segments of the antenna. Earlier work on the evaluation of cross-spectral densities between the collinear segments of a dipole placed in an isotropic noise field is here extended to include the parallel and orthogonal segments of rectangular loop and folded dipole antennas.     

Shared word line DRAM cell

A novel memory cell which has a 2-to-1 cell packaging density advantage relative to a conventional one-device (1D) dynamic RAM cell is described. In the shared word line (SWL) DRAM cell, a pair of cells is connected to the same bit sense line and word line. Unique read and write operations are accomplished by controlling the plate of the storage capacitor. The arrangement of cell pairs also provides a sense amplifier pitch of about six times the average feature size; this greatly relaxes the bit line pitch limitation on sense amplifier layout. The cell layout is fully self-aligned using a process very similar and not significantly more complex than conventional double-polysilicon processes. The cell requires neither contact holes nor metal lines. While the access time of the SWL cell is similar to a 1D cell, the cycle time is somewhat longer due to a more complex write operation.     

Multiple twisted dataline techniques for multigigabit DRAMs

To provide reliable scaled DRAMs, new multiple twisted dataline techniques are proposed and analyzed. Their effectiveness in reducing both the bitline (BL) and wordline (WL) coupling noises in scaled DRAM's was evaluated by means of soft-error-rate measurements on 256-Mbit and 1-Gbit DRAM test chips. At the 1-Gbit level of integration, in our proposed scheme-compared to the conventional twisted bitline (TBL) scheme-the chip area penalty due to twisting is reduced by 66% and the BL coupling noise is reduced by 45%. At the 256-Mbit level, when the proposed technique is applied to both the BL and WL structures, we achieved a 64% coupling noise reduction compared to the conventional TBL and WL schemes. Faster data access time can also be expected when the proposed technique is applied to BL and/or WL structures     

Monolithic analog READ-ONLY memory for character generation

Two novel circuit techniques are used. One is a compact analog memory element that is able to store a pair of coordinate values; eighty such elements can be placed on a 65/spl times/65 mil die. The other is a scanning technique that utilizes a resistive ladder network coupled to an array of common- emitter transistors, having obvious applications in other areas, for example as an analog-digital converting technique.     

A 146-mm/sup 2/ 8-gb multi-level NAND flash memory with 70-nm CMOS technology

An 8-Gb multi-level NAND Flash memory with 4-level programmed cells has been developed successfully. The cost-effective small chip has been fabricated in 70-nm CMOS technology. To decrease the chip size, a one-sided pad arrangement with compacted core architecture and a block address expansion scheme without block redundancy replacement have been introduced. With these methods, the chip size has been reduced to 146 mm/sup 2/, which is 4.9% smaller than the conventional chip. In terms of performance, the program throughput reaches 6 MB/s at 4-KB page operation, which is significantly faster than previously reported and very competitive with binary Flash memories. This high performance has been achieved by the combination of the multi-level cell (MLC) programming with write caches and with the program voltage compensation technique for neighboring select transistors. The read throughput reaches 60 MB/s using 16I/O configuration.     

Image restoration using truncated SVD filter bank based on an energy criterion

Image restoration is formulated using a truncated singular-value-decomposition (SVD) filter bank. A pair of known data patterns is used for identifying a small convolution operator. This is achieved by matrix pseudo-inversion based on SVD. Unlike conventional approaches, however, here SVD is performed upon a data-pattern matrix that is much smaller than the image size, leading to an enormous saving in computation. Regularisation is realised by first decomposing the operator into a bank of sub-filters, and then discarding some high-order ones to avoid noise amplification. By estimating the noise spectrum, sub-filters that produce noise energy more than that of useful information are abandoned. Therefore high-order components in the spectrum responsible for noise amplification are rejected. With the obtained small kernel, image restoration is implemented by convolution in the space domain. Numerical results are given to show the effectiveness of the proposed technique     

Highly Scalable Embedded Flash Memory With Deep Trench Isolation and Novel Buried Bitline Integration for the 90-nm Node and Beyond

In this paper, we embedded a Flash memory cell with 90-nm ground-rules in a high-performance CMOS logic process. A novel deep trench isolation (DTI) module enables an isolated p-well (IPW) bias scheme, leading to Flash with uniform channel program/erase by Fowler-Nordheim tunneling without gate induced drain leakage, a key feature for low-power portable electronics. The IPW concept leads to a compact cell design and a highly scalable high-voltage periphery through the narrow intrawell and interwell isolation spaces. The memory arrays are defined by DTI of each bitline (BL) from its neighboring BLs. We additionally present a buried BL (BBL) concept that links the source contacts of each individual BL via the IPW; thus, effectively eliminating one metal line per BL and reducing overall cell size. A conservative cell size shrink of about 40% can be achieved for a uniform channel program/erase-Flash cell with deep trench and BBL compared to a conventional 21F²cell.     

Soft-error-immune switched-load-resistor memory cell

A soft-error-immune switched-load-resistor memory cell especially suitable for ultrahigh-speed bipolar RAM has been developed. The memory cell is composed of upward sidewall base contact structure (SICOS) transistors and shielded Schottky-barrier diodes (SBDs). Alpha-particle-induced noise charges generated in the p^--substrate are completely shielded by n⁺-buried layers of the transistors and the SBDs. Only the noise charges generated in the transistors or the SBDs active regions are gathered in the collectors of the memory cell. The maximum collected noise charge is reduced to a quarter of that of conventional memory cells using SICOS downward transistors and conventional SBDs. Experiments show that this reduction of the collected noise charge increases soft-error immunity to more than 10⁵ times that of conventional memory cells. This result using hot radiation sources does not directly correspond to the real soft-error rate in the field, but demonstrates the realization of an ultrahigh-speed soft-error-immune memory cell     

A multiplexer-based architecture for high-density, low-power gatearrays

This paper presents a novel architecture that provides higher density and lower power dissipation than conventional basecells. The layout of transistors in this small basecell allows the efficient construction of multiplexers with minimal use of programmable layers. The multiplexer can be used to create any 2 input and some 3 input functions in one basecell. Internal fanout, rather than typical output load, defines the size of driver and multiplexer transistors, which can be independently tailored for the desired speed/area/power target. This basecell, which is well suited for implementing datapath elements, has been used to create a 16×16-b multiplier operating at 50 MHz in 314500 μm² in 0.6 μm technology