高速光突发模式接收机设计

介绍了一种高速光突发模式接收机.其中整形电路采用直流耦合跨阻抗前馈式结构,突发同步恢复电路采用一种新颖的固定相位调节振荡器.仿真表明:在速率为1.25Gb/s、误码率BER≤10-9时,接收灵敏度为25dBm,动态范围可高达24 dB,并且可在10ps之内建立比特同步.     

5Gb/s高速光突发模式CDR电路设计

提出了一种结构简单、高速率的光突发模式时钟、数据恢复(CDR)电路。由系统仿真结果表明对速率为5Gb/s的NRZ突发数据可在10ps之内建立比特同步。     

具有APD-TIA光模块的饱和光功率偏低研究

GPON ONU用光接收模块的光接收灵敏度和饱和光功率分别要求-28dBm和-8dBm。测试表明,具有2.5Gb/s APD-TIA光接收模块在25℃和85℃下接收光灵敏度和饱和光功率一般没问题,但在-40℃下,部分模块饱和光功率低于-8dBm。分析指出,饱和光功率偏低,主要与APD的结构、温度特性以及TIA、AGC性能有关。     

一种应用于长距接入网的新型全光均衡器

提出一种新型的自适应突发信号均衡技术,并将其应用于基于10G EPON的长距离波分时分混合复用无源光网络系统.该技术基于SOA的交叉增益特性,通过动态调整泵浦光的功率来控制SOA的增益,实现了全光域突发信号的功率均衡,具有响应速率高、功率补偿精确的优点,避免使用技术尚未成熟的10Gb/s突发接收机.     

高速光传输中双二进制调制解调系统

提出一种利用逻辑器件搭建的高速双二进制调制(Duo-Binary Modulation,DBM)系统,简述了双二进制调制理论并介绍了新的平台设计方案,实现了在25km标准单模光纤上实时传输速率为10.3125Gb/s的光信号.实验中采用高速误码仪进行检测,实验结果表明,该系统在离线时能实现零误码,在接收光功率为-10dBm时误码率小于10-7.     

突发模式光接收技术及其进展

首先介绍了用于IEEE802．3avEPON10Gbit／s具有复位功能的直流耦合突发模式光接收机的构成、原理和性能。接着阐述了交流耦合突发模式光接收机的机理,介绍了用于IEEE802．3ahEPON的1．25Gbit／s交流耦合突发模式APD光接收机的结构和性能。随后简述了2．5Gbit／s边检测突发模式GPON光接收机的原理和性能。最后给出近年来在文献上报道的一些10Gbit／sPONOLT光突发模式接收机的技术指标和采用的技术。     

OBS路由器中交流耦合突发模式光接收机的设计方法

基于拓展带宽的设计方法,提出一种适于OBS的交流耦合突发模式光接收机设计方法.分析与仿真证明该方法有效地降低由交流耦合电容引入的功率代价,并降低系统对信号频谱中低频成分的限制.在1.25Gb/s的信道速率下,本设计在300ns内实现信道同步,并达到很好的灵敏度指标,打破了交流耦合突发接收机在高速应用中的局限.     

1．25 Gbit／s突发模式光发射机设计

本文分析了光突发交换(OBS)和无源光网络(PON)网络中突发模式光发射的关键技术，提出了采用外调制方式实现1．25Gb/s突发模式光发射机的设计方案；其核心部件为分市反馈式（DFB)半导体激光器和电吸收(EA)调制器集成器件。论证了实现突发模式光发射机的调制方式和及其主要技术指标。     

40GbE和100GbE测试解决方案

DSA8200数字串行分析仪配合新推出的光采样示波器模块80C10B和80C25GBE,可有效降低高性能光发射机开发和标准一致性测试的成本。80C10B及选配了F1选件的80C10BF1为下一代40Gb／s和100Gb／s及以上发射机标准的一致性验证,提供了完整的测试解决方案。80C25GBE模块可满足100Gb／s以太网（100GbE）的制造和一致性验证需求。     

卷积码在光正交频分复用系统中的应用

将卷积码成功地应用到直接检测的光正交频分复用(OFDM)光纤传输实验系统。实验中,产生了2 Gb/s的QPSK OFDM编码光信号,并成功地在标准单模光纤中传输了200 km,和没有采用卷积码的相比,系统的误码性能获得明显提高。在误码率10-3时,可节省1 dBm左右的光功率。实验结果表明,卷积码可应用到OFDM系统。     

High-speed, burst-mode, packet-capable optical receiver andinstantaneous clock recovery for optical bus operation

This paper describes an enhanced performance version of a high-speed burst-mode compatible optical receiver and its application to 622-Mb/s optical bus operation in conjunction with an instantaneous clock recovery scheme. The receiver is fabricated in a 12 GHz f_t silicon bipolar technology and consists of a differential transimpedance amplifier with an auto-threshold level controller and a high-speed quantizer. Using an InGaAs avalanche photodiode, the typical burst mode sensitivity is around -34 dBm (10^-9 BER) at bit rates up to 1.5 Gb/s with a dynamic range of 26 db for both pseudorandom and burst signals. The results using a laser beam modulated by a high-speed external modulator indicate that the receiver can be operated at bit rates higher than 2 Gb/s. With a worst-case self-resetting time <50 ns for the threshold control circuit, the receiver is usable for optical packet communication where data signals with varying optical power are employed. This receiver was demonstrated in a 622-Mb/s optical bus application where the clock signal was recovered from the packet data signal using a novel high-speed CMOS instantaneous clock recovery IC     

Optical digital transmission of HDTV signals for `contribution' use

The key technologies for a 1.2 Gb/s HDTV optical digital transmission system for contribution service use are addressed. A wide-dynamic-range optical receiver is described. Attained average received optical power for an error rate of 10^-9 was from -6 dBm to -38 dBm, with an optical dynamic range of 32 dB. This system provides for transmission lengths from a few meters to up to 80 km. It was confirmed that the system developed is available for interconnecting HDTV equipment within a studio and for dispatching HDTV programs from a production site to a postproduction studio. Scrambled-8B1C NRZ line coding was used to keep clock recovery reliable in the receiver. The line-coding circuit satisfies the BSI (bit sequence independent) property and can be easily implemented using commercial high speed ECL devices     

DC-1 Gb/s burst-mode compatible receiver for optical busapplications

The characteristics and performance of a high-speed, burst-mode compatible receiver for optical bus or packet communications are described. It employs an Si bipolar differential transimpedance amplifier, an auto-threshold tracking level control circuit, and a DC-coupled decision circuit (ECL compatible quantizer). To cope with intermittent data packets, the threshold control circuit can capture data amplitude and set the logic threshold in about 1 ns. Using an avalanche photodiode, the typical receiver sensitivity is -37.5 dBm (10 ^-9 BER) at bit rates up to 900 Mb/s, with a dynamic range of 23 dB for both pseudorandom and burst-mode signals. At 1 Gb/s, the sensitivity is -35 dBm. With a worst-case reset time <100 ns for the threshold control circuit, this receiver can be used for optical bus applications where data signals with varying optical power are employed     

Gigabit receiver ICs for optical communications

The authors discuss gigabit receiver ICs for optical communications, focusing on their circuit and package design, the performance of receivers that were fabricated, and their application to a 1.6 Gb/s optical receiver. The key technologies for the receivers are discussed, and a design based on these key technologies is proposed. The proposed design is used to fabricate six receiver ICs (eight chips) using an ultra-high-speed bipolar process with transistors having a unity gain bandwidth of 6-8 GHz. The receivers are suitable for long-haul optical transmission at bit rates up to 1.6 Gb/s. Experimental results show that the 1.6 Gb/s receiver has an optical dynamic range of more than 23 dB without any adjustment, and the received average optical power required to maintain a 10^-11 error rate is less the -31 dBm     

An integrated 0.35 μm CMOS optical receiver with clock and data recovery circuit

This paper presents an integrated optical receiver that operates at 1 Gb/s in a standard 0.35 μm digital CMOS technology. The receiver consists of an integrated CMOS photodetector, a transimpedance amplifier (TIA) followed by a post-amplification stage and a dual-loop clock and data recovery (CDR) circuit. At a wavelength of 860 nm, the circuit requires an average light input power of −19.7 dBm to obtain a bit-error rate (BER) of 10⁻¹². The complete receiver consumes a total power of approximately 155 mW from a 3.3-V supply. The core circuit area is 0.85×1.32 mm².     

High-speed monolithically integrated silicon photoreceivers fabricated in 130-nm CMOS technology

A complementary metal-oxide-semiconductor (CMOS) monolithically integrated photoreceiver is presented. The circuit was fabricated in a 130-nm unmodified CMOS process flow on 2-/spl mu/m-thick silicon-on-insulator substrates. The receiver operated at 8 Gb/s with 2-dBm average input optical power and a bit error rate of less than 10/sup -9/. The integrated lateral p-i-n photodetector was simultaneously realized with the amplifier and had a responsivity of 0.07 A/W at 850 nm. The measured receiver sensitivities at 5, 3.125, 2, and 1 Gb/s, were -10.9, -15.4, -16.5, and -19 dBm, respectively. A 3-V single-supply operation was possible at bit rates up to 3.125 Gb/s. The transimpedance gain of the receivers was in the range 53.4-31 dB/spl Omega/. The circuit dissipated total power between 10 mW and 35 mW, depending on the design.     

2.5Gb/s Ga As MESFET定时判决电路

设计了 2 .5 Gb/ s光纤通信用耗尽型 Ga As MESFET定时判决电路 .通过 SPICE模拟表明恢复的时钟频率达2 .5 GHz,判决电路传输速率达 2 .5 Gb/ s.实验证明经时钟信号抽样后判决电路可产生正确的数字信号 ,传输速率达 2 .5 Gb/ s     

High-level fluctuation tolerant optical receiver for optical packetswitch and WDM cross-connect

This paper proposes a high-level fluctuation tolerant optical receiver for optical packet switches and WDM cross-connects. We describe the tolerance of an experimental receiver to packet-level fluctuation and coherent crosstalk. The sensitivity of the experimental receiver was -26.9 dBm for the packet receiver configuration and -32.7 dBm for the WDM cross-connect configuration at the bit rate of 10 Gb/s. In the setup for level-fluctuating packet reception, the power-penalties of 1.1 and 4.6 dB were observed with 6 and 10 dB of fluctuation, respectively. As a WDM cross-connect, the sensitivity penalties of the receiver under the coherent crosstalk powers of -15 and -12 dB were 2.5 and 6.5 dB, respectively     

Semiconductor laser diode optical amplifiers/gates in photonicpacket switching

In this paper, we will describe how semiconductor laser diode optical amplifiers/gates can be used in the photonic packet switching systems based on wavelength division multiplexed (WDM) techniques. First, we show that cross-gain modulation (XGM) can be suppressed when the device is used in the transparent condition of the waveguide material even when the input signal power exceeds +18 dBm. We then discuss an appropriate encoding for the optical signal. Experimental results show that high bit rate Manchester-encoding enables the use of semiconductor laser diode optical amplifiers/gates in the gain condition as well as the transparent condition. Finally, a new photonic packet receiver which utilizes a semiconductor laser diode optical amplifier as a packet power equalizer is proposed. This receiver accepts 17 dB power fluctuation at nanosecond speed for 10 Gb/s Manchester-encoded signal     

40-to-10-Gb/s demultiplexing using an electro-absorption sampling window

The demultiplexing experiment from a 40 Gb/s optical time-division multiplexing signal is completed by using electro- absorption sampling window based on electronic phase-locked loop circuit for clock recovery. Error-free demultiplexing is achieved when the launched optical power into electro-absorption sampling window reaches 5.5 dBm without optical filter following the EDFA.