反应离子刻蚀氮化硅过程的损伤研究

针对反应离子刻蚀氮化硅过程中无图形60 nm栅氧的等离子体损伤问题进行了研究.采用接触电势差技术研究了反应刻蚀中电荷在硅片表面上的沉积,利用非接触式CV测试技术研究了Si/SiO2界面态的变化.研究表明,电荷沉积与Si/SiO2界面态密度增加有较好的对应关系,电荷沉积较多的区域具有更高的界面态密度.然而,电荷沉积量与界面态密度不成正比例.     

新的正向栅控二极管技术分离热载流子应力诱生SOI NMOSFET界面陷阱和界面电荷的研究

报道了用新的正向栅控二极管技术分离热载流子应力诱生的SOI-MOSFET界面陷阱和界面电荷的理论和实验研究.理论分析表明:由于正向栅控二极管界面态R-G电流峰的特征,该峰的幅度正比于热载流子应力诱生的界面陷阱的大小,而该峰的位置的移动正比于热载流子应力诱生的界面电荷密度. 实验结果表明:前沟道的热载流子应力在前栅界面不仅诱生相当数量的界面陷阱,同样产生出很大的界面电荷.对于逐渐上升的累积应力时间,抽取出来的诱生界面陷阱和界面电荷密度呈相近似的幂指数方式增加,指数分别为为0.7 和0.85.     

新的正向栅控二极管技术分离热载流子应力诱生SOI NMOSFET界面陷阱和界面电荷的研究

报道了用新的正向栅控二极管技术分离热载流子应力诱生的SOI-MOSFET界面陷阱和界面电荷的理论和实验研究.理论分析表明:由于正向栅控二极管界面态R-G电流峰的特征,该峰的幅度正比于热载流子应力诱生的界面陷阱的大小,而该峰的位置的移动正比于热载流子应力诱生的界面电荷密度. 实验结果表明:前沟道的热载流子应力在前栅界面不仅诱生相当数量的界面陷阱,同样产生出很大的界面电荷.对于逐渐上升的累积应力时间,抽取出来的诱生界面陷阱和界面电荷密度呈相近似的幂指数方式增加,指数分别为为0.7 和0.85.     

施主型界面态引起槽栅PMOSFET性能退化的特征

基于流体动力学能量输运模型,对沟道杂质浓度不同的深亚微米槽栅和平面PMOSFET中施主型界面态引起的器件特性的退化进行了研究.研究结果表明同样浓度的界面态密度在槽栅器件中引起的器件特性的漂移远大于平面器件,且电子施主界面态密度对器件特性的影响远大于空穴界面态.特别是沟道杂质浓度不同,界面态引起的器件特性的退化不同.沟道掺杂浓度提高,同样的界面态密度造成的漏极特性漂移增大.     

施主型界面态引起槽栅PMOSFET性能退化的特征

基于流体动力学能量输运模型 ,对沟道杂质浓度不同的深亚微米槽栅和平面 PMOSFET中施主型界面态引起的器件特性的退化进行了研究 .研究结果表明同样浓度的界面态密度在槽栅器件中引起的器件特性的漂移远大于平面器件 ,且电子施主界面态密度对器件特性的影响远大于空穴界面态 .特别是沟道杂质浓度不同 ,界面态引起的器件特性的退化不同 .沟道掺杂浓度提高 ,同样的界面态密度造成的漏极特性漂移增大 .     

利用弛豫谱技术对界面陷阱密度和其能量分布的研究

基于界面陷阱的定义,通过分别对亚阈值摆幅漂移和亚阈区栅电压漂移采用弛豫谱技术有效地提取了1.9nm MOS结构中的界面陷阱密度和它的能量分布.发现这两种方法提取的界面陷阱密度的能量分布是自洽的,同时也与文献报道的DCIV等方法的结果是一致的.与其它的提取方法相比,采用弛豫谱技术的这两种方法更加简单和方便.     

利用弛豫谱技术对界面陷阱密度和其能量分布的研究

基于界面陷阱的定义 ,通过分别对亚阈值摆幅漂移和亚阈区栅电压漂移采用弛豫谱技术有效地提取了1.9nm MOS结构中的界面陷阱密度和它的能量分布 .发现这两种方法提取的界面陷阱密度的能量分布是自洽的 ,同时也与文献报道的 DCIV等方法的结果是一致的 .与其它的提取方法相比 ,采用弛豫谱技术的这两种方法更加简单和方便 .     

施主型界面态引起深亚微米槽栅PMOS特性的退化

基于流体动力学能量输运模型,对沟道杂质浓度不同的槽栅和平面PMOSFET中施主型界面态引起的器件特性的退化进行了研究,并与受主型界面态的影响进行了对比.研究结果表明同样浓度的界面态在槽栅器件中引起的器件特性的漂移远大于平面器件,且N型施主界面态密度对器件特性的影响远大于P型界面态,N型施主界面态引起器件特性的退化趋势与P型受主界面态相似,而P型施主界面态则与N型受主界面态相似.沟道杂质浓度不同,界面态引起的器件特性的退化则不同.     

施主型界面态引起深亚微米槽栅PMOS特性的退化

基于流体动力学能量输运模型 ,对沟道杂质浓度不同的槽栅和平面 PMOSFET中施主型界面态引起的器件特性的退化进行了研究 ,并与受主型界面态的影响进行了对比 .研究结果表明同样浓度的界面态在槽栅器件中引起的器件特性的漂移远大于平面器件 ,且 N型施主界面态密度对器件特性的影响远大于 P型界面态 ,N型施主界面态引起器件特性的退化趋势与 P型受主界面态相似 ,而 P型施主界面态则与 N型受主界面态相似 .沟道杂质浓度不同 ,界面态引起的器件特性的退化则不同     

金属-二氧化硅-半导体(MOS)结构的电子辐照效应

金属.二氧化硅-半导体(MOS)结构对于SiO2-Si界面非常敏感,能够方便地反映出氧化层电荷、界面态密度等参数.为了研究MOS结构的电子辐照效应,采取了能量为0.8 MeV,辐照剂量范围为2×1013～1×1014cm-2屯的电子束作为辐照源.实验发现,MOS结构经电子辐照后,在SiO2-Si界面处引入界面态,并且在二氧化硅内部积累正电荷.通过对MOS结构在电子辐照前后高、低频C-V曲线的测试,测试出辐照在氧化层引入的界面态密度达到了1014cm-2eV-1,而积累的正电荷面密度达到了10-2cm-2.同时得到了界面态密度和积累电荷密度与辐照剂量的关系.     

Minority carrier lifetimes in HgCdTe alloys

We present the results of full band structure calculations of Fermi levels, intrinsic carrier densities, and one-photon absorption coefficients in undoped HgCdTe alloys. The full band structure is used in the calculation of majority and minority carrier densities and the minority carrier lifetimes limited by radiative, Auger-1, and Auger-7 mechanisms in both n- and p-doped alloys. The lifetimes we predicted differ substantially from those calculated with widely used analytical expressions, except in cases where the hole density is small. This difference originates from the significantly non-parabolic and anisotropic valence bands, which are of increasing significance as the hole density increases. From a comparison of the calculated and measured lifetimes, we deduce that the lifetimes at low temperatures are limited by the Shockley-Read-Hall (SRH) recombination. We have generalized the SRH expression to include Fermi-Dirac statistics, but we still treat the density, energy level, and cross section as adjustable parameters. We find that the calculated radiative and Auger recombination lifetimes, as well as SRH lifetimes, can fit the measured lifetimes using traps located (a) near the conduction band edge in n-HgCdTe and (b) near the valence band edge for p-HgCdTe. In addition, the movement of Fermi level with respect to the trap level explains the observed temperature-dependence of the lifetimes. We conclude that there is considerable room for improvement in HgCdTe material quality.     

Interfacial electronic traps in surface controlled transistors

Carrier recombination at interfacial electronic traps under a surface controlling gate electrode is analyzed using the Shockley-Reed-Hall steady-state recombination kinetics to provide a theoretical basis for quantifying the direct-current current-voltage (DCIV) method for monitoring and diagnosis of MOS transistor reliability, design, and manufacturing processes. Analytical expressions for DCIV lineshape, linewidth, peak gate-voltage and peak amplitude are derived for the determination of interface trap densities, energy level, and spatial location. DCIV peaks in the intrinsic to flat band gate-voltage range originate from carrier recombination at interface traps located over the channel region. Additional peaks in the surface accumulation gate-voltage range originate from interface traps covering the gated p-n-junction space-charge region. Effects on the DCIV line shape from minority carrier injection level and diffusion are described. Examples are given for the determination of the quantum density of states of process-residual interface traps of unstressed MOS transistors as well as hot-carrier-generated interface traps of stressed MOS transistors     

Model for minority carrier lifetimes in doped HgCdTe

We calculate the radiative, Auger, and the Shockley-Read-Hall recombination rates with Fermi-Dirac statistics and accurate band structures to explain the measured temperature dependence and doping dependence of minority carrier lifetimes in three n- and one p-type sample. We show that a trap state tracking the conduction band edge with very small activation energy can explain the lifetimes in the n-doped samples considered here. Similarly, for moderately p-doped HgCdTe alloy, a trap level at 75 meV is needed to explain the observed lifetimes. In either case, movement of Fermi level with respect to the trap level explains the temperature dependence of the lifetimes.     

Anti-Stokes' light converter based on graded-band-gap semiconductors

The anti-Stokes' mechanism of photo-excitation in the smaller band-gap region, followed by radiative recombination in the larger band-gap region is considered. For transport by diffusion the additional photon energy originates from thermal energy; for transport in applied electrical fields, from electrical energy. The requirements on band edge gradients, carrier lifetimes, mobilities, and applied field for the photon conversion are analyzed. A graded heterojunction with a position-independent majority carrier density permits the formation of a uniform applied electric field which can enhance the motion of minority carriers into the larger band-gap region.     

Carrier separation analysis for clarifying carrier conduction and degradation mechanisms in high-k stack gate dielectrics

The carrier conduction and the degradation mechanism in n⁺gate p-channel metal-insulator-semiconductor field-effect-transistors with HfAlO_X (Hf: 60 at.%, Al: 40 at.%)/SiO₂ dielectric layers have been investigated using carrier separation method. Since gate current depends on substrate bias and both electron and hole currents are independent of temperature over the range of 25–150 °C, the conduction mechanism for both currents is controlled by a tunneling process. As the interfacial SiO₂ layer (IL) thickness increases in a fixed high-k layer thickness (T_high-k), a dominant carrier in the leakage current changes from hole to electron around 2.2-nm-thick IL. This is due to an asymmetric barrier height for electrons and holes at the SiO₂/Si interface. On the contrary, in the case of a fixed IL thickness of 1.3 nm, the hole current is dominant in the leakage current, regardless of T_high-k. It is shown that the dominant carrier in the leakage current depends on the structure of the high-k stack. Both electron and hole currents for the stress-induced-leakage-current (SILC) state increase slightly relative to the initial currents, which means that the trap generation in the high-k stack occurs near both the conduction band edge of n⁺poly-Si gate and the valence band edge of Si substrate. The electron current at soft breakdown (SBD) state dramatically increases over that for the SILC state, while the hole currents for both the SILC state and SBD are almost the same. This indicates that the defect sites generated in the high-k stack after SBD are located at energies near the conduction band edge of n⁺poly-Si gate. Both the defect generation rate and the defect size in the HfAlO_X/SiO₂ stacks are large compared with those in SiO₂. It is inferred that, in high-k dielectric stack, the defect generation mainly occurs in the high-k side rather than the IL side, and the defect size larger than the case of SiO₂ could be related to a larger dielectric constant of the high-k layer.     

The determination of the interface-state density distribution from the capacitance-frequency measurements in Au/n-Si schottky barrier diodes

The Au/n-Si Schottky barrier diodes (SBDs) with 200-μm (sample D200) and 400-μm (sample D400) bulk thicknesses have been fabricated. The ideality factor and the barrier height have been calculated from the forward-bias current-voltage (I-V) characteristics of D200 and D400 SBDs. The energy distribution of the interface states and relaxation time are found from the capacitance-frequency (C-f) characteristics. The density of interface state and relaxation times have a (nearly constant) slow exponential rise with bias in the range of E_c −0.77 and E_c −0.47 eV from the midgap toward the bottom of the conductance band. Furthermore, the energy distribution of the interface states obtained from C-f characteristics has been compared with that obtained from the forward-bias I-V characteristics.     

Radiative recombination in modulation-doped GaAs/AlGaAs heterostructures in the presence of an electric field

The radiative recombination processes involving two dimensional (2D) carriers from the notch potential formed at the interface of modulation doped GaAs/AlGaAs heterostructures have been studied by means of photoluminescence (PL) and photoluminescence excitation spectroscopy in the presence of an external electric field applied perpendicular to the layers via a gate electrode. Two PL bands related to the 2D electron gas are interpreted as the radiative recombination between 2D electrons and holes from the valence band (HB1) and from residual acceptors (HB2), respectively. The band bending in the active layer, which determines the energy positions of these H-bands, can be controlled by applying an external electric field. However, also the separation between the Fermi edge, E_F, and the second 2D electron subband is deliberately varied by applying an electric field. At a sufficiently small separation, an efficient scattering path near k=0 is available for electrons at the Fermi energy. This can be observed in the PL spectra as a striking enhancement of the many-body excitonic transition, usually referred to as the Fermi edge singularity (FES). The enhancement of the FES is usually explained in terms of an efficient scattering for electrons at the Fermi edge via the nearly resonant adjacent subband. The efficiency of this process is dependent on the separation between the Fermi edge, E_F, and the next subband, which can be controlled via the applied field in our experiments.     

Origin of the threshold voltage instability in SiO/sub 2//HfO/sub 2/ dual layer gate dielectrics

The magnitude of the V/sub T/ instability in conventional MOSFETs and MOS capacitors with SiO/sub 2//HfO/sub 2/ dual-layer gate dielectrics is shown to depend strongly on the details of the measurement sequence used. By applying time-resolved measurements (capacitance-time traces and charge-pumping measurements), it is demonstrated that this behavior is caused by the fast charging and discharging of preexisting defects near the SiO/sub 2//HfO/sub 2/ interface and in the bulk of the HfO/sub 2/ layer. Based on these results, a simple defect model is proposed that can explain the complex behavior of the V/sub T/ instability in terms of structural defects as follows. 1) A defect band in the HfO/sub 2/ layer is located in energy above the Si conduction band edge. 2) The defect band shifts rapidly in energy with respect to the Fermi level in the Si substrate as the gate bias is varied. 3) The rapid energy shifts allows for efficient charging and discharging of the defects near the SiO/sub 2//HfO/sub 2/ interface by tunneling.     

ZnO/p-Si异质结的I-V及C-V特性研究

通过磁控溅射Al掺杂的ZnO陶瓷靶,在p-Si片上沉积n型电导的ZnO薄膜而制备了ZnO/p-Si异质结,并通过测试其光照下的I-V、C-V特性对其光电特性以及载流子输运特性与导电机理进行了研究。研究表明ZnO/p-Si异质结存在良好的整流特性与光电响应,可以广泛应用在光电探测和太阳电池等领域。由于在ZnO/p-Si异质结界面处的导带补偿与价带补偿相差太大的缘故,在正向电压超过1V时,导电机理为空间电荷限制电流导电。同时,研究表明ZnO/p-Si异质结界面存在大量界面态,可以通过减小界面态进一步提高其光电特性。     

Carrier recombination at grain boundaries and the effective recombination velocity

The recombination of excess minority carriers at grain boundaries, or other interfaces with space-charge regions, is treated theoretically for general energy distributions of interface states (recombination centers). The distinction is made between minority carrier recombination velocity at the (grain-boundary) interface itself, and the effective recombination velocity for the collection of these carriers by the adjacent space-charge region. Calculations of the effective recombination velocity are made, as a function of the excess minority-carrier concentration at the edge of the space-charge region, since this is the quantity of most convenience for device modelling.